...
make[1]: Leaving directory '/builddir/build/BUILD/yosys-61324cf55fc5c5237161d4cee157c121fe115fa1/manual/PRESENTATION_ExOth'
+ make -C PRESENTATION_Prog
make[1]: warning: jobserver unavailable: using -j1.  Add '+' to parent make rule.
make[1]: Entering directory '/builddir/build/BUILD/yosys-61324cf55fc5c5237161d4cee157c121fe115fa1/manual/PRESENTATION_Prog'
../../yosys-config --exec --cxx -O2 -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -Wall -Wextra -ggdb -I/usr/include/yosys -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++11 -Os -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -I../.. --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
my_cmd.cc: In member function 'virtual void {anonymous}::MyPass::execute(std::vector<std::__cxx11::basic_string<char> >, Yosys::RTLIL::Design*)':
my_cmd.cc:17:26: warning: format '%zd' expects argument of type 'signed size_t', but argument 3 has type 'int' [-Wformat=]
   17 |             log("  %s (%zd wires, %zd cells)\n", log_id(mod),
      |                        ~~^
      |                          |
      |                          long int
      |                        %d
   18 |                     GetSize(mod->wires()), GetSize(mod->cells()));
      |                     ~~~~~~~~~~~~~~~~~~~~~
      |                            |
      |                            int
my_cmd.cc:17:37: warning: format '%zd' expects argument of type 'signed size_t', but argument 4 has type 'int' [-Wformat=]
   17 |             log("  %s (%zd wires, %zd cells)\n", log_id(mod),
      |                                   ~~^
      |                                     |
      |                                     long int
      |                                   %d
   18 |                     GetSize(mod->wires()), GetSize(mod->cells()));
      |                                            ~~~~~~~~~~~~~~~~~~~~~
      |                                                   |
      |                                                   int
../../yosys -Ql test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' absval_ref.v
-- Parsing `absval_ref.v' using frontend ` -vlog2k' --
1. Executing Verilog-2005 frontend: absval_ref.v
Parsing Verilog input from `absval_ref.v' to AST representation.
Storing AST representation for module `$abstract\absval_ref'.
Successfully finished Verilog frontend.
-- Running command `my_cmd foo bar' --
Arguments to my_cmd:
  my_cmd
  foo
  bar
Modules in current design:
  $abstract\absval_ref (0 wires, 0 cells)
End of script. Logfile hash: a25069ff9d, CPU: user 0.00s system 0.00s, MEM: 11.91 MB peak
Yosys 0.13+3 (git sha1 UNKNOWN, gcc 11.2.1 -O2 -fexceptions -fstack-protector-strong -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fPIC -Os)
Time spent: 94% 2x read_verilog (0 sec), 3% 1x my_cmd (0 sec), ...
mv test0.log_new test0.log
../../yosys -Ql test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' absval_ref.v
-- Parsing `absval_ref.v' using frontend ` -vlog2k' --
1. Executing Verilog-2005 frontend: absval_ref.v
Parsing Verilog input from `absval_ref.v' to AST representation.
Storing AST representation for module `$abstract\absval_ref'.
Successfully finished Verilog frontend.
-- Running command `clean; test1; dump' --
Name of this module: absval
autoidx 4
module \absval
  wire width 4 $auto$my_cmd.cc:41:execute$1
  wire width 4 output 2 \y
  wire width 4 input 1 \a
  cell $mux $auto$my_cmd.cc:43:execute$3
    parameter \WIDTH 4
    connect \Y \y
    connect \S \a [3]
    connect \B $auto$my_cmd.cc:41:execute$1
    connect \A \a
  end
  cell $neg $auto$my_cmd.cc:42:execute$2
    parameter \Y_WIDTH 4
    parameter \A_WIDTH 4
    parameter \A_SIGNED 1
    connect \Y $auto$my_cmd.cc:41:execute$1
    connect \A \a
  end
end
attribute \cells_not_processed 1
attribute \src "absval_ref.v:1.1-3.10"
module $abstract\absval_ref
end
End of script. Logfile hash: 01cda1039c, CPU: user 0.01s system 0.00s, MEM: 11.89 MB peak
Yosys 0.13+3 (git sha1 UNKNOWN, gcc 11.2.1 -O2 -fexceptions -fstack-protector-strong -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fPIC -Os)
Time spent: 73% 1x clean (0 sec), 18% 2x read_verilog (0 sec), ...
mv test1.log_new test1.log
../../yosys -Ql test2.log_new -m ./my_cmd.so -p 'test2' sigmap_test.v
-- Parsing `sigmap_test.v' using frontend ` -vlog2k' --
1. Executing Verilog-2005 frontend: sigmap_test.v
terminate called after throwing an instance of 'std::out_of_range'
  what():  dict::at()
make[1]: *** [Makefile:19: test2.log] Aborted (core dumped)
make[1]: Leaving directory '/builddir/build/BUILD/yosys-61324cf55fc5c5237161d4cee157c121fe115fa1/manual/PRESENTATION_Prog'
make: *** [Makefile:897: manual] Error 2