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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.std_logic_unsigned.all;
- entity primer1_tb is
- end entity;
- architecture primer1_tb of primer1_tb is
- signal sA : std_logic_vector(2 downto 0);
- signal sB : std_logic_vector(4 downto 0);
- signal sC : std_logic_vector(7 downto 0);
- signal sSEL : std_logic_vector(3 downto 0);
- signal sRESULT : std_logic_vector(7 downto 0);
- component primer1
- port(
- iA : in std_logic_vector(2 downto 0);
- iB : in std_logic_vector(4 downto 0);
- iC : in std_logic_vector(7 downto 0);
- iSEL : in std_logic_vector(3 downto 0);
- oRESULT : out std_logic_vector(7 downto 0)
- );
- end component;
- begin
- uut : primer1 port map(
- iA => sA,
- iB => sB,
- iC => sC,
- iSEL => sSEL,
- oRESULT => sRESULT
- );
- stimulus: process
- begin
- sA <= "101";
- sB <= "00000";
- sC <= "00000000";
- sSEL <= "1000";
- wait for 100 ns;
- sA <= "000";
- sB <= "01100";
- sC <= "00000000";
- sSEL <= "0100";
- wait for 100 ns;
- sA <= "000";
- sB <= "00000";
- sC <= "01010101";
- sSEL <= "0010";
- wait for 100 ns;
- sA <= "000";
- sB <= "00000";
- sC <= "10000000";
- sSEL <= "0000";
- wait;
- end process stimulus;
- end architecture;
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