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Dec 14th, 2019
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.std_logic_unsigned.all;
  4.  
  5. entity primer1_tb is
  6. end entity;
  7.  
  8. architecture primer1_tb of primer1_tb is
  9.  
  10. signal sA : std_logic_vector(2 downto 0);
  11. signal sB : std_logic_vector(4 downto 0);
  12. signal sC : std_logic_vector(7 downto 0);
  13. signal sSEL : std_logic_vector(3 downto 0);
  14. signal sRESULT : std_logic_vector(7 downto 0);
  15.  
  16. component primer1
  17. port(
  18. iA : in std_logic_vector(2 downto 0);
  19. iB : in std_logic_vector(4 downto 0);
  20. iC : in std_logic_vector(7 downto 0);
  21. iSEL : in std_logic_vector(3 downto 0);
  22. oRESULT : out std_logic_vector(7 downto 0)
  23. );
  24.  
  25. end component;
  26.  
  27. begin
  28.  
  29. uut : primer1 port map(
  30. iA => sA,
  31. iB => sB,
  32. iC => sC,
  33. iSEL => sSEL,
  34. oRESULT => sRESULT
  35. );
  36.  
  37. stimulus: process
  38. begin
  39.  
  40. sA <= "101";
  41. sB <= "00000";
  42. sC <= "00000000";
  43. sSEL <= "1000";
  44.  
  45. wait for 100 ns;
  46.  
  47. sA <= "000";
  48. sB <= "01100";
  49. sC <= "00000000";
  50. sSEL <= "0100";
  51.  
  52. wait for 100 ns;
  53.  
  54. sA <= "000";
  55. sB <= "00000";
  56. sC <= "01010101";
  57. sSEL <= "0010";
  58.  
  59. wait for 100 ns;
  60.  
  61. sA <= "000";
  62. sB <= "00000";
  63. sC <= "10000000";
  64. sSEL <= "0000";
  65.  
  66. wait;
  67.  
  68. end process stimulus;
  69. end architecture;
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