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  6. Sun Apr 19, 2020 14:03:44: IAR Embedded Workbench 8.32.1 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll)
  7. Sun Apr 19, 2020 14:03:44: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32H7xx.dmac
  8. Sun Apr 19, 2020 14:03:44: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32H7xx_DBG.dmac
  9. Sun Apr 19, 2020 14:03:44: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32H7xx_OB.dmac
  10. Sun Apr 19, 2020 14:03:44: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\ST\STM32H7xx_TRACE.dmac
  11. Sun Apr 19, 2020 14:03:44: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx.mac
  12. Sun Apr 19, 2020 14:03:44: JLINK command: ProjectFile = C:\projects\mcu\version\STM32Cube_FW_H7_V1.3.0\Projects\STM32H743I_EVAL\Examples\GPIO\GPIO_EXTI\EWARM\settings\Project_STM32H743I_EVAL.jlink, return = 0
  13. Sun Apr 19, 2020 14:03:44: Device "STM32H743XI" selected.
  14. Sun Apr 19, 2020 14:03:44: DLL version: V6.70c, compiled Apr 7 2020 16:25:12
  15. Sun Apr 19, 2020 14:03:44: Firmware: J-Trace PRO V2 Cortex compiled Mar 19 2020 11:14:52
  16. Sun Apr 19, 2020 14:03:44: JTAG speed is fixed to: 100 kHz
  17. Sun Apr 19, 2020 14:03:44: TotalIRLen = 9, IRPrint = 0x0011
  18. Sun Apr 19, 2020 14:03:44: JTAG chain detection found 2 devices:
  19. Sun Apr 19, 2020 14:03:44: #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
  20. Sun Apr 19, 2020 14:03:44: #1 Id: 0x06450041, IRLen: 05, Unknown device
  21. Sun Apr 19, 2020 14:03:44: TotalIRLen = 9, IRPrint = 0x0011
  22. Sun Apr 19, 2020 14:03:44: JTAG chain detection found 2 devices:
  23. Sun Apr 19, 2020 14:03:44: #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
  24. Sun Apr 19, 2020 14:03:44: #1 Id: 0x06450041, IRLen: 05, Unknown device
  25. Sun Apr 19, 2020 14:03:44: Cannot determine DP version. Assuming DPv0
  26. Sun Apr 19, 2020 14:03:44: Scanning AP map to find all available APs
  27. Sun Apr 19, 2020 14:03:44: AP[3]: Stopped AP scan as end of AP map has been reached
  28. Sun Apr 19, 2020 14:03:44: AP[0]: AHB-AP (IDR: 0x84770001)
  29. Sun Apr 19, 2020 14:03:44: AP[1]: AHB-AP (IDR: 0x84770001)
  30. Sun Apr 19, 2020 14:03:44: AP[2]: APB-AP (IDR: 0x54770002)
  31. Sun Apr 19, 2020 14:03:44: Iterating through AP map to find AHB-AP to use
  32. Sun Apr 19, 2020 14:03:44: AP[0]: Core found
  33. Sun Apr 19, 2020 14:03:44: AP[0]: AHB-AP ROM base: 0xE00FE000
  34. Sun Apr 19, 2020 14:03:44: CPUID register: 0x411FC271. Implementer code: 0x41 (ARM)
  35. Sun Apr 19, 2020 14:03:44: Found Cortex-M7 r1p1, Little endian.
  36. Sun Apr 19, 2020 14:03:44: FPUnit: 8 code (BP) slots and 0 literal slots
  37. Sun Apr 19, 2020 14:03:44: CoreSight components:
  38. Sun Apr 19, 2020 14:03:44: ROMTbl[0] @ E00FE000
  39. Sun Apr 19, 2020 14:03:44: ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB4C7 ROM Table
  40. Sun Apr 19, 2020 14:03:44: ROMTbl[1] @ E00FF000
  41. Sun Apr 19, 2020 14:03:44: ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB00C SCS-M7
  42. Sun Apr 19, 2020 14:03:44: ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB002 DWT
  43. Sun Apr 19, 2020 14:03:44: ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00E FPB-M7
  44. Sun Apr 19, 2020 14:03:44: ROMTbl[1][3]: E0000000, CID: B105E00D, PID: 000BB001 ITM
  45. Sun Apr 19, 2020 14:03:44: ROMTbl[0][1]: E0041000, CID: B105900D, PID: 001BB975 ETM-M7
  46. Sun Apr 19, 2020 14:03:44: ROMTbl[0][2]: E0043000, CID: B105900D, PID: 004BB906 CTI
  47. Sun Apr 19, 2020 14:03:44: Cache: Separate I- and D-cache.
  48. Sun Apr 19, 2020 14:03:44: I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way
  49. Sun Apr 19, 2020 14:03:44: D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way
  50. Sun Apr 19, 2020 14:03:44: Reset: Halt core after reset via DEMCR.VC_CORERESET.
  51. Sun Apr 19, 2020 14:03:44: Reset: Reset device via AIRCR.SYSRESETREQ.
  52. Sun Apr 19, 2020 14:03:44: Hardware reset with strategy 0 was performed
  53. Sun Apr 19, 2020 14:03:44: Initial reset was performed
  54. Sun Apr 19, 2020 14:03:44: Found 2 JTAG devices, Total IRLen = 9:
  55. Sun Apr 19, 2020 14:03:44: #0 Id: 0x6BA00477, IRLen: 4, IRPrint: 0x1 CoreSight JTAG-DP
  56. Sun Apr 19, 2020 14:03:44: #1 Id: 0x06450041, IRLen: 5, Unknown device
  57. Sun Apr 19, 2020 14:03:45: 782 bytes downloaded and verified (2.57 Kbytes/sec)
  58. Sun Apr 19, 2020 14:03:45: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx_512kB.out
  59. Sun Apr 19, 2020 14:03:45: Target reset
  60. Sun Apr 19, 2020 14:03:50: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\ST\FlashSTM32H7xxx.mac
  61. Sun Apr 19, 2020 14:03:50: Downloaded C:\projects\mcu\version\STM32Cube_FW_H7_V1.3.0\Projects\STM32H743I_EVAL\Examples\GPIO\GPIO_EXTI\EWARM\STM32H743I_EVAL\Exe\STM32H743I_EVAL.out to flash memory.
  62. Sun Apr 19, 2020 14:03:50: 10480 bytes downloaded into FLASH (1.83 Kbytes/sec)
  63. Sun Apr 19, 2020 14:03:50: Reset: Halt core after reset via DEMCR.VC_CORERESET.
  64. Sun Apr 19, 2020 14:03:50: Reset: Reset device via AIRCR.SYSRESETREQ.
  65. Sun Apr 19, 2020 14:03:50: Hardware reset with strategy 0 was performed
  66. Sun Apr 19, 2020 14:03:51: 10480 bytes downloaded into FLASH and verified (1.78 Kbytes/sec)
  67. Sun Apr 19, 2020 14:03:51: Loaded debugee: C:\projects\mcu\version\STM32Cube_FW_H7_V1.3.0\Projects\STM32H743I_EVAL\Examples\GPIO\GPIO_EXTI\EWARM\STM32H743I_EVAL\Exe\STM32H743I_EVAL.out
  68. Sun Apr 19, 2020 14:03:51: Reset: Halt core after reset via DEMCR.VC_CORERESET.
  69. Sun Apr 19, 2020 14:03:51: Reset: Reset device via AIRCR.SYSRESETREQ.
  70. Sun Apr 19, 2020 14:03:51: Hardware reset with strategy 0 was performed
  71. Sun Apr 19, 2020 14:03:51: Target reset
  72. Sun Apr 19, 2020 14:03:51: DMAC: DBGMCU_CR was modified. DBGMCU_CR=0x00700107
  73. Sun Apr 19, 2020 14:03:51: DMAC/Trace: Configure Trace Funnel
  74. Sun Apr 19, 2020 14:03:51: DMAC/Trace: Enabling SYSCFG clock ...
  75. Sun Apr 19, 2020 14:03:51: DMAC/Trace: Enabling IO compensation cell ...
  76. Sun Apr 19, 2020 14:03:51: DMAC/Trace: Enabling GPIOE clock ...
  77. Sun Apr 19, 2020 14:03:52: DMAC/Trace: GPIOE 2,3... enabled as ETM (AF0, High Speed)...
  78. Sun Apr 19, 2020 14:03:52: DMAC/Trace: Other than PLL1 clock as CPU clock detected ...
  79. Sun Apr 19, 2020 14:03:52: DMAC/Trace: Trace clock should be 1/2 of CPU clock frequency.
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