ADLD Lab4 Dancing LED

`timescale 1ns / 1ps

module clock(input clk, input reset, output clk_out);

    reg [14:0] ctr;
    assign clk_out = ctr[13];

    always @(posedge clk) begin

        if (reset == 1) ctr = 0;
        else ctr = ctr + 1;

    end

endmodule

module dancingLED(input clk, input reset_clk, input reset_led, output reg [3:0] EN, output reg [7:0] y
    );

    wire clk_out;
    clock cout(clk,reset_clk,clk_out);


    always@(posedge clk_out) begin



        if (reset_led == 1'b1) begin
            EN = 4'b1110;
            y = 8'b11111110;
        end

        else begin
            if (y[7] == 0) EN = (EN << 1) | (EN >> 3);
            y = (y << 1) | (y >> 7);
        end

    end

endmodule