/*
 * Do not change Module name
*/
module main;

initial begin
    sr <= 20'h00001;
    count <= 16'h0;
    #20 $finish;
end

// x19+x18+x16+x13+x12+x10+x9+x6+x5+x4+x2+1 (D3675 hex)
// x19+x16+x11+x10+x5+x3+x2+1 (90C2D hex)

reg [19:0] sr;

wire shift_in = sr[19] ^ sr[18] ^ sr[16] ^ sr[13] ^ sr[12] ^ sr[10] ^                 sr[9] ^ sr[6] ^ sr[5] ^ sr[4] ^ sr[2] ^ sr[0];

//reg clock;

reg [7:0] count;


always #1 begin
//    clock = ~clock;
    count <= count + 1;
    $display("%d: The value in the LFSR is: %h", count, sr);
    sr <= {sr[18:0], shift_in};
end


endmodule