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vrangan

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Jul 3rd, 2022
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  1. /*
  2.  * Finite state machine.
  3.  * If input 'a' is asserted, the state machine
  4.  * moves IDLE->STATE_1->FINAL and remains in FINAL.
  5.  * If 'a' is not asserted, FSM returns to idle.
  6.  * Output 'out1' asserts when state machine is in
  7.  * STATE_1. 'out2' asserts when state machine is in
  8.  * FINAL state.
  9.  */
  10. module fsm (
  11.   input  logic clk ,
  12.   input  logic rst ,
  13.   input  logic a   ,
  14.   output logic out1,
  15.   output logic out2
  16. );
  17.  
  18.   enum {
  19.     IDLE,    // Waiting for the sun to rise
  20.     STATE_1, // Doing a lot of work here!
  21.     FINAL,   // Whew, done, lets go back to Idle
  22.     XXX      // Trap!
  23.   } state, next;
  24.  
  25.   // Next state logic
  26.   always @(posedge clk or posedge rst)
  27.     if (rst) state <= IDLE;
  28.     else     state <= next;
  29.  
  30.   // State transitions and outputs
  31.   always_comb begin
  32.     // Default outputs
  33.     out1 = 0;
  34.     out2 = 0;
  35.     next = XXX;
  36.  
  37.     case (state)
  38.       IDLE : begin
  39.         if (a) state <= STATE_1;
  40.         else   state <= IDLE; // @loopback
  41.       end
  42.  
  43.       STATE_1 : begin
  44.         out1 = 1;
  45.         if (a) state <= FINAL;
  46.         else   state <= IDLE;
  47.       end
  48.  
  49.       FINAL : begin
  50.         out2 = 1;
  51.         if (a) state <= FINAL; // @loopback
  52.         else   state <= IDLE;
  53.       end
  54.  
  55.       default :
  56.         state <= XXX;
  57.     endcase
  58.   end
  59.  
  60. endmodule
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