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Apr 23rd, 2021
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  1.  
  2. coreboot-4.13-3180-g1f3309909f-dirty Fri Apr 16 13:41:38 UTC 2021 bootblock starting (log level: 7)...
  3. CPU: Intel(R) Core(TM) i7-10710U CPU @ 1.10GHz
  4. CPU: ID a0660, Cometlake-U A0 (6+2), ucode: 000000df
  5. CPU: AES supported, TXT NOT supported, VT supported
  6. MCH: device id 9b51 (rev 00) is CometLake-U (6+2)
  7. PCH: device id 0284 (rev 00) is Cometlake-U Premium
  8. IGD: device id 9bca (rev 04) is CometLake ULT GT2
  9. FMAP: Found "FLASH" version 1.1 at 0x490000.
  10. FMAP: base = 0x0 size = 0x1000000 #areas = 7
  11. FMAP: area COREBOOT found @ 490200 (11992576 bytes)
  12. CBFS: mcache @0xfef21400 built for 18 files, used 0x3e8 of 0x2000 bytes
  13. CBFS: Found 'fallback/romstage' @0x80 size 0xddf0 in mcache @0xfef2142c
  14. BS: bootblock times (exec / console): total (unknown) / 69 ms
  15.  
  16.  
  17. coreboot-4.13-3180-g1f3309909f-dirty Fri Apr 16 13:41:38 UTC 2021 romstage starting (log level: 7)...
  18. pm1_sts: 8100 pm1_en: 0100 pm1_cnt: 00001c00
  19. gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
  20. gpe0_sts[1]: 00000800 gpe0_en[1]: 00000000
  21. gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
  22. gpe0_sts[3]: 00000040 gpe0_en[3]: 00000000
  23. TCO_STS: 0000 0000
  24. GEN_PMCON: e0801839 00000200
  25. GBLRST_CAUSE: 00000000 00000000
  26. prev_sleep_state 5
  27. CBFS: Found 'fspm.bin' @0x63dc0 size 0x8e000 in mcache @0xfef2163c
  28. FMAP: area RW_MRC_CACHE found @ 420000 (65536 bytes)
  29. Memory config straps: 0x01
  30. SPD INDEX = 1
  31. CBFS: Found 'spd.bin' @0x5f3c0 size 0x1000 in mcache @0xfef215c8
  32. SPD: module type is DDR4
  33. SPD: module part number is MT40A1G16KD-062E:E
  34. SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
  35. SPD: device width 16 bits, bus width 64 bits
  36. SPD: module size is 8192 MB (per channel)
  37. memory slot: 0 configuration done.
  38. memory slot: 2 configuration done.
  39. CBMEM:
  40. IMD: root @ 0x99ffe000 254 entries.
  41. IMD: root @ 0x99ffdc00 62 entries.
  42. External stage cache:
  43. IMD: root @ 0x9abff000 254 entries.
  44. IMD: root @ 0x9abfec00 62 entries.
  45. FMAP: area RW_MRC_CACHE found @ 420000 (65536 bytes)
  46. MRC: Checking cached data update for 'RW_MRC_CACHE'.
  47. SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  48. MRC: 'RW_MRC_CACHE' does not need update.
  49. 2 DIMMs found
  50. SMM Memory Map
  51. SMRAM : 0x9a000000 0x1000000
  52. Subregion 0: 0x9a000000 0xa00000
  53. Subregion 1: 0x9aa00000 0x200000
  54. Subregion 2: 0x9ac00000 0x400000
  55. top_of_ram = 0x9a000000
  56. MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
  57. MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
  58. MTRR Range: Start=ff000000 End=0 (Size 1000000)
  59. Normal boot
  60. CBFS: Found 'fallback/postcar' @0x121680 size 0x5008 in mcache @0xfef21714
  61. Loading module at 0x99c20000 with entry 0x99c20031. filesize: 0x4cd0 memsize: 0x8ff8
  62. Processing 190 relocs. Offset value of 0x97c20000
  63. BS: romstage times (exec / console): total (unknown) / 189 ms
  64.  
  65.  
  66. coreboot-4.13-3180-g1f3309909f-dirty Fri Apr 16 13:41:38 UTC 2021 postcar starting (log level: 7)...
  67. Normal boot
  68. CBFS: Found 'fallback/ramstage' @0x3e7c0 size 0x2064c in mcache @0x99c4c10c
  69. Loading module at 0x99bb9000 with entry 0x99bb9000. filesize: 0x47480 memsize: 0x655f0
  70. Processing 4384 relocs. Offset value of 0x98db9000
  71. BS: postcar times (exec / console): total (unknown) / 33 ms
  72.  
  73.  
  74. coreboot-4.13-3180-g1f3309909f-dirty Fri Apr 16 13:41:38 UTC 2021 ramstage starting (log level: 7)...
  75. Normal boot
  76. ACPI _SWS is PM1 Index 8 GPE Index -1
  77. BS: BS_PRE_DEVICE entry times (exec / console): 0 / 4 ms
  78. CBFS: Found 'cpu_microcode_blob.bin' @0xdf00 size 0x30800 in mcache @0x99c4c0ac
  79. microcode: sig=0xa0660 pf=0x80 revision=0xdf
  80. Skip microcode update
  81. CBFS: Found 'fsps.bin' @0xf2dc0 size 0x2e85f in mcache @0x99c4c2d4
  82. Detected 6 core, 12 thread CPU.
  83. Setting up SMI for CPU
  84. IED base = 0x9ac00000
  85. IED size = 0x00400000
  86. Will perform SMM setup.
  87. CPU: Intel(R) Core(TM) i7-10710U CPU @ 1.10GHz.
  88. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
  89. Processing 16 relocs. Offset value of 0x00030000
  90. Attempting to start 11 APs
  91. Waiting for 10ms after sending INIT.
  92. Waiting for 1st SIPI to complete...done.
  93. AP: slot 9 apic_id 9, MCU rev: 0x000000df
  94. AP: slot 8 apic_id 8, MCU rev: 0x000000df
  95. AP: slot 2 apic_id 3, MCU rev: 0x000000df
  96. AP: slot 1 apic_id 2, MCU rev: 0x000000df
  97. AP: slot 7 apic_id 6, MCU rev: 0x000000df
  98. AP: slot 6 apic_id 7, MCU rev: 0x000000df
  99. Waiting for 2nd SIPI to complete...AP: slot 3 apic_id 1, MCU rev: 0x000000df
  100. done.
  101. AP: slot 11 apic_id b, MCU rev: 0x000000df
  102. AP: slot 10 apic_id a, MCU rev: 0x000000df
  103. AP: slot 5 apic_id 5, MCU rev: 0x000000df
  104. AP: slot 4 apic_id 4, MCU rev: 0x000000df
  105. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1a8 memsize: 0x1a8
  106. Processing 11 relocs. Offset value of 0x00038000
  107. SMM Module: stub loaded at 0x00038000. Will call 0x99bdc956
  108. Installing permanent SMM handler to 0x9a000000
  109. Loading module at 0x9a010000 with entry 0x9a010c2a. filesize: 0x3650 memsize: 0x7720
  110. Processing 200 relocs. Offset value of 0x9a010000
  111. Loading module at 0x9a008000 with entry 0x9a008000. filesize: 0x1a8 memsize: 0x1a8
  112. Processing 11 relocs. Offset value of 0x9a008000
  113. SMM Module: placing jmp sequence at 0x9a007c00 rel16 0x03fd
  114. SMM Module: placing jmp sequence at 0x9a007800 rel16 0x07fd
  115. SMM Module: placing jmp sequence at 0x9a007400 rel16 0x0bfd
  116. SMM Module: placing jmp sequence at 0x9a007000 rel16 0x0ffd
  117. SMM Module: placing jmp sequence at 0x9a006c00 rel16 0x13fd
  118. SMM Module: placing jmp sequence at 0x9a006800 rel16 0x17fd
  119. SMM Module: placing jmp sequence at 0x9a006400 rel16 0x1bfd
  120. SMM Module: placing jmp sequence at 0x9a006000 rel16 0x1ffd
  121. SMM Module: placing jmp sequence at 0x9a005c00 rel16 0x23fd
  122. SMM Module: placing jmp sequence at 0x9a005800 rel16 0x27fd
  123. SMM Module: placing jmp sequence at 0x9a005400 rel16 0x2bfd
  124. SMM Module: stub loaded at 0x9a008000. Will call 0x9a010c2a
  125. Clearing SMI status registers
  126. SMI_STS: PM1
  127. WAK PWRBTN GPE0 STD STS: TCO_SCI
  128. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x9a000000, cpu = 0
  129. In relocation handler: CPU 0
  130. New SMBASE=0x9a000000 IEDBASE=0x9ac00000
  131. Writing SMRR. base = 0x9a000006, mask=0xff000800
  132. Relocation complete.
  133. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99fff400, cpu = 3
  134. In relocation handler: CPU 3
  135. New SMBASE=0x99fff400 IEDBASE=0x9ac00000
  136. Relocation complete.
  137. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffe400, cpu = 7
  138. In relocation handler: CPU 7
  139. New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
  140. Writing SMRR. base = 0x9a000006, mask=0xff000800
  141. Relocation complete.
  142. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffe800, cpu = 6
  143. In relocation handler: CPU 6
  144. New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
  145. Relocation complete.
  146. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99fff000, cpu = 4
  147. In relocation handler: CPU 4
  148. New SMBASE=0x99fff000 IEDBASE=0x9ac00000
  149. Writing SMRR. base = 0x9a000006, mask=0xff000800
  150. Relocation complete.
  151. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffec00, cpu = 5
  152. In relocation handler: CPU 5
  153. New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
  154. Relocation complete.
  155. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffd800, cpu = 10
  156. In relocation handler: CPU 10
  157. New SMBASE=0x99ffd800 IEDBASE=0x9ac00000
  158. Writing SMRR. base = 0x9a000006, mask=0xff000800
  159. Relocation complete.
  160. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffd400, cpu = 11
  161. In relocation handler: CPU 11
  162. New SMBASE=0x99ffd400 IEDBASE=0x9ac00000
  163. Relocation complete.
  164. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffdc00, cpu = 9
  165. In relocation handler: CPU 9
  166. New SMBASE=0x99ffdc00 IEDBASE=0x9ac00000
  167. Relocation complete.
  168. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99ffe000, cpu = 8
  169. In relocation handler: CPU 8
  170. New SMBASE=0x99ffe000 IEDBASE=0x9ac00000
  171. Writing SMRR. base = 0x9a000006, mask=0xff000800
  172. Relocation complete.
  173. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99fff800, cpu = 2
  174. In relocation handler: CPU 2
  175. New SMBASE=0x99fff800 IEDBASE=0x9ac00000
  176. Relocation complete.
  177. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x99fffc00, cpu = 1
  178. In relocation handler: CPU 1
  179. New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
  180. Writing SMRR. base = 0x9a000006, mask=0xff000800
  181. Relocation complete.
  182. Initializing CPU #0
  183. CPU: vendor Intel device a0660
  184. CPU: family 06, model a6, stepping 00
  185. Clearing out pending MCEs
  186. Setting up local APIC...
  187. apic_id: 0x00 done.
  188. Turbo is available but hidden
  189. Turbo is available and visible
  190. VMX status: enabled
  191. IA32_FEATURE_CONTROL status: locked
  192. Skip microcode update
  193. CPU #0 initialized
  194. Initializing CPU #3
  195. Initializing CPU #10
  196. Initializing CPU #11
  197. CPU: vendor Intel device a0660
  198. CPU: family 06, model a6, stepping 00
  199. CPU: vendor Intel device a0660
  200. CPU: family 06, model a6, stepping 00
  201. Clearing out pending MCEs
  202. Clearing out pending MCEs
  203. Setting up local APIC...
  204. Initializing CPU #6
  205. apic_id: 0x0a done.
  206. Setting up local APIC...
  207. Initializing CPU #4
  208. Initializing CPU #5
  209. VMX status: enabled
  210. apic_id: 0x0b done.
  211. IA32_FEATURE_CONTROL status: locked
  212. VMX status: enabled
  213. Skip microcode update
  214. CPU #10 initialized
  215. IA32_FEATURE_CONTROL status: locked
  216. CPU: vendor Intel device a0660
  217. CPU: family 06, model a6, stepping 00
  218. CPU: vendor Intel device a0660
  219. CPU: family 06, model a6, stepping 00
  220. Clearing out pending MCEs
  221. Clearing out pending MCEs
  222. CPU: vendor Intel device a0660
  223. CPU: family 06, model a6, stepping 00
  224. Clearing out pending MCEs
  225. Skip microcode update
  226. CPU #11 initialized
  227. Initializing CPU #2
  228. Initializing CPU #1
  229. CPU: vendor Intel device a0660
  230. CPU: family 06, model a6, stepping 00
  231. CPU: vendor Intel device a0660
  232. CPU: family 06, model a6, stepping 00
  233. Clearing out pending MCEs
  234. Clearing out pending MCEs
  235. Setting up local APIC...
  236. Setting up local APIC...
  237. Setting up local APIC...
  238. apic_id: 0x01 done.
  239. CPU: vendor Intel device a0660
  240. CPU: family 06, model a6, stepping 00
  241. Initializing CPU #7
  242. Clearing out pending MCEs
  243. CPU: vendor Intel device a0660
  244. CPU: family 06, model a6, stepping 00
  245. Setting up local APIC...
  246. apic_id: 0x04 done.
  247. Setting up local APIC...
  248. Initializing CPU #9
  249. Initializing CPU #8
  250. VMX status: enabled
  251. Setting up local APIC...
  252. VMX status: enabled
  253. apic_id: 0x05 done.
  254. IA32_FEATURE_CONTROL status: locked
  255. VMX status: enabled
  256. Skip microcode update
  257. CPU #4 initialized
  258. IA32_FEATURE_CONTROL status: locked
  259. Clearing out pending MCEs
  260. apic_id: 0x07 done.
  261. Setting up local APIC...
  262. apic_id: 0x02 done.
  263. apic_id: 0x03 done.
  264. VMX status: enabled
  265. VMX status: enabled
  266. IA32_FEATURE_CONTROL status: locked
  267. IA32_FEATURE_CONTROL status: locked
  268. Skip microcode update
  269. CPU #1 initialized
  270. Skip microcode update
  271. CPU #2 initialized
  272. VMX status: enabled
  273. apic_id: 0x06 done.
  274. IA32_FEATURE_CONTROL status: locked
  275. VMX status: enabled
  276. Skip microcode update
  277. CPU #6 initialized
  278. IA32_FEATURE_CONTROL status: locked
  279. Skip microcode update
  280. CPU #5 initialized
  281. IA32_FEATURE_CONTROL status: locked
  282. Skip microcode update
  283. CPU #7 initialized
  284. Skip microcode update
  285. CPU #3 initialized
  286. CPU: vendor Intel device a0660
  287. CPU: family 06, model a6, stepping 00
  288. CPU: vendor Intel device a0660
  289. CPU: family 06, model a6, stepping 00
  290. Clearing out pending MCEs
  291. Clearing out pending MCEs
  292. Setting up local APIC...
  293. Setting up local APIC...
  294. apic_id: 0x09 done.
  295. apic_id: 0x08 done.
  296. VMX status: enabled
  297. VMX status: enabled
  298. IA32_FEATURE_CONTROL status: locked
  299. IA32_FEATURE_CONTROL status: locked
  300. Skip microcode update
  301. CPU #9 initialized
  302. Skip microcode update
  303. CPU #8 initialized
  304. bsp_do_flight_plan done after 696 msecs.
  305. CPU: frequency set to 4700 MHz
  306. Enabling SMIs.
  307. Locking SMM.
  308. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 608 / 260 ms
  309. FSPS returned 0
  310. Display FSP Version Info HOB
  311. Reference Code - CPU = 9.0.30.50
  312. uCode Version = 0.0.0.e0
  313. TXT ACM version = ff.ff.ff.ffff
  314. Reference Code - ME = 9.0.30.50
  315. MEBx version = 0.0.0.0
  316. ME Firmware Version = Consumer SKU
  317. Reference Code - CML PCH = 9.0.30.50
  318. PCH-CRID Status = Disabled
  319. PCH-CRID Original Value = ff.ff.ff.ffff
  320. PCH-CRID New Value = ff.ff.ff.ffff
  321. OPROM - RST - RAID = ff.ff.ff.ffff
  322. ChipsetInit Base Version = ff.ff.ff.ffff
  323. ChipsetInit Oem Version = ff.ff.ff.ffff
  324. Reference Code - SA - System Agent = 9.0.30.50
  325. Reference Code - MRC = 0.0.0.45
  326. SA - PCIe Version = 9.0.30.50
  327. SA-CRID Status = Disabled
  328. SA-CRID Original Value = 0.0.0.0
  329. SA-CRID New Value = 0.0.0.0
  330. OPROM - VBIOS = ff.ff.ff.ffff
  331. Found PCIe Root Port #9 at PCI: 00:1d.0.
  332. pcie_rp_update_dev: Couldn't find PCIe Root Port #13 (originally PCI: 00:1d.4) which was enabled in devicetree, removing.
  333. pcie_rp_update_dev: Couldn't find PCIe Root Port #14 (originally PCI: 00:1d.5) which was enabled in devicetree, removing.
  334. BS: BS_DEV_INIT_CHIPS run times (exec / console): 166 / 99 ms
  335. RTC Init
  336. Set power off after power failure.
  337. Disabling Deep S3
  338. Disabling Deep S3
  339. Disabling Deep S4
  340. Disabling Deep S4
  341. Disabling Deep S5
  342. Disabling Deep S5
  343. BS: BS_DEV_INIT_CHIPS exit times (exec / console): 4 / 16 ms
  344. Enumerating buses...
  345. Root Device scanning...
  346. CPU_CLUSTER: 0 enabled
  347. DOMAIN: 0000 enabled
  348. DOMAIN: 0000 scanning...
  349. PCI: pci_scan_bus for bus 00
  350. PCI: 00:00.0 [8086/9b51] enabled
  351. PCI: 00:02.0 [8086/9bca] enabled
  352. PCI: 00:04.0 [8086/1903] enabled
  353. PCI: 00:08.0 [8086/1911] enabled
  354. PCI: 00:12.0 [8086/02f9] enabled
  355. PCI: 00:14.0 [8086/02ed] enabled
  356. PCI: 00:14.2 [8086/02ef] enabled
  357. PCI: 00:14.3 [8086/02f0] enabled
  358. PCI: 00:15.0 [8086/02e8] enabled
  359. PCI: 00:15.1 [8086/02e9] enabled
  360. PCI: 00:16.0 [8086/02e0] disabled
  361. PCI: 00:17.0 [8086/02d3] enabled
  362. PCI: 00:19.0 [8086/02c5] disabled
  363. PCI: 00:19.2 [8086/02c7] enabled
  364. PCI: 00:1a.0 [8086/02c4] enabled
  365. PCI: 00:1d.0 [8086/02b0] enabled
  366. PCI: 00:1e.0 [8086/02a8] enabled
  367. PCI: 00:1f.0 [8086/0284] enabled
  368. PCI: 00:1f.3 [8086/02c8] enabled
  369. PCI: 00:1f.4 [8086/02a3] enabled
  370. PCI: 00:1f.5 [8086/02a4] enabled
  371. PCI: Leftover static devices:
  372. PCI: 00:12.5
  373. PCI: 00:12.6
  374. PCI: 00:14.1
  375. PCI: 00:14.5
  376. PCI: 00:15.2
  377. PCI: 00:15.3
  378. PCI: 00:16.1
  379. PCI: 00:16.2
  380. PCI: 00:16.3
  381. PCI: 00:16.4
  382. PCI: 00:16.5
  383. PCI: 00:19.1
  384. PCI: 00:1e.1
  385. PCI: 00:1e.2
  386. PCI: 00:1e.3
  387. PCI: 00:1f.1
  388. PCI: 00:1f.2
  389. PCI: 00:1f.6
  390. PCI: Check your devicetree.cb.
  391. PCI: 00:02.0 scanning...
  392. scan_bus: bus PCI: 00:02.0 finished in 0 msecs
  393. PCI: 00:14.0 scanning...
  394. scan_bus: bus PCI: 00:14.0 finished in 0 msecs
  395. PCI: 00:14.3 scanning...
  396. GENERIC: 0.0 enabled
  397. scan_bus: bus PCI: 00:14.3 finished in 2 msecs
  398. PCI: 00:15.0 scanning...
  399. I2C: 00:2c enabled
  400. scan_bus: bus PCI: 00:15.0 finished in 1 msecs
  401. PCI: 00:15.1 scanning...
  402. scan_bus: bus PCI: 00:15.1 finished in 0 msecs
  403. PCI: 00:1d.0 scanning...
  404. PCI: pci_scan_bus for bus 01
  405. PCI: 01:00.0 [1987/5012] enabled
  406. Enabling Common Clock Configuration
  407. PCIE CLK PM is not supported by endpoint
  408. L1 Sub-State supported from root port 29
  409. L1 Sub-State Support = 0xf
  410. CommonModeRestoreTime = 0x28
  411. Power On Value = 0x6, Power On Scale = 0x1
  412. ASPM: Enabled L1
  413. PCIe: Max_Payload_Size adjusted to 128
  414. PCI: 01:00.0: Enabled LTR
  415. PCI: 01:00.0: Programmed LTR max latencies
  416. scan_bus: bus PCI: 00:1d.0 finished in 40 msecs
  417. PCI: 00:1f.0 scanning...
  418. PNP: 004e.0 enabled
  419. scan_bus: bus PCI: 00:1f.0 finished in 2 msecs
  420. PCI: 00:1f.3 scanning...
  421. scan_bus: bus PCI: 00:1f.3 finished in 0 msecs
  422. PCI: 00:1f.4 scanning...
  423. scan_bus: bus PCI: 00:1f.4 finished in 0 msecs
  424. PCI: 00:1f.5 scanning...
  425. scan_bus: bus PCI: 00:1f.5 finished in 0 msecs
  426. scan_bus: bus DOMAIN: 0000 finished in 223 msecs
  427. scan_bus: bus Root Device finished in 235 msecs
  428. done
  429. BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 245 ms
  430. MRC: Could not find region 'UNIFIED_MRC_CACHE'
  431. FMAP: area RW_MRC_CACHE found @ 420000 (65536 bytes)
  432. MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
  433. BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 14 ms
  434. found VGA at PCI: 00:02.0
  435. Setting up VGA for PCI: 00:02.0
  436. Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  437. Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  438. Allocating resources...
  439. Reading resources...
  440. Done reading resources.
  441. ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
  442. PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
  443. PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
  444. PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
  445. PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
  446. PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
  447. PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
  448. PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
  449. === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
  450. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  451. update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
  452. update_constraints: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
  453. update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
  454. DOMAIN: 0000: Resource ranges:
  455. * Base: 1000, Size: 800, Tag: 100
  456. * Base: 1900, Size: d6a0, Tag: 100
  457. * Base: efc0, Size: 1040, Tag: 100
  458. PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
  459. PCI: 00:17.0 20 * [0x1040 - 0x105f] limit: 105f io
  460. PCI: 00:17.0 18 * [0x1060 - 0x1067] limit: 1067 io
  461. PCI: 00:17.0 1c * [0x1068 - 0x106b] limit: 106b io
  462. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
  463. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
  464. update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
  465. update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed)
  466. update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
  467. update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
  468. update_constraints: PCI: 00:00.0 04 base fc000000 limit fc000fff mem (fixed)
  469. update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
  470. update_constraints: PCI: 00:00.0 06 base fe000000 limit fe00ffff mem (fixed)
  471. update_constraints: PCI: 00:00.0 07 base fed90000 limit fed90fff mem (fixed)
  472. update_constraints: PCI: 00:00.0 08 base fed91000 limit fed91fff mem (fixed)
  473. update_constraints: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
  474. update_constraints: PCI: 00:00.0 0a base 000c0000 limit 99ffefff mem (fixed)
  475. update_constraints: PCI: 00:00.0 0b base 99fff000 limit 9f7fffff mem (fixed)
  476. update_constraints: PCI: 00:00.0 0c base 100000000 limit 45e7fffff mem (fixed)
  477. update_constraints: PCI: 00:00.0 0d base 000a0000 limit 000bffff mem (fixed)
  478. update_constraints: PCI: 00:00.0 0e base 000c0000 limit 000fffff mem (fixed)
  479. update_constraints: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed)
  480. DOMAIN: 0000: Resource ranges:
  481. * Base: 9f800000, Size: 40800000, Tag: 200
  482. * Base: f0000000, Size: c000000, Tag: 200
  483. * Base: fc001000, Size: 1fff000, Tag: 200
  484. * Base: fe010000, Size: 22000, Tag: 200
  485. * Base: fe033000, Size: cdd000, Tag: 200
  486. * Base: fed18000, Size: 68000, Tag: 200
  487. * Base: fed84000, Size: c000, Tag: 200
  488. * Base: fed92000, Size: e000, Tag: 200
  489. * Base: feda2000, Size: 125e000, Tag: 200
  490. * Base: 45e800000, Size: 7ba1800000, Tag: 100200
  491. PCI: 00:02.0 18 * [0xa0000000 - 0xafffffff] limit: afffffff prefmem
  492. PCI: 00:02.0 10 * [0xb0000000 - 0xb0ffffff] limit: b0ffffff mem
  493. PCI: 00:1d.0 20 * [0x9f800000 - 0x9f8fffff] limit: 9f8fffff mem
  494. PCI: 00:1f.3 20 * [0x9f900000 - 0x9f9fffff] limit: 9f9fffff mem
  495. PCI: 00:14.0 10 * [0x9fa00000 - 0x9fa0ffff] limit: 9fa0ffff mem
  496. PCI: 00:04.0 10 * [0x9fa10000 - 0x9fa17fff] limit: 9fa17fff mem
  497. PCI: 00:14.3 10 * [0x9fa18000 - 0x9fa1bfff] limit: 9fa1bfff mem
  498. PCI: 00:1f.3 10 * [0x9fa1c000 - 0x9fa1ffff] limit: 9fa1ffff mem
  499. PCI: 00:14.2 10 * [0x9fa20000 - 0x9fa21fff] limit: 9fa21fff mem
  500. PCI: 00:17.0 10 * [0x9fa22000 - 0x9fa23fff] limit: 9fa23fff mem
  501. PCI: 00:08.0 10 * [0x9fa24000 - 0x9fa24fff] limit: 9fa24fff mem
  502. PCI: 00:12.0 10 * [0x9fa25000 - 0x9fa25fff] limit: 9fa25fff mem
  503. PCI: 00:14.2 18 * [0x9fa26000 - 0x9fa26fff] limit: 9fa26fff mem
  504. PCI: 00:15.0 10 * [0x9fa27000 - 0x9fa27fff] limit: 9fa27fff mem
  505. PCI: 00:15.1 10 * [0x9fa28000 - 0x9fa28fff] limit: 9fa28fff mem
  506. PCI: 00:19.2 18 * [0x9fa29000 - 0x9fa29fff] limit: 9fa29fff mem
  507. PCI: 00:1a.0 10 * [0x9fa2a000 - 0x9fa2afff] limit: 9fa2afff mem
  508. PCI: 00:1e.0 10 * [0x9fa2b000 - 0x9fa2bfff] limit: 9fa2bfff mem
  509. PCI: 00:1e.0 18 * [0x9fa2c000 - 0x9fa2cfff] limit: 9fa2cfff mem
  510. PCI: 00:1f.5 10 * [0x9fa2d000 - 0x9fa2dfff] limit: 9fa2dfff mem
  511. PCI: 00:17.0 24 * [0x9fa2e000 - 0x9fa2e7ff] limit: 9fa2e7ff mem
  512. PCI: 00:17.0 14 * [0x9fa2f000 - 0x9fa2f0ff] limit: 9fa2f0ff mem
  513. PCI: 00:1f.4 10 * [0x9fa30000 - 0x9fa300ff] limit: 9fa300ff mem
  514. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
  515. PCI: 00:1d.0 mem: base: 9f800000 size: 100000 align: 20 gran: 20 limit: 9f8fffff
  516. PCI: 00:1d.0: Resource ranges:
  517. * Base: 9f800000, Size: 100000, Tag: 200
  518. PCI: 01:00.0 10 * [0x9f800000 - 0x9f803fff] limit: 9f803fff mem
  519. PCI: 00:1d.0 mem: base: 9f800000 size: 100000 align: 20 gran: 20 limit: 9f8fffff done
  520. === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
  521. PCI: 00:02.0 10 <- [0x00b0000000 - 0x00b0ffffff] size 0x01000000 gran 0x18 mem64
  522. PCI: 00:02.0 18 <- [0x00a0000000 - 0x00afffffff] size 0x10000000 gran 0x1c prefmem64
  523. PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
  524. PCI: 00:04.0 10 <- [0x009fa10000 - 0x009fa17fff] size 0x00008000 gran 0x0f mem64
  525. PCI: 00:08.0 10 <- [0x009fa24000 - 0x009fa24fff] size 0x00001000 gran 0x0c mem64
  526. PCI: 00:12.0 10 <- [0x009fa25000 - 0x009fa25fff] size 0x00001000 gran 0x0c mem64
  527. PCI: 00:14.0 10 <- [0x009fa00000 - 0x009fa0ffff] size 0x00010000 gran 0x10 mem64
  528. PCI: 00:14.2 10 <- [0x009fa20000 - 0x009fa21fff] size 0x00002000 gran 0x0d mem64
  529. PCI: 00:14.2 18 <- [0x009fa26000 - 0x009fa26fff] size 0x00001000 gran 0x0c mem64
  530. PCI: 00:14.3 10 <- [0x009fa18000 - 0x009fa1bfff] size 0x00004000 gran 0x0e mem64
  531. PCI: 00:15.0 10 <- [0x009fa27000 - 0x009fa27fff] size 0x00001000 gran 0x0c mem64
  532. PCI: 00:15.1 10 <- [0x009fa28000 - 0x009fa28fff] size 0x00001000 gran 0x0c mem64
  533. PCI: 00:17.0 10 <- [0x009fa22000 - 0x009fa23fff] size 0x00002000 gran 0x0d mem
  534. PCI: 00:17.0 14 <- [0x009fa2f000 - 0x009fa2f0ff] size 0x00000100 gran 0x08 mem
  535. PCI: 00:17.0 18 <- [0x0000001060 - 0x0000001067] size 0x00000008 gran 0x03 io
  536. PCI: 00:17.0 1c <- [0x0000001068 - 0x000000106b] size 0x00000004 gran 0x02 io
  537. PCI: 00:17.0 20 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io
  538. PCI: 00:17.0 24 <- [0x009fa2e000 - 0x009fa2e7ff] size 0x00000800 gran 0x0b mem
  539. PCI: 00:19.2 18 <- [0x009fa29000 - 0x009fa29fff] size 0x00001000 gran 0x0c mem64
  540. PCI: 00:1a.0 10 <- [0x009fa2a000 - 0x009fa2afff] size 0x00001000 gran 0x0c mem64
  541. PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
  542. PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
  543. PCI: 00:1d.0 20 <- [0x009f800000 - 0x009f8fffff] size 0x00100000 gran 0x14 bus 01 mem
  544. PCI: 01:00.0 10 <- [0x009f800000 - 0x009f803fff] size 0x00004000 gran 0x0e mem64
  545. PCI: 00:1e.0 10 <- [0x009fa2b000 - 0x009fa2bfff] size 0x00001000 gran 0x0c mem64
  546. PCI: 00:1e.0 18 <- [0x009fa2c000 - 0x009fa2cfff] size 0x00001000 gran 0x0c mem64
  547. PCI: 00:1f.3 10 <- [0x009fa1c000 - 0x009fa1ffff] size 0x00004000 gran 0x0e mem64
  548. PCI: 00:1f.3 20 <- [0x009f900000 - 0x009f9fffff] size 0x00100000 gran 0x14 mem64
  549. PCI: 00:1f.4 10 <- [0x009fa30000 - 0x009fa300ff] size 0x00000100 gran 0x08 mem64
  550. PCI: 00:1f.5 10 <- [0x009fa2d000 - 0x009fa2dfff] size 0x00001000 gran 0x0c mem
  551. Done setting resources.
  552. Done allocating resources.
  553. BS: BS_DEV_RESOURCES run times (exec / console): 1 / 774 ms
  554. Enabling resources...
  555. PCI: 00:00.0 subsystem <- 8086/9b51
  556. PCI: 00:00.0 cmd <- 06
  557. PCI: 00:02.0 subsystem <- 8086/9bca
  558. PCI: 00:02.0 cmd <- 03
  559. PCI: 00:04.0 subsystem <- 8086/1903
  560. PCI: 00:04.0 cmd <- 02
  561. PCI: 00:08.0 subsystem <- 8086/1911
  562. PCI: 00:08.0 cmd <- 06
  563. PCI: 00:12.0 subsystem <- 8086/02f9
  564. PCI: 00:12.0 cmd <- 02
  565. PCI: 00:14.0 subsystem <- 8086/02ed
  566. PCI: 00:14.0 cmd <- 02
  567. PCI: 00:14.2 cmd <- 02
  568. PCI: 00:14.3 subsystem <- 8086/02f0
  569. PCI: 00:14.3 cmd <- 02
  570. PCI: 00:15.0 subsystem <- 8086/02e8
  571. PCI: 00:15.0 cmd <- 02
  572. PCI: 00:15.1 subsystem <- 8086/02e9
  573. PCI: 00:15.1 cmd <- 02
  574. PCI: 00:17.0 subsystem <- 8086/02d3
  575. PCI: 00:17.0 cmd <- 03
  576. PCI: 00:19.2 subsystem <- 8086/02c7
  577. PCI: 00:19.2 cmd <- 06
  578. PCI: 00:1a.0 subsystem <- 8086/02c4
  579. PCI: 00:1a.0 cmd <- 06
  580. PCI: 00:1d.0 bridge ctrl <- 0013
  581. PCI: 00:1d.0 subsystem <- 8086/02b0
  582. PCI: 00:1d.0 cmd <- 06
  583. PCI: 00:1e.0 subsystem <- 8086/02a8
  584. PCI: 00:1e.0 cmd <- 02
  585. PCI: 00:1f.0 subsystem <- 8086/0284
  586. PCI: 00:1f.0 cmd <- 07
  587. PCI: 00:1f.3 subsystem <- 10ec/119e
  588. PCI: 00:1f.3 cmd <- 02
  589. PCI: 00:1f.4 subsystem <- 8086/02a3
  590. PCI: 00:1f.4 cmd <- 03
  591. PCI: 00:1f.5 subsystem <- 8086/02a4
  592. PCI: 00:1f.5 cmd <- 406
  593. PCI: 01:00.0 subsystem <- 1987/5012
  594. PCI: 01:00.0 cmd <- 02
  595. done.
  596. BS: BS_DEV_ENABLE run times (exec / console): 0 / 122 ms
  597. HECI: No CSE device
  598. BS: BS_DEV_ENABLE exit times (exec / console): 0 / 2 ms
  599. Initializing devices...
  600. PCI: 00:00.0 init
  601. CPU TDP = 15 Watts
  602. CPU PL1 = 20 Watts
  603. CPU PL2 = 30 Watts
  604. PCI: 00:00.0 init finished in 6 msecs
  605. PCI: 00:02.0 init
  606. CBFS: Found 'vbt.bin' @0xf1e00 size 0x490 in mcache @0x99c4c27c
  607. Found a VBT of 4608 bytes after decompression
  608. GMA: Found VBT in CBFS
  609. GMA: Found valid VBT in CBFS
  610. [2.414888] HW.GFX.GMA.Initialize
  611. [2.418019] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  612. [2.422697] HW.GFX.GMA.Panel.Setup_PP_Sequencer
  613. [2.427402] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS
  614. [2.435403] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  615. [2.443501] HW.GFX.GMA.Registers.Read: 0x00000012 <- 0x000c7204:PCH_PP_CONTROL
  616. [2.451286] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_ON_DELAYS
  617. [2.458136] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c7208:PCH_PP_ON_DELAYS
  618. [2.466118] HW.GFX.GMA.Registers.Write: 0x08340001 -> 0x000c7208:PCH_PP_ON_DELAYS
  619. [2.474139] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_OFF_DELAYS
  620. [2.481069] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c720c:PCH_PP_OFF_DELAYS
  621. [2.489146] HW.GFX.GMA.Registers.Write: 0x138801f4 -> 0x000c720c:PCH_PP_OFF_DELAYS
  622. [2.497267] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_PP_CONTROL
  623. [2.503903] HW.GFX.GMA.Registers.Read: 0x00000012 <- 0x000c7204:PCH_PP_CONTROL
  624. [2.511689] HW.GFX.GMA.Registers.Write: 0x00000072 -> 0x000c7204:PCH_PP_CONTROL
  625. [2.519516] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PCH_PP_CONTROL
  626. [2.526542] HW.GFX.GMA.Registers.Read: 0x00000072 <- 0x000c7204:PCH_PP_CONTROL
  627. [2.534327] HW.GFX.GMA.Registers.Write: 0x00000072 -> 0x000c7204:PCH_PP_CONTROL
  628. [2.542156] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  629. [2.547989] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  630. [2.555698] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  631. [2.562160] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c4030:SHOTPLUG_CTL
  632. [2.569749] HW.GFX.GMA.Registers.Write: 0x13000000 -> 0x000c4030:SHOTPLUG_CTL
  633. [2.577381] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  634. [2.583042] HW.GFX.GMA.Registers.Read: 0x00000106 <- 0x000c2014:SFUSE_STRAP
  635. [2.590534] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  636. [2.596995] HW.GFX.GMA.Registers.Read: 0x10000000 <- 0x000c4030:SHOTPLUG_CTL
  637. [2.604586] HW.GFX.GMA.Registers.Write: 0x10000013 -> 0x000c4030:SHOTPLUG_CTL
  638. [2.612219] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  639. [2.617876] HW.GFX.GMA.Registers.Read: 0x00000106 <- 0x000c2014:SFUSE_STRAP
  640. [2.625370] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  641. [2.631832] HW.GFX.GMA.Registers.Read: 0x10000010 <- 0x000c4030:SHOTPLUG_CTL
  642. [2.639421] HW.GFX.GMA.Registers.Write: 0x10001310 -> 0x000c4030:SHOTPLUG_CTL
  643. [2.647055] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e00:DDI_BUF_TRANS_A_S0T1
  644. [2.655425] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e04:DDI_BUF_TRANS_A_S0T2
  645. [2.663819] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e08:DDI_BUF_TRANS_A_S1T1
  646. [2.672210] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e0c:DDI_BUF_TRANS_A_S1T2
  647. [2.680603] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e10:DDI_BUF_TRANS_A_S2T1
  648. [2.688996] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e14:DDI_BUF_TRANS_A_S2T2
  649. [2.697389] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e18:DDI_BUF_TRANS_A_S3T1
  650. [2.705782] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e1c:DDI_BUF_TRANS_A_S3T2
  651. [2.714174] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e20:DDI_BUF_TRANS_A_S4T1
  652. [2.722567] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e24:DDI_BUF_TRANS_A_S4T2
  653. [2.730960] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e28:DDI_BUF_TRANS_A_S5T1
  654. [2.739354] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e2c:DDI_BUF_TRANS_A_S5T2
  655. [2.747747] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e30:DDI_BUF_TRANS_A_S6T1
  656. [2.756140] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e34:DDI_BUF_TRANS_A_S6T2
  657. [2.764531] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e38:DDI_BUF_TRANS_A_S7T1
  658. [2.772926] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e3c:DDI_BUF_TRANS_A_S7T2
  659. [2.781317] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e40:DDI_BUF_TRANS_A_S8T1
  660. [2.789709] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e44:DDI_BUF_TRANS_A_S8T2
  661. [2.798101] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064e48:DDI_BUF_TRANS_A_S9T1
  662. [2.806495] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e4c:DDI_BUF_TRANS_A_S9T2
  663. [2.814890] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e60:DDI_BUF_TRANS_B_S0T1
  664. [2.823283] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064e64:DDI_BUF_TRANS_B_S0T2
  665. [2.831675] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064e68:DDI_BUF_TRANS_B_S1T1
  666. [2.840069] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064e6c:DDI_BUF_TRANS_B_S1T2
  667. [2.848463] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e70:DDI_BUF_TRANS_B_S2T1
  668. [2.856855] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064e74:DDI_BUF_TRANS_B_S2T2
  669. [2.865249] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064e78:DDI_BUF_TRANS_B_S3T1
  670. [2.873642] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e7c:DDI_BUF_TRANS_B_S3T2
  671. [2.882034] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064e80:DDI_BUF_TRANS_B_S4T1
  672. [2.890426] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064e84:DDI_BUF_TRANS_B_S4T2
  673. [2.898819] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064e88:DDI_BUF_TRANS_B_S5T1
  674. [2.907212] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e8c:DDI_BUF_TRANS_B_S5T2
  675. [2.915605] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064e90:DDI_BUF_TRANS_B_S6T1
  676. [2.923999] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064e94:DDI_BUF_TRANS_B_S6T2
  677. [2.932391] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064e98:DDI_BUF_TRANS_B_S7T1
  678. [2.940786] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064e9c:DDI_BUF_TRANS_B_S7T2
  679. [2.949179] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ea0:DDI_BUF_TRANS_B_S8T1
  680. [2.957573] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ea4:DDI_BUF_TRANS_B_S8T2
  681. [2.965965] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064ea8:DDI_BUF_TRANS_B_S9T1
  682. [2.974359] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064eac:DDI_BUF_TRANS_B_S9T2
  683. [2.982754] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ec0:DDI_BUF_TRANS_C_S0T1
  684. [2.991147] HW.GFX.GMA.Registers.Write: 0x000000a1 -> 0x00064ec4:DDI_BUF_TRANS_C_S0T2
  685. [2.999540] HW.GFX.GMA.Registers.Write: 0x00005012 -> 0x00064ec8:DDI_BUF_TRANS_C_S1T1
  686. [3.007933] HW.GFX.GMA.Registers.Write: 0x00000088 -> 0x00064ecc:DDI_BUF_TRANS_C_S1T2
  687. [3.016324] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ed0:DDI_BUF_TRANS_C_S2T1
  688. [3.024716] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064ed4:DDI_BUF_TRANS_C_S2T2
  689. [3.033110] HW.GFX.GMA.Registers.Write: 0x80009010 -> 0x00064ed8:DDI_BUF_TRANS_C_S3T1
  690. [3.041502] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064edc:DDI_BUF_TRANS_C_S3T2
  691. [3.049895] HW.GFX.GMA.Registers.Write: 0x0000201b -> 0x00064ee0:DDI_BUF_TRANS_C_S4T1
  692. [3.058286] HW.GFX.GMA.Registers.Write: 0x0000009d -> 0x00064ee4:DDI_BUF_TRANS_C_S4T2
  693. [3.066679] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064ee8:DDI_BUF_TRANS_C_S5T1
  694. [3.075073] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064eec:DDI_BUF_TRANS_C_S5T2
  695. [3.083468] HW.GFX.GMA.Registers.Write: 0x80007011 -> 0x00064ef0:DDI_BUF_TRANS_C_S6T1
  696. [3.091862] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064ef4:DDI_BUF_TRANS_C_S6T2
  697. [3.100256] HW.GFX.GMA.Registers.Write: 0x00002016 -> 0x00064ef8:DDI_BUF_TRANS_C_S7T1
  698. [3.108649] HW.GFX.GMA.Registers.Write: 0x0000004f -> 0x00064efc:DDI_BUF_TRANS_C_S7T2
  699. [3.117041] HW.GFX.GMA.Registers.Write: 0x80005012 -> 0x00064f00:DDI_BUF_TRANS_C_S8T1
  700. [3.125436] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x00064f04:DDI_BUF_TRANS_C_S8T2
  701. [3.133830] HW.GFX.GMA.Registers.Write: 0x80003015 -> 0x00064f08:DDI_BUF_TRANS_C_S9T1
  702. [3.142224] HW.GFX.GMA.Registers.Write: 0x000000cd -> 0x00064f0c:DDI_BUF_TRANS_C_S9T2
  703. [3.150618] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DISPIO_CR_TX_BMU_CR0
  704. [3.157840] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  705. [3.166234] HW.GFX.GMA.Registers.Write: 0x0036db00 -> 0x0006c00c:DISPIO_CR_TX_BMU_CR0
  706. [3.174730] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S CPU_VGACNTRL
  707. [3.181381] HW.GFX.GMA.Registers.Read: 0x80002900 <- 0x00041000:CPU_VGACNTRL
  708. [3.188994] HW.GFX.GMA.Registers.Write: 0x80002900 -> 0x00041000:CPU_VGACNTRL
  709. [3.196607] HW.GFX.GMA.Registers.Set_Mask: 0x000f8000 .S DPLL_CTRL2
  710. [3.203243] HW.GFX.GMA.Registers.Read: 0x00a00000 <- 0x0006c05c:DPLL_CTRL2
  711. [3.210659] HW.GFX.GMA.Registers.Write: 0x00af8000 -> 0x0006c05c:DPLL_CTRL2
  712. [3.218077] HW.GFX.GMA.Registers.Set_Mask: 0x00000010 .S NDE_RSTWRN_OPT
  713. [3.225105] HW.GFX.GMA.Registers.Read: 0x00000030 <- 0x00046408:NDE_RSTWRN_OPT
  714. [3.232913] HW.GFX.GMA.Registers.Write: 0x00000030 -> 0x00046408:NDE_RSTWRN_OPT
  715. [3.240722] HW.GFX.GMA.Registers.Wait: 0x08000000 <- 0x08000000 & 0x00042000:FUSE_STATUS
  716. [3.249507] HW.GFX.GMA.Power_And_Clocks.PD_On
  717. [3.253996] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  718. [3.262097] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  719. [3.270393] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  720. [3.278494] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  721. [3.286692] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  722. [3.294404] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  723. [3.302114] HW.GFX.GMA.Registers.Set_Mask: 0x20000000 .S PWR_WELL_CTL_DRIVER
  724. [3.309628] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  725. [3.317922] HW.GFX.GMA.Registers.Write: 0x70000001 -> 0x00045404:PWR_WELL_CTL_DRIVER
  726. [3.326219] HW.GFX.GMA.Registers.Wait: 0x10000000 <- 0x10000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  727. [3.335783] HW.GFX.GMA.Registers.Wait: 0x04000000 <- 0x04000000 & 0x00042000:FUSE_STATUS
  728. [3.344569] HW.GFX.GMA.Power_And_Clocks.PD_On
  729. [3.349057] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  730. [3.357157] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  731. [3.365453] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  732. [3.373554] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  733. [3.381752] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  734. [3.389464] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  735. [3.397174] HW.GFX.GMA.Registers.Set_Mask: 0x00000002 .S PWR_WELL_CTL_DRIVER
  736. [3.404691] HW.GFX.GMA.Registers.Read: 0x70000001 <- 0x00045404:PWR_WELL_CTL_DRIVER
  737. [3.412986] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  738. [3.421284] HW.GFX.GMA.Registers.Wait: 0x00000001 <- 0x00000001 & 0x00045404:PWR_WELL_CTL_DRIVER
  739. [3.430850] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S LCPLL1_CTL
  740. [3.437486] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x00046010:LCPLL1_CTL
  741. [3.444904] HW.GFX.GMA.Registers.Write: 0xc0000000 -> 0x00046010:LCPLL1_CTL
  742. [3.452322] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00046010:LCPLL1_CTL
  743. [3.461010] HW.GFX.GMA.Registers.Read: 0x0c000544 <- 0x00046000:CDCLK_CTL
  744. [3.468329] HW.GFX.GMA.Registers.Read: 0x20400042 <- 0x00051000:DFSM
  745. [3.475161] HW.GFX.GMA.PCode.Mailbox_Write_Read
  746. [3.479845] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  747. [3.488532] HW.GFX.GMA.Registers.Write: 0x00000003 -> 0x00138128:GT_MAILBOX_DATA
  748. [3.496438] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  749. [3.504540] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  750. [3.511958] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00138124:GT_MAILBOX
  751. [3.520645] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00138128:GT_MAILBOX_DATA
  752. [3.528550] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0013812c:GT_MAILBOX_DATA_1
  753. [3.536650] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  754. [3.544556] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  755. [3.552658] HW.GFX.GMA.Registers.Write: 0x080002a1 -> 0x00046000:CDCLK_CTL
  756. [3.559977] HW.GFX.GMA.PCode.Mailbox_Write_Read
  757. [3.564662] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00138128:GT_MAILBOX_DATA
  758. [3.572567] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0013812c:GT_MAILBOX_DATA_1
  759. [3.580668] HW.GFX.GMA.Registers.Write: 0x80000007 -> 0x00138124:GT_MAILBOX
  760. [3.588086] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S DBUF_CTL
  761. [3.594528] HW.GFX.GMA.Registers.Read: 0x0000000a <- 0x00045008:DBUF_CTL
  762. [3.601749] HW.GFX.GMA.Registers.Write: 0x8000000a -> 0x00045008:DBUF_CTL
  763. [3.608973] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045008:DBUF_CTL
  764. [3.617466] HW.GFX.GMA.Registers.Is_Set_Mask: SFUSE_STRAP
  765. [3.623147] HW.GFX.GMA.Registers.Read: 0x00000106 <- 0x000c2014:SFUSE_STRAP
  766. [3.630641] HW.GFX.GMA.Registers.Unset_And_Set_Mask: PCH_RAWCLK_FREQ
  767. [3.637398] HW.GFX.GMA.Registers.Read: 0x10120000 <- 0x000c6204:PCH_RAWCLK_FREQ
  768. [3.645282] HW.GFX.GMA.Registers.Write: 0x00180000 -> 0x000c6204:PCH_RAWCLK_FREQ
  769. [3.653208] HW.GFX.GMA.Panel.On
  770. [3.656310] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  771. [3.662284] HW.GFX.GMA.Registers.Read: 0x00000072 <- 0x000c7204:PCH_PP_CONTROL
  772. [3.670073] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  773. [3.677120] HW.GFX.GMA.Registers.Read: 0x00000072 <- 0x000c7204:PCH_PP_CONTROL
  774. [3.684909] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL
  775. [3.692739] HW.GFX.GMA.Panel.Wait_On
  776. [3.902718] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  777. [3.911531] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  778. [3.918753] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL
  779. [3.926541] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL
  780. [3.934371] HW.GFX.GMA.Display_Probing.Read_EDID
  781. [3.939133] HW.GFX.GMA.Power_And_Clocks.PD_On
  782. [3.943623] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  783. [3.951726] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  784. [3.960023] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  785. [3.968123] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  786. [3.976322] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  787. [3.984033] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  788. [3.991745] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  789. [4.001312] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  790. [4.008825] HW.GFX.GMA.Registers.Read: 0x70000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  791. [4.017121] HW.GFX.GMA.Registers.Write: 0x7000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  792. [4.025418] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  793. [4.034985] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  794. [4.040839] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  795. [4.048550] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  796. [4.056556] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  797. [4.063093] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064010:DDI_AUX_CTL_A
  798. [4.070805] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  799. [4.078517] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  800. [4.087496] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  801. [4.095206] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  802. [4.103210] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  803. [4.109066] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  804. [4.116776] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064014:DDI_AUX_DATA_A_1
  805. [4.124779] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  806. [4.132784] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  807. [4.139322] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  808. [4.147033] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  809. [4.154743] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  810. [4.163721] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  811. [4.171430] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  812. [4.179434] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  813. [4.185289] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  814. [4.192999] HW.GFX.GMA.Registers.Write: 0x00005000 -> 0x00064014:DDI_AUX_DATA_A_1
  815. [4.201004] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  816. [4.207542] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  817. [4.215252] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  818. [4.222963] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  819. [4.231941] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  820. [4.239650] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  821. [4.247651] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  822. [4.253507] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  823. [4.261217] HW.GFX.GMA.Registers.Write: 0x50005000 -> 0x00064014:DDI_AUX_DATA_A_1
  824. [4.269220] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  825. [4.275759] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  826. [4.283469] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  827. [4.291180] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  828. [4.300158] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  829. [4.307868] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  830. [4.315872] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  831. [4.321728] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  832. [4.329439] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  833. [4.337442] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  834. [4.343981] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  835. [4.351692] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  836. [4.359404] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  837. [4.368384] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  838. [4.376094] HW.GFX.GMA.Registers.Read: 0x0000ffff <- 0x00064014:DDI_AUX_DATA_A_1
  839. [4.384099] HW.GFX.GMA.Registers.Read: 0xffffffff <- 0x00064018:DDI_AUX_DATA_A_2
  840. [4.392102] HW.GFX.GMA.Registers.Read: 0x00387020 <- 0x0006401c:DDI_AUX_DATA_A_3
  841. [4.400104] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4
  842. [4.408108] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  843. [4.416111] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  844. [4.421968] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  845. [4.429679] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  846. [4.437683] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  847. [4.444223] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  848. [4.451933] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  849. [4.459644] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  850. [4.468626] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  851. [4.476335] HW.GFX.GMA.Registers.Read: 0x00001b01 <- 0x00064014:DDI_AUX_DATA_A_1
  852. [4.484340] HW.GFX.GMA.Registers.Read: 0x04a51d11 <- 0x00064018:DDI_AUX_DATA_A_2
  853. [4.492344] HW.GFX.GMA.Registers.Read: 0x78067b50 <- 0x0006401c:DDI_AUX_DATA_A_3
  854. [4.500348] HW.GFX.GMA.Registers.Read: 0xa256519c <- 0x00064020:DDI_AUX_DATA_A_4
  855. [4.508351] HW.GFX.GMA.Registers.Read: 0x27000000 <- 0x00064024:DDI_AUX_DATA_A_5
  856. [4.516356] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  857. [4.522212] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  858. [4.529923] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  859. [4.537926] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  860. [4.544467] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  861. [4.552178] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  862. [4.559888] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  863. [4.568871] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  864. [4.576581] HW.GFX.GMA.Registers.Read: 0x000c4e53 <- 0x00064014:DDI_AUX_DATA_A_1
  865. [4.584585] HW.GFX.GMA.Registers.Read: 0x00000001 <- 0x00064018:DDI_AUX_DATA_A_2
  866. [4.592588] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x0006401c:DDI_AUX_DATA_A_3
  867. [4.600593] HW.GFX.GMA.Registers.Read: 0x01010101 <- 0x00064020:DDI_AUX_DATA_A_4
  868. [4.608596] HW.GFX.GMA.Registers.Read: 0x01000000 <- 0x00064024:DDI_AUX_DATA_A_5
  869. [4.616599] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  870. [4.622455] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  871. [4.630166] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  872. [4.638168] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  873. [4.644708] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  874. [4.652418] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  875. [4.660128] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  876. [4.669109] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  877. [4.676820] HW.GFX.GMA.Registers.Read: 0x00010101 <- 0x00064014:DDI_AUX_DATA_A_1
  878. [4.684823] HW.GFX.GMA.Registers.Read: 0x0101011a <- 0x00064018:DDI_AUX_DATA_A_2
  879. [4.692828] HW.GFX.GMA.Registers.Read: 0x3680a070 <- 0x0006401c:DDI_AUX_DATA_A_3
  880. [4.700832] HW.GFX.GMA.Registers.Read: 0x381f4030 <- 0x00064020:DDI_AUX_DATA_A_4
  881. [4.708836] HW.GFX.GMA.Registers.Read: 0x20000000 <- 0x00064024:DDI_AUX_DATA_A_5
  882. [4.716842] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  883. [4.722699] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  884. [4.730410] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  885. [4.738415] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  886. [4.744955] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  887. [4.752665] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  888. [4.760377] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  889. [4.769358] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  890. [4.777068] HW.GFX.GMA.Registers.Read: 0x00350026 <- 0x00064014:DDI_AUX_DATA_A_1
  891. [4.785072] HW.GFX.GMA.Registers.Read: 0xa5100000 <- 0x00064018:DDI_AUX_DATA_A_2
  892. [4.793076] HW.GFX.GMA.Registers.Read: 0x18542b80 <- 0x0006401c:DDI_AUX_DATA_A_3
  893. [4.801081] HW.GFX.GMA.Registers.Read: 0xa070381f <- 0x00064020:DDI_AUX_DATA_A_4
  894. [4.809084] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00064024:DDI_AUX_DATA_A_5
  895. [4.817089] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  896. [4.822946] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  897. [4.830657] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  898. [4.838662] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  899. [4.845201] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  900. [4.852912] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  901. [4.860625] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  902. [4.869605] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  903. [4.877315] HW.GFX.GMA.Registers.Read: 0x00302035 <- 0x00064014:DDI_AUX_DATA_A_1
  904. [4.885319] HW.GFX.GMA.Registers.Read: 0x0026a510 <- 0x00064018:DDI_AUX_DATA_A_2
  905. [4.893326] HW.GFX.GMA.Registers.Read: 0x00001800 <- 0x0006401c:DDI_AUX_DATA_A_3
  906. [4.901331] HW.GFX.GMA.Registers.Read: 0x00001000 <- 0x00064020:DDI_AUX_DATA_A_4
  907. [4.909335] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064024:DDI_AUX_DATA_A_5
  908. [4.917339] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  909. [4.923195] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  910. [4.930908] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  911. [4.938913] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  912. [4.945452] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  913. [4.953163] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  914. [4.960873] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  915. [4.969854] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  916. [4.977564] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  917. [4.985568] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064018:DDI_AUX_DATA_A_2
  918. [4.993571] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006401c:DDI_AUX_DATA_A_3
  919. [5.001576] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064020:DDI_AUX_DATA_A_4
  920. [5.009581] HW.GFX.GMA.Registers.Read: 0xfc000000 <- 0x00064024:DDI_AUX_DATA_A_5
  921. [5.017584] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  922. [5.023440] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  923. [5.031152] HW.GFX.GMA.Registers.Write: 0x5000500f -> 0x00064014:DDI_AUX_DATA_A_1
  924. [5.039156] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  925. [5.045695] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  926. [5.053407] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  927. [5.061118] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  928. [5.070098] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  929. [5.077809] HW.GFX.GMA.Registers.Read: 0x00004c4d <- 0x00064014:DDI_AUX_DATA_A_1
  930. [5.085815] HW.GFX.GMA.Registers.Read: 0x3133334c <- 0x00064018:DDI_AUX_DATA_A_2
  931. [5.093818] HW.GFX.GMA.Registers.Read: 0x46354c30 <- 0x0006401c:DDI_AUX_DATA_A_3
  932. [5.101821] HW.GFX.GMA.Registers.Read: 0x310a2000 <- 0x00064020:DDI_AUX_DATA_A_4
  933. [5.109825] HW.GFX.GMA.Registers.Read: 0x52000000 <- 0x00064024:DDI_AUX_DATA_A_5
  934. [5.117829] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  935. [5.123685] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  936. [5.131396] HW.GFX.GMA.Registers.Write: 0x10005000 -> 0x00064014:DDI_AUX_DATA_A_1
  937. [5.139402] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  938. [5.145942] HW.GFX.GMA.Registers.Read: 0x4510023f <- 0x00064010:DDI_AUX_CTL_A
  939. [5.153653] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064010:DDI_AUX_CTL_A
  940. [5.161365] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  941. [5.170346] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  942. [5.178057] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  943. [5.186061] EDID+0x0000: 00 ff ff ff ff ff ff 00 38 70 20 00 00 00 00 00
  944. [5.193479] EDID+0x0010: 00 1b 01 04 a5 1d 11 78 06 7b 50 a2 56 51 9c 27
  945. [5.200898] EDID+0x0020: 0c 4e 53 00 00 00 01 01 01 01 01 01 01 01 01 01
  946. [5.208315] EDID+0x0030: 01 01 01 01 01 01 1a 36 80 a0 70 38 1f 40 30 20
  947. [5.215734] EDID+0x0040: 35 00 26 a5 10 00 00 18 54 2b 80 a0 70 38 1f 40
  948. [5.223152] EDID+0x0050: 30 20 35 00 26 a5 10 00 00 18 00 00 00 10 00 00
  949. [5.230571] EDID+0x0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 fc
  950. [5.237990] EDID+0x0070: 00 4c 4d 31 33 33 4c 46 35 4c 30 31 0a 20 00 52
  951. [5.245408] HW.GFX.GMA.Display_Probing.Read_EDID
  952. [5.250191] HW.GFX.GMA.Power_And_Clocks.PD_On
  953. [5.254682] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  954. [5.262784] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  955. [5.271081] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  956. [5.279183] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  957. [5.287382] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  958. [5.295092] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  959. [5.302804] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PWR_WELL_CTL_DRIVER
  960. [5.310320] HW.GFX.GMA.Registers.Read: 0x7000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  961. [5.318617] HW.GFX.GMA.Registers.Write: 0xf000000f -> 0x00045404:PWR_WELL_CTL_DRIVER
  962. [5.326915] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  963. [5.336482] HW.GFX.GMA.Registers.Wait: 0x02000000 <- 0x02000000 & 0x00042000:FUSE_STATUS
  964. [5.345267] HW.GFX.GMA.Power_And_Clocks.PD_On
  965. [5.349755] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  966. [5.357857] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  967. [5.366154] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  968. [5.374255] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  969. [5.382453] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  970. [5.390164] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  971. [5.397876] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  972. [5.407443] HW.GFX.GMA.Registers.Set_Mask: 0x00000020 .S PWR_WELL_CTL_DRIVER
  973. [5.414958] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  974. [5.423254] HW.GFX.GMA.Registers.Write: 0xf000002f -> 0x00045404:PWR_WELL_CTL_DRIVER
  975. [5.431552] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  976. [5.441118] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  977. [5.446974] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  978. [5.454686] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  979. [5.462690] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  980. [5.469230] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064110:DDI_AUX_CTL_B
  981. [5.476941] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  982. [5.484652] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  983. [5.493633] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  984. [5.501343] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  985. [5.507200] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  986. [5.514911] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  987. [5.522916] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  988. [5.529455] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  989. [5.537168] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  990. [5.544879] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  991. [5.553860] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  992. [5.561571] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_B
  993. [5.567426] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  994. [5.575138] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064114:DDI_AUX_DATA_B_1
  995. [5.583142] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_B
  996. [5.589681] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  997. [5.597392] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064110:DDI_AUX_CTL_B
  998. [5.605103] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064110:DDI_AUX_CTL_B
  999. [5.614083] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064110:DDI_AUX_CTL_B
  1000. [5.621794] HW.GFX.GMA.Display_Probing.Read_EDID
  1001. [5.626575] HW.GFX.GMA.Power_And_Clocks.PD_On
  1002. [5.631066] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  1003. [5.639167] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1004. [5.647462] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1005. [5.655563] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1006. [5.663762] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1007. [5.671471] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1008. [5.679182] HW.GFX.GMA.Power_And_Clocks.PD_On
  1009. [5.683672] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  1010. [5.691774] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1011. [5.700071] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1012. [5.708171] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1013. [5.716368] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1014. [5.724080] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1015. [5.731791] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  1016. [5.741359] HW.GFX.GMA.Registers.Set_Mask: 0x00000080 .S PWR_WELL_CTL_DRIVER
  1017. [5.748873] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1018. [5.757170] HW.GFX.GMA.Registers.Write: 0xf00000bf -> 0x00045404:PWR_WELL_CTL_DRIVER
  1019. [5.765468] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  1020. [5.775033] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1021. [5.780888] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
  1022. [5.788598] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
  1023. [5.796602] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1024. [5.803141] HW.GFX.GMA.Registers.Read: 0x0000023f <- 0x00064210:DDI_AUX_CTL_C
  1025. [5.810850] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  1026. [5.818563] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1027. [5.827543] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1028. [5.835254] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1029. [5.841110] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1030. [5.848822] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
  1031. [5.856825] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1032. [5.863363] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1033. [5.871072] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  1034. [5.878784] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1035. [5.887764] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1036. [5.895474] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_C
  1037. [5.901330] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1038. [5.909041] HW.GFX.GMA.Registers.Write: 0x40005000 -> 0x00064214:DDI_AUX_DATA_C_1
  1039. [5.917045] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_C
  1040. [5.923583] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1041. [5.931294] HW.GFX.GMA.Registers.Write: 0xd630023f -> 0x00064210:DDI_AUX_CTL_C
  1042. [5.939004] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064210:DDI_AUX_CTL_C
  1043. [5.947985] HW.GFX.GMA.Registers.Read: 0x5540023f <- 0x00064210:DDI_AUX_CTL_C
  1044. [5.955695] HW.GFX.GMA.Display_Probing.Read_EDID
  1045. [5.960478] HW.GFX.GMA.I2C.I2C_Read
  1046. [5.963992] HW.GFX.GMA.I2C.Init_GMBUS
  1047. [5.967701] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  1048. [5.975041] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1049. [5.983123] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1050. [5.991246] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  1051. [5.999933] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  1052. [6.007351] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  1053. [6.014770] HW.GFX.GMA.Registers.Write: 0x00000001 -> 0x000c5100:PCH_GMBUS0
  1054. [6.022188] HW.GFX.GMA.I2C.Check_And_Reset
  1055. [6.026385] HW.GFX.GMA.Registers.Read: 0x00008800 <- 0x000c5108:PCH_GMBUS2
  1056. [6.033782] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  1057. [6.041222] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  1058. [6.049934] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
  1059. [6.057306] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
  1060. [6.066015] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
  1061. [6.073434] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
  1062. [6.080851] HW.GFX.GMA.I2C.Release_GMBUS
  1063. [6.084832] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  1064. [6.092272] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  1065. [6.099690] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  1066. [6.107205] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1067. [6.115286] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1068. [6.123409] HW.GFX.GMA.Display_Probing.Read_EDID
  1069. [6.128170] HW.GFX.GMA.I2C.I2C_Read
  1070. [6.131684] HW.GFX.GMA.I2C.Init_GMBUS
  1071. [6.135395] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S PCH_DSPCLK_GATE_D
  1072. [6.142737] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1073. [6.150818] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1074. [6.158942] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00008000 & 0x000c5108:PCH_GMBUS2
  1075. [6.167629] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5110:PCH_GMBUS4
  1076. [6.175047] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5120:PCH_GMBUS5
  1077. [6.182466] HW.GFX.GMA.Registers.Write: 0x00000002 -> 0x000c5100:PCH_GMBUS0
  1078. [6.189884] HW.GFX.GMA.I2C.Check_And_Reset
  1079. [6.194081] HW.GFX.GMA.Registers.Read: 0x00008000 <- 0x000c5108:PCH_GMBUS2
  1080. [6.201477] HW.GFX.GMA.Registers.Write: 0x468000a1 -> 0x000c5104:PCH_GMBUS1
  1081. [6.208917] HW.GFX.GMA.Registers.Wait: 0x00000800 <- 0x00000800 & 0x000c5108:PCH_GMBUS2
  1082. [6.217630] HW.GFX.GMA.Registers.Read: 0x00008c00 <- 0x000c5108:PCH_GMBUS2
  1083. [6.225000] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000200 & 0x000c5108:PCH_GMBUS2
  1084. [6.233710] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c5104:PCH_GMBUS1
  1085. [6.241128] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5104:PCH_GMBUS1
  1086. [6.248546] HW.GFX.GMA.I2C.Release_GMBUS
  1087. [6.252526] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c5100:PCH_GMBUS0
  1088. [6.259967] HW.GFX.GMA.Registers.Write: 0x00008000 -> 0x000c5108:PCH_GMBUS2
  1089. [6.267386] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PCH_DSPCLK_GATE_D
  1090. [6.274902] HW.GFX.GMA.Registers.Read: 0x80000000 <- 0x000c2020:PCH_DSPCLK_GATE_D
  1091. [6.282982] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000c2020:PCH_DSPCLK_GATE_D
  1092. [6.291105] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1093. [6.295670] HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS
  1094. [6.303771] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
  1095. [6.312066] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1096. [6.320167] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1097. [6.328365] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1098. [6.336077] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1099. [6.343788] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1100. [6.348375] HW.GFX.GMA.Registers.Read: 0xf0000057 <- 0x00045400:PWR_WELL_CTL_BIOS
  1101. [6.356474] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
  1102. [6.364770] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1103. [6.372872] HW.GFX.GMA.Registers.Read: 0x50000055 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1104. [6.381069] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1105. [6.388781] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1106. [6.396492] HW.GFX.GMA.Registers.Wait: 0x00000040 <- 0x00000040 & 0x00045404:PWR_WELL_CTL_DRIVER
  1107. [6.406059] HW.GFX.GMA.Registers.Unset_Mask: 0x00000080 !S PWR_WELL_CTL_DRIVER
  1108. [6.413769] HW.GFX.GMA.Registers.Read: 0xf00000ff <- 0x00045404:PWR_WELL_CTL_DRIVER
  1109. [6.422065] HW.GFX.GMA.Registers.Write: 0xf000007f -> 0x00045404:PWR_WELL_CTL_DRIVER
  1110. [6.430362] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1111. [6.434949] HW.GFX.GMA.Registers.Read: 0xf0000017 <- 0x00045400:PWR_WELL_CTL_BIOS
  1112. [6.443051] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1113. [6.451347] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1114. [6.459448] HW.GFX.GMA.Registers.Read: 0x50000015 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1115. [6.467648] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1116. [6.475358] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1117. [6.483069] HW.GFX.GMA.Registers.Wait: 0x00000010 <- 0x00000010 & 0x00045404:PWR_WELL_CTL_DRIVER
  1118. [6.492634] HW.GFX.GMA.Registers.Unset_Mask: 0x00000020 !S PWR_WELL_CTL_DRIVER
  1119. [6.500346] HW.GFX.GMA.Registers.Read: 0xf000003f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1120. [6.508641] HW.GFX.GMA.Registers.Write: 0xf000001f -> 0x00045404:PWR_WELL_CTL_DRIVER
  1121. [6.516938] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1122. [6.521526] HW.GFX.GMA.Registers.Read: 0xf0000007 <- 0x00045400:PWR_WELL_CTL_BIOS
  1123. [6.529627] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1124. [6.537923] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1125. [6.546024] HW.GFX.GMA.Registers.Read: 0x50000005 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1126. [6.554223] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1127. [6.561935] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1128. [6.569647] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1129. [6.579213] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PWR_WELL_CTL_DRIVER
  1130. [6.586924] HW.GFX.GMA.Registers.Read: 0xf000000f <- 0x00045404:PWR_WELL_CTL_DRIVER
  1131. [6.595219] HW.GFX.GMA.Registers.Write: 0xf0000007 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1132. [6.603516] HW.GFX.GMA.Power_And_Clocks.PD_Off
  1133. [6.608103] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1134. [6.616204] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1135. [6.624499] HW.GFX.GMA.Registers.Read: 0x40000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1136. [6.632602] HW.GFX.GMA.Registers.Read: 0x50000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1137. [6.640800] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1138. [6.648513] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1139. [6.656223] HW.GFX.GMA.Registers.Wait: 0x40000000 <- 0x40000000 & 0x00045404:PWR_WELL_CTL_DRIVER
  1140. [6.665790] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_BIOS
  1141. [6.673305] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1142. [6.681404] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045400:PWR_WELL_CTL_BIOS
  1143. [6.689505] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PWR_WELL_CTL_DRIVER
  1144. [6.697215] HW.GFX.GMA.Registers.Read: 0xf0000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1145. [6.705512] HW.GFX.GMA.Registers.Write: 0x70000003 -> 0x00045404:PWR_WELL_CTL_DRIVER
  1146.  
  1147. [6.714004] CONFIG =>
  1148. [6.716151] (Primary =>
  1149. [6.718883] (Port => eDP ,
  1150. [6.722396] Framebuffer =>
  1151. [6.725616] (Width => 1920,
  1152. [6.729520] Height => 1080,
  1153. [6.733424] Start_X => 0,
  1154. [6.737034] Start_Y => 0,
  1155. [6.740646] Stride => 1920,
  1156. [6.744549] V_Stride => 1080,
  1157. [6.748454] Tiling => Linear ,
  1158. [6.752650] Rotation => No_Rotation,
  1159. [6.757237] Offset => 0x00000000,
  1160. [6.761434] BPC => 8),
  1161. [6.764849] Mode =>
  1162. [6.767387] (Dotclock => 138500000,
  1163. [6.772659] H_Visible => 1920,
  1164. [6.777440] H_Sync_Begin => 1968,
  1165. [6.782223] H_Sync_End => 2000,
  1166. [6.787007] H_Total => 2080,
  1167. [6.791788] V_Visible => 1080,
  1168. [6.796572] V_Sync_Begin => 1083,
  1169. [6.801355] V_Sync_End => 1088,
  1170. [6.806137] V_Total => 1111,
  1171. [6.810919] H_Sync_Active_High => False,
  1172. [6.815799] V_Sync_Active_High => False,
  1173. [6.820680] BPC => 8)),
  1174. [6.825365] Secondary =>
  1175. [6.828098] (Port => Disabled,
  1176. [6.831611] Framebuffer =>
  1177. [6.834832] (Width => 1,
  1178. [6.838444] Height => 1,
  1179. [6.842055] Start_X => 0,
  1180. [6.845665] Start_Y => 0,
  1181. [6.849276] Stride => 1,
  1182. [6.852886] V_Stride => 1,
  1183. [6.856498] Tiling => Linear ,
  1184. [6.860695] Rotation => No_Rotation,
  1185. [6.865282] Offset => 0x00000000,
  1186. [6.869479] BPC => 8),
  1187. [6.872895] Mode =>
  1188. [6.875432] (Dotclock => 1000000,
  1189. [6.880508] H_Visible => 1,
  1190. [6.884998] H_Sync_Begin => 1,
  1191. [6.889487] H_Sync_End => 1,
  1192. [6.893976] H_Total => 1,
  1193. [6.898465] V_Visible => 1,
  1194. [6.902955] V_Sync_Begin => 1,
  1195. [6.907445] V_Sync_End => 1,
  1196. [6.911933] V_Total => 1,
  1197. [6.916422] H_Sync_Active_High => False,
  1198. [6.921303] V_Sync_Active_High => False,
  1199. [6.926182] BPC => 5)),
  1200. [6.930866] Tertiary =>
  1201. [6.933598] (Port => Disabled,
  1202. [6.937112] Framebuffer =>
  1203. [6.940332] (Width => 1,
  1204. [6.943944] Height => 1,
  1205. [6.947553] Start_X => 0,
  1206. [6.951165] Start_Y => 0,
  1207. [6.954777] Stride => 1,
  1208. [6.958388] V_Stride => 1,
  1209. [6.962000] Tiling => Linear ,
  1210. [6.966197] Rotation => No_Rotation,
  1211. [6.970785] Offset => 0x00000000,
  1212. [6.974981] BPC => 8),
  1213. [6.978397] Mode =>
  1214. [6.980934] (Dotclock => 1000000,
  1215. [6.986010] H_Visible => 1,
  1216. [6.990499] H_Sync_Begin => 1,
  1217. [6.994988] H_Sync_End => 1,
  1218. [6.999479] H_Total => 1,
  1219. [7.003968] V_Visible => 1,
  1220. [7.008457] V_Sync_Begin => 1,
  1221. [7.012947] V_Sync_End => 1,
  1222. [7.017437] V_Total => 1,
  1223. [7.021926] H_Sync_Active_High => False,
  1224. [7.026807] V_Sync_Active_High => False,
  1225. [7.031687] BPC => 5)));
  1226. [7.232980] HW.GFX.GMA.Power_And_Clocks.PD_On
  1227. [7.237281] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045400:PWR_WELL_CTL_BIOS
  1228. [7.245382] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1229. [7.253677] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00045408:PWR_WELL_CTL_KVMR
  1230. [7.261778] HW.GFX.GMA.Registers.Read: 0x10000001 <- 0x0004540c:PWR_WELL_CTL_DEBUG
  1231. [7.269976] HW.GFX.GMA.Registers.Read: 0x050f0000 <- 0x00045410:PWR_WELL_CTL5
  1232. [7.277686] HW.GFX.GMA.Registers.Read: 0x0000050f <- 0x00045414:PWR_WELL_CTL6
  1233. [7.285397] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1234. [7.294962] HW.GFX.GMA.Registers.Set_Mask: 0x00000008 .S PWR_WELL_CTL_DRIVER
  1235. [7.302478] HW.GFX.GMA.Registers.Read: 0x30000003 <- 0x00045404:PWR_WELL_CTL_DRIVER
  1236. [7.310774] HW.GFX.GMA.Registers.Write: 0x3000000b -> 0x00045404:PWR_WELL_CTL_DRIVER
  1237. [7.319072] HW.GFX.GMA.Registers.Wait: 0x00000004 <- 0x00000004 & 0x00045404:PWR_WELL_CTL_DRIVER
  1238.  
  1239. [7.328831] Trying to enable port eDP
  1240. [7.333029] HW.GFX.GMA.Connector_Info.Preferred_Link_Setting
  1241. [7.338982] HW.GFX.GMA.Panel.On
  1242. [7.342106] HW.GFX.GMA.Registers.Is_Set_Mask: PCH_PP_CONTROL
  1243. [7.348079] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL
  1244. [7.355867] HW.GFX.GMA.Registers.Set_Mask: 0x00000001 .S PCH_PP_CONTROL
  1245. [7.362916] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL
  1246. [7.370703] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL
  1247. [7.378533] HW.GFX.GMA.Panel.Wait_On
  1248. [7.382123] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x30000000 & 0x000c7200:PCH_PP_STATUS
  1249. [7.391124] HW.GFX.GMA.Registers.Unset_Mask: 0x00000008 !S PCH_PP_CONTROL
  1250. [7.398345] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL
  1251. [7.406131] HW.GFX.GMA.Registers.Write: 0x00000073 -> 0x000c7204:PCH_PP_CONTROL
  1252. [7.413960] HW.GFX.GMA.DP_Info.Read_Caps
  1253. [7.417942] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1254. [7.423797] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1255. [7.431507] HW.GFX.GMA.Registers.Write: 0x9000000e -> 0x00064014:DDI_AUX_DATA_A_1
  1256. [7.439513] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1257. [7.446053] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1258. [7.453763] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1259. [7.461475] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1260. [7.470455] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1261. [7.478166] HW.GFX.GMA.Registers.Read: 0x00120a02 <- 0x00064014:DDI_AUX_DATA_A_1
  1262. [7.486171] HW.GFX.GMA.Registers.Read: 0x41000001 <- 0x00064018:DDI_AUX_DATA_A_2
  1263. [7.494174] HW.GFX.GMA.Registers.Read: 0x80020000 <- 0x0006401c:DDI_AUX_DATA_A_3
  1264. [7.502177] HW.GFX.GMA.Registers.Read: 0x00000b00 <- 0x00064020:DDI_AUX_DATA_A_4
  1265.  
  1266. [7.510376] DPCD:
  1267. [7.512133] Rev : 0x12
  1268. [7.515743] Max_Link_Rate : 0x0a
  1269. [7.519353] Max_Lane_Count : 0x02
  1270. [7.522966] TPS3_Supported : 0x00
  1271. [7.526576] Enhanced_Framing: 0x00
  1272. [7.530187] No_Aux_Handshake: 0x40
  1273. [7.533797] Aux_RD_Interval : 0x00
  1274.  
  1275. [7.537603] HW.GFX.GMA.DP_Info.Read_eDP_Rates
  1276. [7.542094] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1277. [7.547949] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1278. [7.555660] HW.GFX.GMA.Registers.Write: 0x90070002 -> 0x00064014:DDI_AUX_DATA_A_1
  1279. [7.563661] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1280. [7.570201] HW.GFX.GMA.Registers.Read: 0x4500023f <- 0x00064010:DDI_AUX_CTL_A
  1281. [7.577911] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1282. [7.585620] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1283. [7.594600] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1284. [7.602310] HW.GFX.GMA.Registers.Read: 0x00011800 <- 0x00064014:DDI_AUX_DATA_A_1
  1285. [7.610313] Trying DP settings: Symbol Rate = 270000000; Lane Count = 2
  1286.  
  1287. [7.617536] HW.GFX.GMA.PLLs.Alloc
  1288. [7.620854] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c058:DPLL_CTRL1
  1289. [7.628271] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL1
  1290. [7.634518] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x0006c058:DPLL_CTRL1
  1291. [7.641936] HW.GFX.GMA.Registers.Write: 0x000000c0 -> 0x0006c058:DPLL_CTRL1
  1292. [7.649354] HW.GFX.GMA.Registers.Read: 0x000000c0 <- 0x0006c058:DPLL_CTRL1
  1293. [7.656772] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x00046014:LCPLL2_CTL
  1294. [7.664190] HW.GFX.GMA.Registers.Wait: 0x00000100 <- 0x00000100 & 0x0006c060:DPLL_STATUS
  1295. [7.672996] HW.GFX.GMA.Registers.Unset_And_Set_Mask: SHOTPLUG_CTL
  1296. [7.679435] HW.GFX.GMA.Registers.Read: 0x12001010 <- 0x000c4030:SHOTPLUG_CTL
  1297. [7.687028] HW.GFX.GMA.Registers.Write: 0x13001010 -> 0x000c4030:SHOTPLUG_CTL
  1298. [7.694662] HW.GFX.GMA.Connectors.Pre_On
  1299. [7.698641] HW.GFX.GMA.Connectors.DDI.Pre_On
  1300. [7.703034] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DPLL_CTRL2
  1301. [7.709281] HW.GFX.GMA.Registers.Read: 0x00af8000 <- 0x0006c05c:DPLL_CTRL2
  1302. [7.716698] HW.GFX.GMA.Registers.Write: 0x00af0003 -> 0x0006c05c:DPLL_CTRL2
  1303. [7.724117] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Train_DP
  1304. [7.730266] HW.GFX.GMA.Registers.Write: 0x80000080 -> 0x00064040:DP_TP_CTL_A
  1305. [7.737781] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1306. [7.743637] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1307. [7.751347] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1308. [7.757886] HW.GFX.GMA.Registers.Read: 0x00000091 <- 0x00064000:DDI_BUF_CTL_A
  1309. [7.765596] HW.GFX.GMA.Registers.Write: 0x80000093 -> 0x00064000:DDI_BUF_CTL_A
  1310. [7.773307] HW.GFX.GMA.Registers.Read: 0x80000093 <- 0x00064000:DDI_BUF_CTL_A
  1311. [7.781618] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Init
  1312. [7.787666] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1313. [7.793522] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1314. [7.801232] HW.GFX.GMA.Registers.Write: 0x80010001 -> 0x00064014:DDI_AUX_DATA_A_1
  1315. [7.809236] HW.GFX.GMA.Registers.Write: 0x0a020000 -> 0x00064018:DDI_AUX_DATA_A_2
  1316. [7.817240] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1317. [7.823780] HW.GFX.GMA.Registers.Read: 0x4440023f <- 0x00064010:DDI_AUX_CTL_A
  1318. [7.831490] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1319. [7.839201] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1320. [7.848182] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1321. [7.855892] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1322. [7.863896] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1323. [7.869753] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1324. [7.877464] HW.GFX.GMA.Registers.Write: 0x80010701 -> 0x00064014:DDI_AUX_DATA_A_1
  1325. [7.885467] HW.GFX.GMA.Registers.Write: 0x00010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1326. [7.893470] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1327. [7.900008] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1328. [7.907719] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1329. [7.915429] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1330. [7.924409] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1331. [7.932120] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1332. [7.940124] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1333. [7.947932] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1334. [7.953787] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1335. [7.961497] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1336. [7.969501] HW.GFX.GMA.Registers.Write: 0x21000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1337. [7.977505] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1338. [7.984043] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1339. [7.991756] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1340. [7.999465] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1341. [8.008445] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1342. [8.016156] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1343. [8.024260] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1344. [8.031401] HW.GFX.GMA.DP_Info.Read_Link_Status
  1345. [8.036085] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1346. [8.041943] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1347. [8.049653] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1348. [8.057656] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1349. [8.064197] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1350. [8.071908] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1351. [8.079620] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1352. [8.088600] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1353. [8.096310] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1354. [8.104313] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1355.  
  1356. [8.112513] Link Status:
  1357. [8.114952] Lane0:
  1358. [8.117001] CR_Done : 0
  1359. [8.120417] Channel_EQ_Done: 0
  1360. [8.123834] Symbol_Locked : 0
  1361. [8.127249] Lane1:
  1362. [8.129298] CR_Done : 0
  1363. [8.132716] Channel_EQ_Done: 0
  1364. [8.136131] Symbol_Locked : 0
  1365. [8.139548] Interlane_Align_Done: 0
  1366. [8.143257] Adjust0:
  1367. [8.145501] Voltage_Swing: 1
  1368. [8.148721] Pre_Emph : 0
  1369. [8.151942] Adjust1:
  1370. [8.154186] Voltage_Swing: 1
  1371. [8.157407] Pre_Emph : 0
  1372.  
  1373. [8.160823] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1374. [8.166679] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1375. [8.174388] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1376. [8.180927] HW.GFX.GMA.Registers.Read: 0x80000013 <- 0x00064000:DDI_BUF_CTL_A
  1377. [8.188637] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1378. [8.196348] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1379. [8.204059] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1380. [8.211574] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1381. [8.217429] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1382. [8.225140] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1383. [8.233142] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1384. [8.241145] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1385. [8.247684] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1386. [8.255395] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1387. [8.263106] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1388. [8.272086] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1389. [8.279795] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1390. [8.287900] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1391. [8.295042] HW.GFX.GMA.DP_Info.Read_Link_Status
  1392. [8.299726] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1393. [8.305582] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1394. [8.313291] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1395. [8.321296] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1396. [8.327834] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1397. [8.335544] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1398. [8.343256] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1399. [8.352237] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1400. [8.359948] HW.GFX.GMA.Registers.Read: 0x00000080 <- 0x00064014:DDI_AUX_DATA_A_1
  1401. [8.367949] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1402.  
  1403. [8.376147] Link Status:
  1404. [8.378586] Lane0:
  1405. [8.380635] CR_Done : 0
  1406. [8.384051] Channel_EQ_Done: 0
  1407. [8.387467] Symbol_Locked : 0
  1408. [8.390883] Lane1:
  1409. [8.392932] CR_Done : 0
  1410. [8.396349] Channel_EQ_Done: 0
  1411. [8.399763] Symbol_Locked : 0
  1412. [8.403180] Interlane_Align_Done: 0
  1413. [8.406888] Adjust0:
  1414. [8.409133] Voltage_Swing: 1
  1415. [8.412354] Pre_Emph : 0
  1416. [8.415573] Adjust1:
  1417. [8.417817] Voltage_Swing: 1
  1418. [8.421038] Pre_Emph : 0
  1419.  
  1420. [8.424455] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_BUF_CTL_A
  1421. [8.430310] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1422. [8.438021] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_BUF_CTL_A
  1423. [8.444560] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1424. [8.452269] HW.GFX.GMA.Registers.Write: 0x84000013 -> 0x00064000:DDI_BUF_CTL_A
  1425. [8.459980] HW.GFX.GMA.Registers.Read: 0x84000013 <- 0x00064000:DDI_BUF_CTL_A
  1426. [8.467692] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Signal_Levels
  1427. [8.475207] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1428. [8.481062] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1429. [8.488772] HW.GFX.GMA.Registers.Write: 0x80010301 -> 0x00064014:DDI_AUX_DATA_A_1
  1430. [8.496775] HW.GFX.GMA.Registers.Write: 0x01010000 -> 0x00064018:DDI_AUX_DATA_A_2
  1431. [8.504778] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1432. [8.511316] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1433. [8.519027] HW.GFX.GMA.Registers.Write: 0xd660023f -> 0x00064010:DDI_AUX_CTL_A
  1434. [8.526738] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1435. [8.535717] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1436. [8.543428] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1437. [8.551533] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1438. [8.558677] HW.GFX.GMA.DP_Info.Read_Link_Status
  1439. [8.563361] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1440. [8.569219] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1441. [8.576930] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1442. [8.584933] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1443. [8.591472] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1444. [8.599183] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1445. [8.606893] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1446. [8.615874] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1447. [8.623583] HW.GFX.GMA.Registers.Read: 0x00110080 <- 0x00064014:DDI_AUX_DATA_A_1
  1448. [8.631587] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1449.  
  1450. [8.639784] Link Status:
  1451. [8.642224] Lane0:
  1452. [8.644275] CR_Done : 1
  1453. [8.647690] Channel_EQ_Done: 0
  1454. [8.651107] Symbol_Locked : 0
  1455. [8.654522] Lane1:
  1456. [8.656573] CR_Done : 1
  1457. [8.659989] Channel_EQ_Done: 0
  1458. [8.663404] Symbol_Locked : 0
  1459. [8.666821] Interlane_Align_Done: 0
  1460. [8.670528] Adjust0:
  1461. [8.672774] Voltage_Swing: 1
  1462. [8.675994] Pre_Emph : 0
  1463. [8.679215] Adjust1:
  1464. [8.681459] Voltage_Swing: 1
  1465. [8.684680] Pre_Emph : 0
  1466.  
  1467. [8.688095] HW.GFX.GMA.Registers.Write: 0x80000180 -> 0x00064040:DP_TP_CTL_A
  1468. [8.695610] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1469. [8.703419] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1470. [8.709275] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1471. [8.716986] HW.GFX.GMA.Registers.Write: 0x80010202 -> 0x00064014:DDI_AUX_DATA_A_1
  1472. [8.724988] HW.GFX.GMA.Registers.Write: 0x22010100 -> 0x00064018:DDI_AUX_DATA_A_2
  1473. [8.732990] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1474. [8.739530] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1475. [8.747241] HW.GFX.GMA.Registers.Write: 0xd670023f -> 0x00064010:DDI_AUX_CTL_A
  1476. [8.754952] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1477. [8.763931] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1478. [8.771642] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1479. [8.780046] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Adjust_Training
  1480. [8.787177] HW.GFX.GMA.DP_Info.Read_Link_Status
  1481. [8.791863] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1482. [8.797719] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1483. [8.805431] HW.GFX.GMA.Registers.Write: 0x90020205 -> 0x00064014:DDI_AUX_DATA_A_1
  1484. [8.813435] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1485. [8.819977] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1486. [8.827688] HW.GFX.GMA.Registers.Write: 0xd640023f -> 0x00064010:DDI_AUX_CTL_A
  1487. [8.835400] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1488. [8.844379] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1489. [8.852090] HW.GFX.GMA.Registers.Read: 0x00770081 <- 0x00064014:DDI_AUX_DATA_A_1
  1490. [8.860093] HW.GFX.GMA.Registers.Read: 0x00110000 <- 0x00064018:DDI_AUX_DATA_A_2
  1491.  
  1492. [8.868293] Link Status:
  1493. [8.870733] Lane0:
  1494. [8.872784] CR_Done : 1
  1495. [8.876199] Channel_EQ_Done: 1
  1496. [8.879614] Symbol_Locked : 1
  1497. [8.883031] Lane1:
  1498. [8.885079] CR_Done : 1
  1499. [8.888495] Channel_EQ_Done: 1
  1500. [8.891912] Symbol_Locked : 1
  1501. [8.895328] Interlane_Align_Done: 1
  1502. [8.899036] Adjust0:
  1503. [8.901282] Voltage_Swing: 1
  1504. [8.904503] Pre_Emph : 0
  1505. [8.907725] Adjust1:
  1506. [8.909970] Voltage_Swing: 1
  1507. [8.913190] Pre_Emph : 0
  1508.  
  1509. [8.916608] HW.GFX.GMA.Connectors.DDI.Pre_On.Training.Sink_Set_Training_Pattern
  1510. [8.924416] HW.GFX.GMA.Registers.Is_Set_Mask: DDI_AUX_CTL_A
  1511. [8.930272] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1512. [8.937984] HW.GFX.GMA.Registers.Write: 0x80010200 -> 0x00064014:DDI_AUX_DATA_A_1
  1513. [8.945987] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00064018:DDI_AUX_DATA_A_2
  1514. [8.953992] HW.GFX.GMA.Registers.Unset_And_Set_Mask: DDI_AUX_CTL_A
  1515. [8.960531] HW.GFX.GMA.Registers.Read: 0x4470023f <- 0x00064010:DDI_AUX_CTL_A
  1516. [8.968244] HW.GFX.GMA.Registers.Write: 0xd650023f -> 0x00064010:DDI_AUX_CTL_A
  1517. [8.975955] HW.GFX.GMA.Registers.Wait: 0x00000000 <- 0x80000000 & 0x00064010:DDI_AUX_CTL_A
  1518. [8.984936] HW.GFX.GMA.Registers.Read: 0x4410023f <- 0x00064010:DDI_AUX_CTL_A
  1519. [8.992646] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00064014:DDI_AUX_DATA_A_1
  1520. [9.000649] HW.GFX.GMA.Registers.Write: 0x80000200 -> 0x00064040:DP_TP_CTL_A
  1521. [9.008166] HW.GFX.GMA.Registers.Write: 0x80000300 -> 0x00064040:DP_TP_CTL_A
  1522. [9.015684] HW.GFX.GMA.Pipe_Setup.On
  1523. [9.019295] HW.GFX.GMA.Transcoder.Setup
  1524. [9.023198] HW.GFX.GMA.Transcoder.Setup_Link
  1525. [9.027590] HW.GFX.GMA.DP_Info.Calculate_M_N
  1526. [9.031984] HW.GFX.GMA.Registers.Write: 0x7e627d27 -> 0x0006f030:PIPE_EDP_DATA_M1
  1527. [9.039986] HW.GFX.GMA.Registers.Write: 0x00800000 -> 0x0006f034:PIPE_EDP_DATA_N1
  1528. [9.047991] HW.GFX.GMA.Registers.Write: 0x00083518 -> 0x0006f040:PIPE_EDP_LINK_M1
  1529. [9.055995] HW.GFX.GMA.Registers.Write: 0x00100000 -> 0x0006f044:PIPE_EDP_LINK_N1
  1530. [9.063999] HW.GFX.GMA.Registers.Write: 0x00000021 -> 0x0006f410:PIPE_EDP_MSA_MISC
  1531. [9.072100] HW.GFX.GMA.Registers.Write: 0x081f077f -> 0x0006f000:HTOTAL_EDP
  1532. [9.079518] HW.GFX.GMA.Registers.Write: 0x081f077f -> 0x0006f004:HBLANK_EDP
  1533. [9.086938] HW.GFX.GMA.Registers.Write: 0x07cf07af -> 0x0006f008:HSYNC_EDP
  1534. [9.094259] HW.GFX.GMA.Registers.Write: 0x04560437 -> 0x0006f00c:VTOTAL_EDP
  1535. [9.101677] HW.GFX.GMA.Registers.Write: 0x04560437 -> 0x0006f010:VBLANK_EDP
  1536. [9.109097] HW.GFX.GMA.Registers.Write: 0x043f043a -> 0x0006f014:VSYNC_EDP
  1537. [9.116419] HW.GFX.GMA.Pipe_Setup.Setup_FB
  1538. [9.120616] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
  1539. [9.127937] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
  1540. [9.135258] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
  1541. [9.142677] HW.GFX.GMA.Pipe_Setup.Setup_Display
  1542. [9.147362] HW.GFX.GMA.Registers.Write: 0x009f0008 -> 0x0007027c:PLANE_BUF_CFG_1_A
  1543. [9.155463] HW.GFX.GMA.Registers.Write: 0x80008098 -> 0x00070240:PLANE_WM_1_A_0
  1544. [9.163272] HW.GFX.GMA.Registers.Write: 0x00070000 -> 0x0007017c:CUR_BUF_CFG_A
  1545. [9.170984] HW.GFX.GMA.Registers.Write: 0x80008008 -> 0x00070140:CUR_WM_A_0
  1546. [9.178402] HW.GFX.GMA.Pipe_Setup.Setup_Hires_Plane
  1547. [9.183479] HW.GFX.GMA.Registers.Write: 0x84002000 -> 0x00070180:DSPACNTR
  1548. [9.190700] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x000701a4:DSPATILEOFF
  1549. [9.198216] HW.GFX.GMA.Registers.Write: 0x0437077f -> 0x00070190:PLANE_SIZE_1_A
  1550. [9.206027] HW.GFX.GMA.Registers.Write: 0x00000078 -> 0x00070188:DSPASTRIDE
  1551. [9.213445] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007018c:PLANE_POS_1_A
  1552. [9.221155] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x0007019c:DSPASURF
  1553. [9.228380] HW.GFX.GMA.Registers.Write: 0x077f0437 -> 0x0006001c:PIPEASRC
  1554. [9.235603] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070030:PIPEAMISC
  1555. [9.242923] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_1_A
  1556. [9.249852] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068180:PS_CTRL_1_A
  1557. [9.257369] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068180:PS_CTRL_1_A
  1558. [9.264884] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068174:PS_WIN_SZ_1_A
  1559. [9.272596] HW.GFX.GMA.Registers.Unset_Mask: 0x80000000 !S PS_CTRL_2_A
  1560. [9.279525] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x00068280:PS_CTRL_2_A
  1561. [9.287041] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068280:PS_CTRL_2_A
  1562. [9.294558] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00068274:PS_WIN_SZ_2_A
  1563. [9.302268] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070080:CUR_CTL_A
  1564. [9.309587] HW.GFX.GMA.Registers.Write: 0x80208020 -> 0x00070088:CUR_POS_A
  1565. [9.316908] HW.GFX.GMA.Registers.Write: 0x00000000 -> 0x00070084:CUR_BASE_A
  1566. [9.324324] HW.GFX.GMA.Registers.Write: 0x82000002 -> 0x0006f400:PIPE_EDP_DDI_FUNC_CTL
  1567. [9.332817] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x0007f008:PIPE_EDP_CONF
  1568. [9.340528] HW.GFX.GMA.Registers.Read: 0xc0000000 <- 0x0007f008:PIPE_EDP_CONF
  1569. [9.348239] HW.GFX.GMA.Connectors.Post_On
  1570. [9.352337] HW.GFX.GMA.Connectors.DDI.Post_On
  1571. [9.356828] HW.GFX.GMA.Panel.Backlight_On
  1572. [9.360929] HW.GFX.GMA.Registers.Set_Mask: 0x80000000 .S BLC_PWM_PCH_CTL1
  1573. [9.368173] HW.GFX.GMA.Registers.Read: 0x00000000 <- 0x000c8250:BLC_PWM_PCH_CTL1
  1574. [9.376156] HW.GFX.GMA.Registers.Write: 0x80000000 -> 0x000c8250:BLC_PWM_PCH_CTL1
  1575. [9.384182] HW.GFX.GMA.Registers.Set_Mask: 0x00000004 .S PCH_PP_CONTROL
  1576. [9.391210] HW.GFX.GMA.Registers.Read: 0x00000073 <- 0x000c7204:PCH_PP_CONTROL
  1577. [9.398999] HW.GFX.GMA.Registers.Write: 0x00000077 -> 0x000c7204:PCH_PP_CONTROL
  1578. [9.406829] Enabled port eDP
  1579. framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
  1580. x_res x y_res: 1920 x 1080, size: 8294400 at 0xa0000000
  1581. PCI: 00:02.0 init finished in 7025 msecs
  1582. PCI: 00:04.0 init
  1583. PCI: 00:04.0 init finished in 0 msecs
  1584. PCI: 00:08.0 init
  1585. PCI: 00:08.0 init finished in 0 msecs
  1586. PCI: 00:12.0 init
  1587. PCI: 00:12.0 init finished in 0 msecs
  1588. PCI: 00:14.0 init
  1589. PCI: 00:14.0 init finished in 0 msecs
  1590. PCI: 00:14.2 init
  1591. PCI: 00:14.2 init finished in 0 msecs
  1592. PCI: 00:15.0 init
  1593. I2C bus 0 version 0x3132322a
  1594. DW I2C bus 0 at 0x9fa27000 (400 KHz)
  1595. PCI: 00:15.0 init finished in 6 msecs
  1596. PCI: 00:15.1 init
  1597. I2C bus 1 version 0x3132322a
  1598. DW I2C bus 1 at 0x9fa28000 (400 KHz)
  1599. PCI: 00:15.1 init finished in 6 msecs
  1600. PCI: 00:1a.0 init
  1601. PCI: 00:1a.0 init finished in 0 msecs
  1602. PCI: 00:1d.0 init
  1603. Initializing PCH PCIe bridge.
  1604. PCI: 00:1d.0 init finished in 3 msecs
  1605. PCI: 00:1f.0 init
  1606. IOAPIC: Initializing IOAPIC at 0xfec00000
  1607. IOAPIC: Bootstrap Processor Local APIC = 0x00
  1608. IOAPIC: ID = 0x02
  1609. PCI: 00:1f.0 init finished in 11 msecs
  1610. PCI: 00:1f.3 init
  1611. HDA: codec_mask = 01
  1612. HDA: Initializing codec #0
  1613. HDA: codec viddid: 10ec0256
  1614. HDA: verb not loaded
  1615. PCI: 00:1f.3 init finished in 18 msecs
  1616. PCI: 00:1f.4 init
  1617. PCI: 00:1f.4 init finished in 0 msecs
  1618. PCI: 01:00.0 init
  1619. PCI: 01:00.0 init finished in 0 msecs
  1620. PNP: 004e.0 init
  1621. IT8987: Initializing keyboard.
  1622. PNP: 004e.0 init finished in 11 msecs
  1623. Devices initialized
  1624. BS: BS_DEV_INIT run times (exec / console): 7014 / 171 ms
  1625. FMAP: area SMMSTORE found @ 430000 (262144 bytes)
  1626. SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
  1627. smm store: 4 # blocks with size 0x10000
  1628. SMMSTORE: Setting up SMI handler
  1629. apm_control: Disabling ACPI.
  1630. APMC done.
  1631. BS: BS_DEV_INIT exit times (exec / console): 0 / 23 ms
  1632. Finalize devices...
  1633. PCI: 00:17.0 final
  1634. Devices finalized
  1635. BS: BS_POST_DEVICE run times (exec / console): 0 / 6 ms
  1636. HECI: No CSE device
  1637. BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 2 ms
  1638. CBFS: Found 'fallback/dsdt.aml' @0x60400 size 0x357d in mcache @0x99c4c1e8
  1639. CBFS: 'fallback/slic' not found.
  1640. ACPI: Writing ACPI tables at 99b36000.
  1641. ACPI: * FACS
  1642. ACPI: * DSDT
  1643. PCI space above 4GB MMIO is at 0x45e800000, len = 0x7ba1800000
  1644. ACPI: * FADT
  1645. SCI is IRQ9
  1646. ACPI: added table 1/32, length now 40
  1647. ACPI: * SSDT
  1648. Found 1 CPU(s) with 6/12 physical/logical core(s) each.
  1649. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1650. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1651. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1652. PSS: 800MHz power 10534 control 0x800 status 0x800
  1653. PSS: 600MHz power 7709 control 0x600 status 0x600
  1654. PSS: 400MHz power 5014 control 0x400 status 0x400
  1655. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1656. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1657. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1658. PSS: 800MHz power 10534 control 0x800 status 0x800
  1659. PSS: 600MHz power 7709 control 0x600 status 0x600
  1660. PSS: 400MHz power 5014 control 0x400 status 0x400
  1661. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1662. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1663. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1664. PSS: 800MHz power 10534 control 0x800 status 0x800
  1665. PSS: 600MHz power 7709 control 0x600 status 0x600
  1666. PSS: 400MHz power 5014 control 0x400 status 0x400
  1667. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1668. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1669. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1670. PSS: 800MHz power 10534 control 0x800 status 0x800
  1671. PSS: 600MHz power 7709 control 0x600 status 0x600
  1672. PSS: 400MHz power 5014 control 0x400 status 0x400
  1673. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1674. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1675. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1676. PSS: 800MHz power 10534 control 0x800 status 0x800
  1677. PSS: 600MHz power 7709 control 0x600 status 0x600
  1678. PSS: 400MHz power 5014 control 0x400 status 0x400
  1679. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1680. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1681. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1682. PSS: 800MHz power 10534 control 0x800 status 0x800
  1683. PSS: 600MHz power 7709 control 0x600 status 0x600
  1684. PSS: 400MHz power 5014 control 0x400 status 0x400
  1685. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1686. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1687. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1688. PSS: 800MHz power 10534 control 0x800 status 0x800
  1689. PSS: 600MHz power 7709 control 0x600 status 0x600
  1690. PSS: 400MHz power 5014 control 0x400 status 0x400
  1691. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1692. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1693. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1694. PSS: 800MHz power 10534 control 0x800 status 0x800
  1695. PSS: 600MHz power 7709 control 0x600 status 0x600
  1696. PSS: 400MHz power 5014 control 0x400 status 0x400
  1697. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1698. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1699. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1700. PSS: 800MHz power 10534 control 0x800 status 0x800
  1701. PSS: 600MHz power 7709 control 0x600 status 0x600
  1702. PSS: 400MHz power 5014 control 0x400 status 0x400
  1703. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1704. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1705. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1706. PSS: 800MHz power 10534 control 0x800 status 0x800
  1707. PSS: 600MHz power 7709 control 0x600 status 0x600
  1708. PSS: 400MHz power 5014 control 0x400 status 0x400
  1709. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1710. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1711. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1712. PSS: 800MHz power 10534 control 0x800 status 0x800
  1713. PSS: 600MHz power 7709 control 0x600 status 0x600
  1714. PSS: 400MHz power 5014 control 0x400 status 0x400
  1715. PSS: 1101MHz power 15000 control 0x2f00 status 0x2f00
  1716. PSS: 1100MHz power 15000 control 0xb00 status 0xb00
  1717. PSS: 1000MHz power 13471 control 0xa00 status 0xa00
  1718. PSS: 800MHz power 10534 control 0x800 status 0x800
  1719. PSS: 600MHz power 7709 control 0x600 status 0x600
  1720. PSS: 400MHz power 5014 control 0x400 status 0x400
  1721. \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
  1722. \_SB.PCI0.I2C0.H02C: Touchpad at I2C: 00:2c
  1723. ACPI: added table 2/32, length now 44
  1724. ACPI: * MCFG
  1725. ACPI: added table 3/32, length now 48
  1726. ACPI: * LPIT
  1727. ACPI: added table 4/32, length now 52
  1728. ACPI: * MADT
  1729. SCI is IRQ9
  1730. ACPI: added table 5/32, length now 56
  1731. current = 99b3b820
  1732. ACPI: * DMAR
  1733. ACPI: added table 6/32, length now 60
  1734. ACPI: added table 7/32, length now 64
  1735. ACPI: * HPET
  1736. ACPI: added table 8/32, length now 68
  1737. ACPI: done.
  1738. ACPI tables: 22864 bytes.
  1739. smbios_write_tables: 99b35000
  1740. Create SMBIOS type 16
  1741. Create SMBIOS type 17
  1742. GENERIC: 0.0 (WIFI Device)
  1743. SMBIOS tables: 975 bytes.
  1744. Writing table forward entry at 0x00000500
  1745. Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum c628
  1746. Writing coreboot table at 0x99b5a000
  1747. CBFS: Found 'cmos_layout.bin' @0xf22c0 size 0x3ec in mcache @0x99c4c2ac
  1748. 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  1749. 1. 0000000000001000-000000000009ffff: RAM
  1750. 2. 00000000000a0000-00000000000fffff: RESERVED
  1751. 3. 0000000000100000-0000000099b34fff: RAM
  1752. 4. 0000000099b35000-0000000099bb8fff: CONFIGURATION TABLES
  1753. 5. 0000000099bb9000-0000000099c1efff: RAMSTAGE
  1754. 6. 0000000099c1f000-0000000099ffefff: CONFIGURATION TABLES
  1755. 7. 0000000099fff000-000000009f7fffff: RESERVED
  1756. 8. 00000000e0000000-00000000efffffff: RESERVED
  1757. 9. 00000000fc000000-00000000fc000fff: RESERVED
  1758. 10. 00000000fe000000-00000000fe00ffff: RESERVED
  1759. 11. 00000000fed10000-00000000fed17fff: RESERVED
  1760. 12. 00000000fed80000-00000000fed83fff: RESERVED
  1761. 13. 00000000fed90000-00000000fed91fff: RESERVED
  1762. 14. 00000000feda0000-00000000feda1fff: RESERVED
  1763. 15. 0000000100000000-000000045e7fffff: RAM
  1764. Wrote coreboot table at: 0x99b5a000, 0x8f0 bytes, checksum afde
  1765. coreboot table: 2312 bytes.
  1766. IMD ROOT 0. 0x99ffe000 0x00001000
  1767. IMD SMALL 1. 0x99ffd000 0x00001000
  1768. FSP MEMORY 2. 0x99c4d000 0x003b0000
  1769. RO MCACHE 3. 0x99c4c000 0x000003e8
  1770. CONSOLE 4. 0x99c2c000 0x00020000
  1771. TIME STAMP 5. 0x99c2b000 0x00000910
  1772. ROMSTG STCK 6. 0x99c2a000 0x00001000
  1773. AFTER CAR 7. 0x99c1f000 0x0000b000
  1774. RAMSTAGE 8. 0x99bb8000 0x00067000
  1775. REFCODE 9. 0x99b84000 0x00034000
  1776. SMM BACKUP 10. 0x99b74000 0x00010000
  1777. 4f444749 11. 0x99b72000 0x00002000
  1778. 53534d32 12. 0x99b62000 0x00010000
  1779. COREBOOT 13. 0x99b5a000 0x00008000
  1780. ACPI 14. 0x99b36000 0x00024000
  1781. SMBIOS 15. 0x99b35000 0x00000800
  1782. IMD small region:
  1783. IMD ROOT 0. 0x99ffdc00 0x00000400
  1784. FSP RUNTIME 1. 0x99ffdbe0 0x00000004
  1785. FMAP 2. 0x99ffda80 0x0000015e
  1786. POWER STATE 3. 0x99ffda40 0x00000040
  1787. ROMSTAGE 4. 0x99ffda20 0x00000004
  1788. MEM INFO 5. 0x99ffd840 0x000001e0
  1789. ACPI GNVS 6. 0x99ffd740 0x00000100
  1790. BS: BS_WRITE_TABLES run times (exec / console): 3 / 669 ms
  1791. MTRR: Physical address space:
  1792. 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
  1793. 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
  1794. 0x00000000000c0000 - 0x0000000099fff000 size 0x99f3f000 type 6
  1795. 0x0000000099fff000 - 0x00000000a0000000 size 0x06001000 type 0
  1796. 0x00000000a0000000 - 0x00000000b0000000 size 0x10000000 type 1
  1797. 0x00000000b0000000 - 0x0000000100000000 size 0x50000000 type 0
  1798. 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
  1799. MTRR: Fixed MSR 0x250 0x0606060606060606
  1800. MTRR: Fixed MSR 0x258 0x0606060606060606
  1801. MTRR: Fixed MSR 0x259 0x0000000000000000
  1802. MTRR: Fixed MSR 0x268 0x0606060606060606
  1803. MTRR: Fixed MSR 0x269 0x0606060606060606
  1804. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1805. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1806. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1807. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1808. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1809. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1810. CPU physical address size: 39 bits
  1811. MTRR: default type WB/UC MTRR counts: 6/9.
  1812. MTRR: WB selected as default type.
  1813. MTRR: 0 base 0x0000000099fff000 mask 0x0000007ffffff000 type 0
  1814. MTRR: 1 base 0x000000009a000000 mask 0x0000007ffe000000 type 0
  1815. MTRR: 2 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
  1816. MTRR: 3 base 0x00000000a0000000 mask 0x0000007ff0000000 type 1
  1817. MTRR: 4 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0
  1818. MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
  1819. MTRR: Fixed MSR 0x250 0x0606060606060606
  1820. MTRR: Fixed MSR 0x258 0x0606060606060606
  1821. MTRR: Fixed MSR 0x259 0x0000000000000000
  1822. MTRR: Fixed MSR 0x268 0x0606060606060606
  1823. MTRR: Fixed MSR 0x269 0x0606060606060606
  1824. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1825. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1826. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1827. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1828. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1829. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1830.  
  1831. MTRR check
  1832. Fixed MTRRs : Enabled
  1833. Variable MTRRs: Enabled
  1834.  
  1835. CPU physical address size: 39 bits
  1836. BS: BS_WRITE_TABLES exit times (exec / console): 46 / 148 ms
  1837. MTRR: Fixed MSR 0x250 0x0606060606060606
  1838. MTRR: Fixed MSR 0x250 0x0606060606060606
  1839. MTRR: Fixed MSR 0x258 0x0606060606060606
  1840. MTRR: Fixed MSR 0x259 0x0000000000000000
  1841. MTRR: Fixed MSR 0x268 0x0606060606060606
  1842. MTRR: Fixed MSR 0x269 0x0606060606060606
  1843. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1844. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1845. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1846. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1847. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1848. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1849. MTRR: Fixed MSR 0x258 0x0606060606060606
  1850. CPU physical address size: 39 bits
  1851. MTRR: Fixed MSR 0x259 0x0000000000000000
  1852. MTRR: Fixed MSR 0x268 0x0606060606060606
  1853. MTRR: Fixed MSR 0x269 0x0606060606060606
  1854. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1855. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1856. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1857. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1858. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1859. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1860. MTRR: Fixed MSR 0x250 0x0606060606060606
  1861. MTRR: Fixed MSR 0x258 0x0606060606060606
  1862. MTRR: Fixed MSR 0x259 0x0000000000000000
  1863. MTRR: Fixed MSR 0x268 0x0606060606060606
  1864. MTRR: Fixed MSR 0x269 0x0606060606060606
  1865. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1866. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1867. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1868. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1869. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1870. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1871. MTRR: Fixed MSR 0x250 0x0606060606060606
  1872. CPU physical address size: 39 bits
  1873. MTRR: Fixed MSR 0x258 0x0606060606060606
  1874. MTRR: Fixed MSR 0x259 0x0000000000000000
  1875. MTRR: Fixed MSR 0x268 0x0606060606060606
  1876. MTRR: Fixed MSR 0x269 0x0606060606060606
  1877. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1878. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1879. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1880. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1881. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1882. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1883. MTRR: Fixed MSR 0x250 0x0606060606060606
  1884. MTRR: Fixed MSR 0x250 0x0606060606060606
  1885. MTRR: Fixed MSR 0x258 0x0606060606060606
  1886. MTRR: Fixed MSR 0x259 0x0000000000000000
  1887. MTRR: Fixed MSR 0x268 0x0606060606060606
  1888. MTRR: Fixed MSR 0x269 0x0606060606060606
  1889. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1890. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1891. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1892. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1893. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1894. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1895. MTRR: Fixed MSR 0x258 0x0606060606060606
  1896. CPU physical address size: 39 bits
  1897. MTRR: Fixed MSR 0x259 0x0000000000000000
  1898. MTRR: Fixed MSR 0x268 0x0606060606060606
  1899. MTRR: Fixed MSR 0x269 0x0606060606060606
  1900. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1901. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1902. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1903. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1904. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1905. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1906. CPU physical address size: 39 bits
  1907. CPU physical address size: 39 bits
  1908. MTRR: Fixed MSR 0x250 0x0606060606060606
  1909. MTRR: Fixed MSR 0x258 0x0606060606060606
  1910. MTRR: Fixed MSR 0x259 0x0000000000000000
  1911. MTRR: Fixed MSR 0x268 0x0606060606060606
  1912. MTRR: Fixed MSR 0x269 0x0606060606060606
  1913. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1914. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1915. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1916. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1917. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1918. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1919. MTRR: Fixed MSR 0x250 0x0606060606060606
  1920. CPU physical address size: 39 bits
  1921. MTRR: Fixed MSR 0x258 0x0606060606060606
  1922. MTRR: Fixed MSR 0x259 0x0000000000000000
  1923. MTRR: Fixed MSR 0x268 0x0606060606060606
  1924. MTRR: Fixed MSR 0x269 0x0606060606060606
  1925. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1926. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1927. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1928. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1929. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1930. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1931. CPU physical address size: 39 bits
  1932. CPU physical address size: 39 bits
  1933. CBFS: Found 'fallback/payload' @0x126700 size 0xb8cec in mcache @0x99c4c358
  1934. MTRR: Fixed MSR 0x250 0x0606060606060606
  1935. MTRR: Fixed MSR 0x250 0x0606060606060606
  1936. MTRR: Fixed MSR 0x258 0x0606060606060606
  1937. MTRR: Fixed MSR 0x259 0x0000000000000000
  1938. MTRR: Fixed MSR 0x268 0x0606060606060606
  1939. MTRR: Fixed MSR 0x269 0x0606060606060606
  1940. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1941. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1942. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1943. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1944. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1945. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1946. MTRR: Fixed MSR 0x258 0x0606060606060606
  1947. CPU physical address size: 39 bits
  1948. MTRR: Fixed MSR 0x259 0x0000000000000000
  1949. MTRR: Fixed MSR 0x268 0x0606060606060606
  1950. MTRR: Fixed MSR 0x269 0x0606060606060606
  1951. MTRR: Fixed MSR 0x26a 0x0606060606060606
  1952. MTRR: Fixed MSR 0x26b 0x0606060606060606
  1953. MTRR: Fixed MSR 0x26c 0x0606060606060606
  1954. MTRR: Fixed MSR 0x26d 0x0606060606060606
  1955. MTRR: Fixed MSR 0x26e 0x0606060606060606
  1956. MTRR: Fixed MSR 0x26f 0x0606060606060606
  1957. Checking segment from ROM address 0xff5b692c
  1958. CPU physical address size: 39 bits
  1959. Checking segment from ROM address 0xff5b6948
  1960. Loading segment from ROM address 0xff5b692c
  1961. code (compression=1)
  1962. New segment dstaddr 0x00800000 memsize 0x800000 srcaddr 0xff5b6964 filesize 0xb8cb4
  1963. Loading Segment: addr: 0x00800000 memsz: 0x0000000000800000 filesz: 0x00000000000b8cb4
  1964. using LZMA
  1965. Loading segment from ROM address 0xff5b6948
  1966. Entry Point 0x00803120
  1967. BS: BS_PAYLOAD_LOAD run times (exec / console): 812 / 48 ms
  1968. Finalizing chipset.
  1969. apm_control: Finalizing SMM.
  1970. APMC done.
  1971. BS: BS_PAYLOAD_LOAD exit times (exec / console): 2 / 6 ms
  1972. mp_park_aps done after 0 msecs.
  1973. Jumping to boot code at 0x00803120(0x99b5a000)
  1974.  
  1975.  
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