counter60.sv

module counter60(
    input logic  c,
    input logic  en,
    output logic trig,
    output logic [5:0] count
    );

logic [5:0] counter = 6'd0;

always @(posedge c) begin
    if (en & trig)
        counter <= 6'd0;
    else if (en)
        counter <= counter + 1;
end
assign trig = (counter == 6'd59);
assign count = counter;

endmodule