import cmd_bits::*;

module dev_fsm
#(
    // parameter declaration
    parameter DW = 8    // data width
)
(
    // inputs
    input logic clk, rst, cs,
    input logic [DW - 1:0] din,

    // outputs
    output logic busy, drdy,
    output logic [DW - 1:0] dout
);

    // state register and next state value
    enum logic [4:0] {ST_IDLE, ST_RCV_1, ST_RCV_2, ST_PROC, ST_TX} state, next_state;

    // data and status registers
    logic [DW - 1:0] result;
    logic [DW - 1:0] op_1;
    logic [DW - 1:0] op_2;
    logic [DW - 1:0] cmd;

    // state register
    always_ff @ (posedge clk or negedge rst)
    begin
        if (~rst) state <= ST_IDLE;
        else state <= next_state;
    end

    //next state logic
    always_comb
    begin
        next_state = state;
        case (state)
        ST_IDLE:
            if (cs)
            begin
                if (din[b_op_1]) next_state = ST_RCV_1;
                else if (din[b_op_2]) next_state = ST_RCV_2;
                else if (din[b_tx]) next_state = ST_TX;
                else next_state = ST_PROC;
            end
        ST_RCV_1:
            if (cmd[b_op_2]) next_state = ST_RCV_2;
            else if (cmd[b_tx]) next_state = ST_TX;
            else next_state = ST_IDLE;
        ST_RCV_2:
            if (cmd[b_tx]) next_state = ST_TX;
            else next_state = ST_IDLE;
        ST_PROC:
            next_state = ST_IDLE;
        ST_TX:
            next_state = ST_IDLE;
        default:
            next_state = ST_IDLE;
        endcase
    end

    // data and status registers
    always_ff @ (posedge clk or negedge rst)
    begin
        if (~rst)
        begin
            drdy <= 0;
            busy <= 0;
            result <= 0;
            op_1 <= 0;
            op_2 <= 0;
            cmd <= 0;
        end
        else
        begin
            //since drdy is registered, set to 1 at the cloc edge when state changes to ST_TX
            drdy<=(next_state==ST_TX);
            //we set busy to 0 at reset and when we enter idle
            busy<=!(next_state==ST_IDLE);
            //latching data in registers
            case (state)
            ST_IDLE:
                //store command in register when we leave idle
                if (cs) cmd<=din;
            ST_RCV_1:
                //store operand 1
                op_1<=din;
            ST_RCV_2:
                //store operand 2
                op_2<=din;
            ST_PROC:
                //change result register according to opcode
                case (cmd[DW - 1:DW - 4])
                    4'b1000: result <= op_1 + op_2;
                    4'b0100: result <= op_1 - op_2;
                    4'b0010: result <= result + op_1;
                    4'b0001: result <= result - op_1;
                endcase
            endcase
        end
    end

    assign dout = (state==ST_TX)?result:'bx;

endmodule




`timescale 1 ps/ 1 ps

//command bit definitions
import cmd_bits::*;

module dev_fsm_tb();

    //parameters
    parameter DW = 8;

    // test vector input registers
    logic clk;
    logic cs;
    logic [DW-1:0] din;
    logic rst;
    // module output connections
    logic busy;
    logic [DW-1:0] dout;
    logic drdy;
    // testbench variables
    logic [DW-1:0] res;

    //device under test
    dev_fsm #(.DW(DW)) dut (
        .busy(busy),
        .clk(clk),
        .cs(cs),
        .din(din),
        .dout(dout),
        .drdy(drdy),
        .rst(rst)
    );

    // create clock
    initial
    begin
        clk=0;
        forever #10 clk=~clk;
    end

    // reset circuit and run several transactions
    initial
    begin
        // reset
        rst=0;
        @(negedge clk) rst=1;
        //skip one edge after reset
        @(posedge clk);
        // send two operands and add them to result
        write_transaction((1<<b_op_1)|(1<<b_op_2)|(1<<b_addop),$random,$random,res);
        // send one operand, add it to result and read the result back
        write_transaction((1<<b_addop),0,0,res);
        //wait couple clock cycles
        //$stop;
        repeat (2) @(posedge clk);
        write_transaction((1<<b_tx),0,0,res);
        //stop simulation
        @(posedge clk);
        $stop;
    end

    //basic transaction with module
    task write_transaction;
        //input signals
        input [DW-1:0] cmd;
        input [DW-1:0] op_1;
        input [DW-1:0] op_2;
        output [DW-1:0] result;
        //transaction implementation
        begin
            //wait while device is busy
            while (busy) @(posedge clk);
            //set chip select and write command to DUT
            cs=1;
            din=cmd;
            //clear chip select
            @(posedge clk);
            cs=0;
            //write op_1 if required and wait for one clock cycle
            if (cmd[b_op_1])
            begin
                din=op_1;
                @(posedge clk);
            end
            //write op_2 if required and wait for one clock cycle
            if (cmd[b_op_2])
            begin
                din=op_2;
                @(posedge clk);
            end
            //if read is supposed, wait for rdy to latch result
            if (cmd[b_tx])
            begin
                while (!drdy) @(posedge clk);
                result = dout;
            end
            else result = 'bx;
        end
    endtask

endmodule