module MAIN;
  reg J;
  reg K;
  reg CLK;
  wire Q, nQ;
  localparam per = 28;
  JKTrigger jktrigger(J,K,CLK,Q,nQ);
  initial
    begin
      $dumpfile("dump.vcd");
      $dumpvars(1);
      CLK = 1;
      J = 0;
      K = 1;
      #5;
      J = 1;
      K = 0;
      #5;
      J = 0;
      K = 0;
      #5;
      J = 1;
      K = 1;
      #5
      J = 1;
      K = 0;
      #5;
      J = 0;
      K = 0;
      #5;
      J = 1;
      K = 1;
      #5
      $finish;
    end
  always #per CLK = ~CLK;
endmodule;