CU

module CU(
    input CLK_IN_CU,
    input RST_IN_CU,

    input [7:0]DATA_IN_CU,              // Data input from the External Data Bus
    input [7:0]FLAGS_IN_CU,             // FLAGS input from the ALU
    output [18:0]CONTROL_OUT_CU         // Control Signal output
    );

    reg [7:0]INST;
    reg [26:0]CONTROL_CU;
    reg [3:0]STATE;
    reg FLAG_CHECKED;

    wire [3:0]INT_STATE_CU;
    wire [3:0]INT_CONTROL_CU;
    wire NEG_CLK_IN_CU;

    initial
    begin
        INST = 0;
        STATE = 'hF;
        CONTROL_CU = 0;
        FLAG_CHECKED = 0;
    end

    assign {CONTROL_OUT_CU[18:0], INT_CONTROL_CU[3:0], INT_STATE_CU[3:0]} = CONTROL_CU;
    assign NEG_CLK_IN_CU = ~CLK_IN_CU;                                      // what the fuck, why does this work

    always @(posedge CLK_IN_CU, posedge NEG_CLK_IN_CU, posedge RST_IN_CU)   // Instruction decoding/executing
    begin
        if (RST_IN_CU == 1)                                                 // Reset
        begin
            INST <= 0;
            STATE <= 'hF;
            CONTROL_CU <= 0;
            FLAG_CHECKED <= 0;
        end
        else
        begin
            if (CLK_IN_CU == 1)                                             // Check if the clock is at it's rising or falling edge
            begin                                                           // this begins on the rising edge
                if (INT_CONTROL_CU[3] == 1)
                    INST <= DATA_IN_CU;
                if (FLAG_CHECKED == 0)
                begin
                    case (INT_CONTROL_CU[2:0])
                        'h3 : FLAG_CHECKED = FLAGS_IN_CU[0];
                        'h4 : FLAG_CHECKED = FLAGS_IN_CU[1];
                        'h5 : FLAG_CHECKED = FLAGS_IN_CU[2];
                        'h6 : FLAG_CHECKED = FLAGS_IN_CU[3];
                        'h7 : FLAG_CHECKED = FLAGS_IN_CU[4];
                        default : ;
                    endcase
                end
            end
            else
            begin                                                           // this begins on the falling edge
                if (STATE == 'hF)
                    CONTROL_CU <= 'h0800280;
                else
                begin
                        case (INST)
                        'h00 :                                              // NOP
                            begin
                                case (STATE)
                                    'h0 : CONTROL_CU <= 'h005800F;
                                endcase
                            end
                    endcase
                end
                STATE <= INT_STATE_CU;
            end
        end
    end
endmodule