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Coreboot Log 07-09-2016 Alix 2D13

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  1. coreboot-4.4-1435-g614ffc6-20160709 Wed Sep  7 17:06:42 UTC 2016 romstage starting...
  2. MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e
  3. Configuring PLL.
  4.  
  5.  
  6. coreboot-4.4-1435-g614ffc6-20160709 Wed Sep  7 17:06:42 UTC 2016 romstage starting...
  7. MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e
  8. PLL configured.
  9. Castle 2.0 BTM periodic sync period.
  10. Enable Quack for fewer re-RAS on the MC
  11.  GLIU port active enable
  12. Set the Delay Control in GLCP
  13. spd_read_byte dev 50 addr 0d returns 08
  14. spd_read_byte dev 50 addr 05 returns 01
  15. spd_read_byte dev 51 returns 0xff
  16. Enable RSDC
  17. FPU imprecise exceptions bit
  18. Enable Suspend on HLT & PAUSE instructions
  19. Enable SUSP and allow TSC to run in Suspend
  20. Setup throttling delays to proper mode
  21. Done cpuRegInit
  22. Ram1.00
  23. Ram2.00
  24.  * sdram_set_spd_register
  25. spd_read_byte dev 50 addr 15 returns ff
  26.  * Check DIMM 0
  27.  * Check DIMM 1
  28. spd_read_byte dev 51 returns 0xff
  29.  * Check DDR MAX
  30. spd_read_byte dev 50 addr 09 returns 0a
  31. spd_read_byte dev 51 returns 0xff
  32.  * AUTOSIZE DIMM 0
  33.  * Check present
  34. spd_read_byte dev 50 addr 02 returns 07
  35.  * MODBANKS
  36. spd_read_byte dev 50 addr 05 returns 01
  37.  * FIELDBANKS
  38. spd_read_byte dev 50 addr 11 returns 04
  39.  * SPDNUMROWS
  40. spd_read_byte dev 50 addr 03 returns 03
  41. spd_read_byte dev 50 addr 04 returns 0a
  42.  * SPDBANKDENSITY
  43. spd_read_byte dev 50 addr 1f returns 40
  44.  * DIMMSIZE
  45.  * BEFORT CTZ
  46.  * TEST DIMM SIZE>8
  47.  * PAGESIZE
  48. spd_read_byte dev 50 addr 04 returns 0a
  49.  * MAXCOLADDR
  50.  * >12address test
  51.  * RDMSR CF07
  52.  * WRMSR CF07
  53.  * ALL DONE
  54.  * AUTOSIZE DIMM 1
  55.  * Check present
  56. spd_read_byte dev 51 returns 0xff
  57.  * set cas latency
  58. spd_read_byte dev 50 addr 12 returns 10
  59. spd_read_byte dev 50 addr 17 returns 3c
  60. spd_read_byte dev 50 addr 19 returns 4b
  61. spd_read_byte dev 51 returns 0xff
  62.  * set all latency
  63. spd_read_byte dev 50 addr 1e returns 28
  64. spd_read_byte dev 51 returns 0xff
  65. spd_read_byte dev 50 addr 1b returns 0f
  66. spd_read_byte dev 51 returns 0xff
  67. spd_read_byte dev 50 addr 1d returns 0f
  68. spd_read_byte dev 51 returns 0xff
  69. spd_read_byte dev 50 addr 1c returns 0a
  70. spd_read_byte dev 51 returns 0xff
  71. spd_read_byte dev 50 addr 2a returns 46
  72. spd_read_byte dev 51 returns 0xff
  73.  * set emrs
  74. spd_read_byte dev 50 addr 16 returns ff
  75. spd_read_byte dev 51 returns 0xff
  76.  * set ref rate
  77. spd_read_byte dev 50 addr 0c returns 3a
  78. spd_read_byte dev 51 returns 0xff
  79. Ram3
  80.  * DRAM controller init done.
  81.  
  82. RAM DLL lock
  83. Ram4
  84. POST 02
  85. Past wbinvd
  86. CBFS: 'Master Header Locator' located CBFS at [100:7ffc0)
  87. CBFS: Locating 'fallback/ramstage'
  88. CBFS: Found @ offset 4640 size 904f
  89.  
  90.  
  91. coreboot-4.4-1435-g614ffc6-20160709 Wed Sep  7 17:06:42 UTC 2016 ramstage starting...
  92. BS: BS_PRE_DEVICE times (us): entry 0 run 3 exit 0
  93. BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0
  94. Enumerating buses...
  95. Show all devs... Before device enumeration.
  96. Root Device: enabled 1
  97. DOMAIN: 0000: enabled 1
  98. PCI: 00:01.0: enabled 1
  99. PCI: 00:01.1: enabled 1
  100. PCI: 00:0f.0: enabled 1
  101. PCI: 00:0f.1: enabled 1
  102. PCI: 00:0f.2: enabled 1
  103. PCI: 00:0f.4: enabled 1
  104. PCI: 00:0f.5: enabled 1
  105. CPU_CLUSTER: 0: enabled 1
  106. APIC: 00: enabled 1
  107. Compare with tree...
  108. Root Device: enabled 1
  109.  DOMAIN: 0000: enabled 1
  110.   PCI: 00:01.0: enabled 1
  111.   PCI: 00:01.1: enabled 1
  112.   PCI: 00:0f.0: enabled 1
  113.   PCI: 00:0f.1: enabled 1
  114.   PCI: 00:0f.2: enabled 1
  115.   PCI: 00:0f.4: enabled 1
  116.   PCI: 00:0f.5: enabled 1
  117.  CPU_CLUSTER: 0: enabled 1
  118.   APIC: 00: enabled 1
  119. Root Device scanning...
  120. root_dev_scan_bus for Root Device
  121. >> Entering northbridge.c: enable_dev with path 6
  122. >> Entering northbridge.c: pci_domain_enable
  123. Enter northbridge_init_early
  124. writeglmsr: MSR 0x10000020, val 0x20000000:0x000fff80
  125. writeglmsr: MSR 0x10000021, val 0x20000000:0x080fffe0
  126. sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
  127. sizeram: sizem 0x100MB
  128. SysmemInit: enable for 256MBytes
  129. usable RAM: 268304383 bytes
  130. SysmemInit: MSR 0x10000028, val 0x2000000f:0xfdf00100
  131. sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
  132. sizeram: sizem 0x100MB
  133. SMMGL0Init: 268304384 bytes
  134. SMMGL0Init: offset is 0x80400000
  135. SMMGL0Init: MSR 0x10000026, val 0x28fbe080:0x400fffe0
  136. writeglmsr: MSR 0x10000080, val 0x00000000:0x00000003
  137. writeglmsr: MSR 0x40000020, val 0x20000000:0x000fff80
  138. writeglmsr: MSR 0x40000021, val 0x20000000:0x080fffe0
  139. sizeram: _MSR MC_CF07_DATA: 10076013:00061a40
  140. sizeram: sizem 0x100MB
  141. SysmemInit: enable for 256MBytes
  142. usable RAM: 268304383 bytes
  143. SysmemInit: MSR 0x4000002a, val 0x2000000f:0xfdf00100
  144. SMMGL1Init:
  145. SMMGL1Init: MSR 0x40000023, val 0x20000080:0x400fffe0
  146. writeglmsr: MSR 0x40000080, val 0x00000000:0x00000001
  147. writeglmsr: MSR 0x400000e3, val 0x60000000:0x033000f0
  148. CPU_RCONF_DEFAULT (1808): 0x25FFFC02:0x10FFDF00
  149. CPU_RCONF_BYPASS (180A): 0x00000000 : 0x00000000
  150. L2 cache enabled
  151. Enabling cache
  152. GLPCI R1: system msr.lo 0x00100130 msr.hi 0x0ffdf000
  153. GLPCI R2: system msr.lo 0x80400120 msr.hi 0x8041f000
  154. Exit northbridge_init_early
  155. Done cpubug fixes
  156. Not Doing ChipsetFlashSetup()
  157. Preparing for VSA...
  158. Real mode stub @00000600: 867 bytes
  159. CBFS: 'Master Header Locator' located CBFS at [100:7ffc0)
  160. CBFS: Locating 'vsa'
  161. CBFS: Found @ offset 2d040 size e0bc
  162. VSA: Buffer @00060000 *[0k]=ba
  163. VSA: Signature *[0x20-0x23] is b0:10:e6:80
  164. Calling VSA module...
  165. ... VSA module returned.
  166. VSM: VSA2 VR signature verified.
  167. Graphics init...
  168. VRC_VG value: 0x2808
  169. DOMAIN: 0000 enabled
  170. >> Entering northbridge.c: enable_dev with path 7
  171. CPU_CLUSTER: 0 enabled
  172. DOMAIN: 0000 scanning...
  173. PCI: pci_scan_bus for bus 00
  174. >> Entering northbridge.c: enable_dev with path 2
  175. PCI: 00:01.0 [1022/2080] ops
  176. PCI: 00:01.0 [1022/2080] enabled
  177. >> Entering northbridge.c: enable_dev with path 2
  178. PCI: 00:01.1 [1022/2081] enabled
  179. PCI: 00:01.2 [1022/2082] enabled
  180. PCI: 00:09.0 [1106/3053] enabled
  181. PCI: 00:0b.0 [1106/3053] enabled
  182. cs5536: southbridge_enable: dev is 001113c0
  183. PCI: 00:0f.0 [1022/2090] bus ops
  184. PCI: 00:0f.0 [1022/2090] enabled
  185. cs5536: southbridge_enable: dev is 00111320
  186. PCI: Static device PCI: 00:0f.1 not found, disabling it.
  187. cs5536: southbridge_enable: dev is 00111280
  188. PCI: 00:0f.2 [1022/209a] ops
  189. PCI: 00:0f.2 [1022/209a] enabled
  190. PCI: 00:0f.3 [1022/2093] enabled
  191. cs5536: southbridge_enable: dev is 001111e0
  192. PCI: 00:0f.4 [1022/2094] enabled
  193. cs5536: southbridge_enable: dev is 00111140
  194. PCI: 00:0f.5 [1022/2095] enabled
  195. PCI: 00:0f.6 [1022/2096] enabled
  196. PCI: 00:0f.7 [1022/2097] enabled
  197. PCI: 00:0f.0 scanning...
  198. scan_smbus for PCI: 00:0f.0
  199. scan_smbus for PCI: 00:0f.0 done
  200. scan_bus: scanning of bus PCI: 00:0f.0 took 23176 usecs
  201. scan_bus: scanning of bus DOMAIN: 0000 took 284347 usecs
  202. root_dev_scan_bus for Root Device done
  203. scan_bus: scanning of bus Root Device took 887159 usecs
  204. done
  205. BS: BS_DEV_ENUMERATE times (us): entry 0 run 1073220 exit 0
  206. found VGA at PCI: 00:01.1
  207. Setting up VGA for PCI: 00:01.1
  208. Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
  209. Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
  210. Allocating resources...
  211. Reading resources...
  212. Root Device read_resources bus 0 link: 0
  213. DOMAIN: 0000 read_resources bus 0 link: 0
  214. DOMAIN: 0000 read_resources bus 0 link: 0 done
  215. CPU_CLUSTER: 0 read_resources bus 0 link: 0
  216. CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
  217. Root Device read_resources bus 0 link: 0 done
  218. Done reading resources.
  219. Show resources in subtree (Root Device)...After reading.
  220.  Root Device child on link 0 DOMAIN: 0000
  221.   DOMAIN: 0000 child on link 0 PCI: 00:01.0
  222.   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  223.   DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
  224.    PCI: 00:01.0
  225.    PCI: 00:01.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 10
  226.    PCI: 00:01.1
  227.    PCI: 00:01.1 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
  228.    PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14
  229.    PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18
  230.    PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 1c
  231.    PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 20
  232.    PCI: 00:01.2
  233.    PCI: 00:01.2 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
  234.    PCI: 00:09.0
  235.    PCI: 00:09.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
  236.    PCI: 00:09.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
  237.    PCI: 00:0b.0
  238.    PCI: 00:0b.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
  239.    PCI: 00:0b.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
  240.    PCI: 00:0f.0
  241.    PCI: 00:0f.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
  242.    PCI: 00:0f.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
  243.    PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 18
  244.    PCI: 00:0f.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 1c
  245.    PCI: 00:0f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 20
  246.    PCI: 00:0f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24
  247.    PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
  248.    PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
  249.    PCI: 00:0f.1
  250.    PCI: 00:0f.2
  251.    PCI: 00:0f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
  252.    PCI: 00:0f.3
  253.    PCI: 00:0f.3 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10
  254.    PCI: 00:0f.4
  255.    PCI: 00:0f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
  256.    PCI: 00:0f.5
  257.    PCI: 00:0f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
  258.    PCI: 00:0f.6
  259.    PCI: 00:0f.6 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
  260.    PCI: 00:0f.7
  261.    PCI: 00:0f.7 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
  262.   CPU_CLUSTER: 0 child on link 0 APIC: 00
  263.    APIC: 00
  264. DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
  265. PCI: 00:09.0 10 *  [0x0 - 0xff] io
  266. PCI: 00:0b.0 10 *  [0x400 - 0x4ff] io
  267. PCI: 00:0f.0 14 *  [0x800 - 0x8ff] io
  268. PCI: 00:0f.0 20 *  [0xc00 - 0xc7f] io
  269. PCI: 00:0f.3 10 *  [0xc80 - 0xcff] io
  270. PCI: 00:0f.0 18 *  [0x1000 - 0x103f] io
  271. PCI: 00:0f.0 24 *  [0x1040 - 0x107f] io
  272. PCI: 00:0f.0 1c *  [0x1080 - 0x109f] io
  273. PCI: 00:0f.2 20 *  [0x10a0 - 0x10af] io
  274. PCI: 00:0f.0 10 *  [0x10b0 - 0x10b7] io
  275. PCI: 00:01.0 10 *  [0x10b8 - 0x10bb] io
  276. DOMAIN: 0000 io: base: 10bc size: 10bc align: 8 gran: 0 limit: ffff done
  277. DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
  278. PCI: 00:01.1 10 *  [0x0 - 0xffffff] mem
  279. PCI: 00:01.1 14 *  [0x1000000 - 0x1003fff] mem
  280. PCI: 00:01.1 18 *  [0x1004000 - 0x1007fff] mem
  281. PCI: 00:01.1 1c *  [0x1008000 - 0x100bfff] mem
  282. PCI: 00:01.1 20 *  [0x100c000 - 0x100ffff] mem
  283. PCI: 00:01.2 10 *  [0x1010000 - 0x1013fff] mem
  284. PCI: 00:0f.6 10 *  [0x1014000 - 0x1015fff] mem
  285. PCI: 00:0f.4 10 *  [0x1016000 - 0x1016fff] mem
  286. PCI: 00:0f.5 10 *  [0x1017000 - 0x1017fff] mem
  287. PCI: 00:0f.7 10 *  [0x1018000 - 0x1018fff] mem
  288. PCI: 00:09.0 14 *  [0x1019000 - 0x10190ff] mem
  289. PCI: 00:0b.0 14 *  [0x101a000 - 0x101a0ff] mem
  290. DOMAIN: 0000 mem: base: 101a100 size: 101a100 align: 24 gran: 0 limit: ffffffff done
  291. avoid_fixed_resources: DOMAIN: 0000
  292. avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
  293. avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
  294. constrain_resources: PCI: 00:0f.0 01 base 00000000 limit 00000fff io (fixed)
  295. constrain_resources: PCI: 00:0f.0 03 base fec00000 limit fec00fff mem (fixed)
  296. avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
  297. avoid_fixed_resources:@DOMAIN: 0000 10000100 base fd000000 limit febfffff
  298. Setting resources...
  299. DOMAIN: 0000 io: base:1000 size:10bc align:8 gran:0 limit:ffff
  300. PCI: 00:09.0 10 *  [0x1000 - 0x10ff] io
  301. PCI: 00:0b.0 10 *  [0x1400 - 0x14ff] io
  302. PCI: 00:0f.0 14 *  [0x1800 - 0x18ff] io
  303. PCI: 00:0f.0 20 *  [0x1c00 - 0x1c7f] io
  304. PCI: 00:0f.3 10 *  [0x1c80 - 0x1cff] io
  305. PCI: 00:0f.0 18 *  [0x2000 - 0x203f] io
  306. PCI: 00:0f.0 24 *  [0x2040 - 0x207f] io
  307. PCI: 00:0f.0 1c *  [0x2080 - 0x209f] io
  308. PCI: 00:0f.2 20 *  [0x20a0 - 0x20af] io
  309. PCI: 00:0f.0 10 *  [0x20b0 - 0x20b7] io
  310. PCI: 00:01.0 10 *  [0x20b8 - 0x20bb] io
  311. DOMAIN: 0000 io: next_base: 20bc size: 10bc align: 8 gran: 0 done
  312. DOMAIN: 0000 mem: base:fd000000 size:101a100 align:24 gran:0 limit:febfffff
  313. PCI: 00:01.1 10 *  [0xfd000000 - 0xfdffffff] mem
  314. PCI: 00:01.1 14 *  [0xfe000000 - 0xfe003fff] mem
  315. PCI: 00:01.1 18 *  [0xfe004000 - 0xfe007fff] mem
  316. PCI: 00:01.1 1c *  [0xfe008000 - 0xfe00bfff] mem
  317. PCI: 00:01.1 20 *  [0xfe00c000 - 0xfe00ffff] mem
  318. PCI: 00:01.2 10 *  [0xfe010000 - 0xfe013fff] mem
  319. PCI: 00:0f.6 10 *  [0xfe014000 - 0xfe015fff] mem
  320. PCI: 00:0f.4 10 *  [0xfe016000 - 0xfe016fff] mem
  321. PCI: 00:0f.5 10 *  [0xfe017000 - 0xfe017fff] mem
  322. PCI: 00:0f.7 10 *  [0xfe018000 - 0xfe018fff] mem
  323. PCI: 00:09.0 14 *  [0xfe019000 - 0xfe0190ff] mem
  324. PCI: 00:0b.0 14 *  [0xfe01a000 - 0xfe01a0ff] mem
  325. DOMAIN: 0000 mem: next_base: fe01a100 size: 101a100 align: 24 gran: 0 done
  326. Root Device assign_resources, bus 0 link: 0
  327. >> Entering northbridge.c: pci_domain_set_resources
  328. DOMAIN: 0000 assign_resources, bus 0 link: 0
  329. PCI: 00:01.1 10 <- [0x00fd000000 - 0x00fdffffff] size 0x01000000 gran 0x18 mem
  330. PCI: 00:01.1 14 <- [0x00fe000000 - 0x00fe003fff] size 0x00004000 gran 0x0e mem
  331. PCI: 00:01.1 18 <- [0x00fe004000 - 0x00fe007fff] size 0x00004000 gran 0x0e mem
  332. PCI: 00:01.1 1c <- [0x00fe008000 - 0x00fe00bfff] size 0x00004000 gran 0x0e mem
  333. PCI: 00:01.1 20 <- [0x00fe00c000 - 0x00fe00ffff] size 0x00004000 gran 0x0e mem
  334. PCI: 00:01.2 10 <- [0x00fe010000 - 0x00fe013fff] size 0x00004000 gran 0x0e mem
  335. PCI: 00:09.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
  336. PCI: 00:09.0 14 <- [0x00fe019000 - 0x00fe0190ff] size 0x00000100 gran 0x08 mem
  337. PCI: 00:0b.0 10 <- [0x0000001400 - 0x00000014ff] size 0x00000100 gran 0x08 io
  338. PCI: 00:0b.0 14 <- [0x00fe01a000 - 0x00fe01a0ff] size 0x00000100 gran 0x08 mem
  339. PCI: 00:0f.0 10 <- [0x00000020b0 - 0x00000020b7] size 0x00000008 gran 0x03 io
  340. PCI: 00:0f.0 14 <- [0x0000001800 - 0x00000018ff] size 0x00000100 gran 0x08 io
  341. PCI: 00:0f.0 18 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io
  342. PCI: 00:0f.0 1c <- [0x0000002080 - 0x000000209f] size 0x00000020 gran 0x05 io
  343. PCI: 00:0f.0 20 <- [0x0000001c00 - 0x0000001c7f] size 0x00000080 gran 0x07 io
  344. PCI: 00:0f.0 24 <- [0x0000002040 - 0x000000207f] size 0x00000040 gran 0x06 io
  345. PCI: 00:0f.2 20 <- [0x00000020a0 - 0x00000020af] size 0x00000010 gran 0x04 io
  346. PCI: 00:0f.3 10 <- [0x0000001c80 - 0x0000001cff] size 0x00000080 gran 0x07 io
  347. PCI: 00:0f.4 10 <- [0x00fe016000 - 0x00fe016fff] size 0x00001000 gran 0x0c mem
  348. PCI: 00:0f.5 10 <- [0x00fe017000 - 0x00fe017fff] size 0x00001000 gran 0x0c mem
  349. PCI: 00:0f.6 10 <- [0x00fe014000 - 0x00fe015fff] size 0x00002000 gran 0x0d mem
  350. PCI: 00:0f.7 10 <- [0x00fe018000 - 0x00fe018fff] size 0x00001000 gran 0x0c mem
  351. DOMAIN: 0000 assign_resources, bus 0 link: 0
  352. Root Device assign_resources, bus 0 link: 0
  353. Done setting resources.
  354. Show resources in subtree (Root Device)...After assigning values.
  355.  Root Device child on link 0 DOMAIN: 0000
  356.   DOMAIN: 0000 child on link 0 PCI: 00:01.0
  357.   DOMAIN: 0000 resource base 1000 size 10bc align 8 gran 0 limit ffff flags 40040100 index 10000000
  358.   DOMAIN: 0000 resource base fd000000 size 101a100 align 24 gran 0 limit febfffff flags 40040200 index 10000100
  359.   DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a
  360.   DOMAIN: 0000 resource base c0000 size f720000 align 0 gran 0 limit 0 flags e0004200 index b
  361.    PCI: 00:01.0
  362.    PCI: 00:01.0 resource base 20b8 size 4 align 2 gran 2 limit 20bb flags 40000100 index 10
  363.    PCI: 00:01.1
  364.    PCI: 00:01.1 resource base fd000000 size 1000000 align 24 gran 24 limit fdffffff flags 60000200 index 10
  365.    PCI: 00:01.1 resource base fe000000 size 4000 align 14 gran 14 limit fe003fff flags 60000200 index 14
  366.    PCI: 00:01.1 resource base fe004000 size 4000 align 14 gran 14 limit fe007fff flags 60000200 index 18
  367.    PCI: 00:01.1 resource base fe008000 size 4000 align 14 gran 14 limit fe00bfff flags 60000200 index 1c
  368.    PCI: 00:01.1 resource base fe00c000 size 4000 align 14 gran 14 limit fe00ffff flags 60000200 index 20
  369.    PCI: 00:01.2
  370.    PCI: 00:01.2 resource base fe010000 size 4000 align 14 gran 14 limit fe013fff flags 60000200 index 10
  371.    PCI: 00:09.0
  372.    PCI: 00:09.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
  373.    PCI: 00:09.0 resource base fe019000 size 100 align 12 gran 8 limit fe0190ff flags 60000200 index 14
  374.    PCI: 00:0b.0
  375.    PCI: 00:0b.0 resource base 1400 size 100 align 8 gran 8 limit 14ff flags 60000100 index 10
  376.    PCI: 00:0b.0 resource base fe01a000 size 100 align 12 gran 8 limit fe01a0ff flags 60000200 index 14
  377.    PCI: 00:0f.0
  378.    PCI: 00:0f.0 resource base 20b0 size 8 align 3 gran 3 limit 20b7 flags 60000100 index 10
  379.    PCI: 00:0f.0 resource base 1800 size 100 align 8 gran 8 limit 18ff flags 60000100 index 14
  380.    PCI: 00:0f.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 18
  381.    PCI: 00:0f.0 resource base 2080 size 20 align 5 gran 5 limit 209f flags 60000100 index 1c
  382.    PCI: 00:0f.0 resource base 1c00 size 80 align 7 gran 7 limit 1c7f flags 60000100 index 20
  383.    PCI: 00:0f.0 resource base 2040 size 40 align 6 gran 6 limit 207f flags 60000100 index 24
  384.    PCI: 00:0f.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1
  385.    PCI: 00:0f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
  386.    PCI: 00:0f.1
  387.    PCI: 00:0f.2
  388.    PCI: 00:0f.2 resource base 20a0 size 10 align 4 gran 4 limit 20af flags 60000100 index 20
  389.    PCI: 00:0f.3
  390.    PCI: 00:0f.3 resource base 1c80 size 80 align 7 gran 7 limit 1cff flags 60000100 index 10
  391.    PCI: 00:0f.4
  392.    PCI: 00:0f.4 resource base fe016000 size 1000 align 12 gran 12 limit fe016fff flags 60000200 index 10
  393.    PCI: 00:0f.5
  394.    PCI: 00:0f.5 resource base fe017000 size 1000 align 12 gran 12 limit fe017fff flags 60000200 index 10
  395.    PCI: 00:0f.6
  396.    PCI: 00:0f.6 resource base fe014000 size 2000 align 13 gran 13 limit fe015fff flags 60000200 index 10
  397.    PCI: 00:0f.7
  398.    PCI: 00:0f.7 resource base fe018000 size 1000 align 12 gran 12 limit fe018fff flags 60000200 index 10
  399.   CPU_CLUSTER: 0 child on link 0 APIC: 00
  400.    APIC: 00
  401. Done allocating resources.
  402. BS: BS_DEV_RESOURCES times (us): entry 0 run 3100423 exit 0
  403. Enabling resources...
  404. PCI: 00:01.0 cmd <- 05
  405. PCI: 00:01.1 subsystem <- 0000/0000
  406. PCI: 00:01.1 cmd <- 03
  407. PCI: 00:01.2 cmd <- 02
  408. PCI: 00:09.0 cmd <- 83
  409. PCI: 00:0b.0 cmd <- 83
  410. PCI: 00:0f.0 cmd <- 09
  411. PCI: 00:0f.2 cmd <- 01
  412. PCI: 00:0f.3 cmd <- 01
  413. PCI: 00:0f.4 subsystem <- 0000/0000
  414. PCI: 00:0f.4 cmd <- 02
  415. PCI: 00:0f.5 subsystem <- 0000/0000
  416. PCI: 00:0f.5 cmd <- 02
  417. PCI: 00:0f.6 cmd <- 02
  418. PCI: 00:0f.7 cmd <- 02
  419. done.
  420. BS: BS_DEV_ENABLE times (us): entry 0 run 112400 exit 0
  421. Initializing devices...
  422. Root Device init ...
  423. Root Device init finished in 5754 usecs
  424. CPU_CLUSTER: 0 init ...
  425. >> Entering northbridge.c: cpu_bus_init
  426. Initializing CPU #0
  427. CPU: vendor AMD device 5a2
  428. CPU: family 05, model 0a, stepping 02
  429. geode_lx_init
  430. Enabling cache
  431. A20 (0x92): 2
  432. A20 (0x92): 2
  433. CPU geode_lx_init DONE
  434. CPU #0 initialized
  435. CPU_CLUSTER: 0 init finished in 67613 usecs
  436. PCI: 00:01.0 init ...
  437. >> Entering northbridge.c: northbridge_init
  438. PCI: 00:01.0 init finished in 17719 usecs
  439. PCI: 00:01.1 init ...
  440. PCI: 00:01.1 init finished in 6017 usecs
  441. PCI: 00:01.2 init ...
  442. PCI: 00:01.2 init finished in 6017 usecs
  443. PCI: 00:09.0 init ...
  444. PCI: 00:09.0 init finished in 6017 usecs
  445. PCI: 00:0b.0 init ...
  446. PCI: 00:0b.0 init finished in 6017 usecs
  447. PCI: 00:0f.0 init ...
  448. cs5536: southbridge_init
  449. RTC Init
  450. GPIO_ADDR: 00001800
  451. uarts_init: enable COM1
  452. uarts_init: enable COM2
  453. uarts_init: wrote COM2 address 0x2f8
  454. uarts_init: set COM2 irq
  455. uarts_init: set output enable
  456. uarts_init: set OUTAUX1
  457. uarts_init: set pullup COM2
  458. uarts_init: COM2 enabled
  459. cs5536: southbridge_init: enable_ide_nand_flash is 0
  460. Disabling VPCI device: 0x80000900
  461. Disabling VPCI device: 0x80007B00
  462. PCI: 00:0f.0 init finished in 112343 usecs
  463. PCI: 00:0f.2 init ...
  464. cs5536_ide: ide_init
  465. PCI: 00:0f.2 init finished in 11801 usecs
  466. PCI: 00:0f.3 init ...
  467. PCI: 00:0f.3 init finished in 6017 usecs
  468. PCI: 00:0f.4 init ...
  469. PCI: 00:0f.4 init finished in 6017 usecs
  470. PCI: 00:0f.5 init ...
  471. PCI: 00:0f.5 init finished in 6017 usecs
  472. PCI: 00:0f.6 init ...
  473. PCI: 00:0f.6 init finished in 6016 usecs
  474. PCI: 00:0f.7 init ...
  475. PCI: 00:0f.7 init finished in 6017 usecs
  476. Devices initialized
  477. Show all devs... After init.
  478. Root Device: enabled 1
  479. DOMAIN: 0000: enabled 1
  480. PCI: 00:01.0: enabled 1
  481. PCI: 00:01.1: enabled 1
  482. PCI: 00:0f.0: enabled 1
  483. PCI: 00:0f.1: enabled 0
  484. PCI: 00:0f.2: enabled 1
  485. PCI: 00:0f.4: enabled 1
  486. PCI: 00:0f.5: enabled 1
  487. CPU_CLUSTER: 0: enabled 1
  488. APIC: 00: enabled 1
  489. PCI: 00:01.2: enabled 1
  490. PCI: 00:09.0: enabled 1
  491. PCI: 00:0b.0: enabled 1
  492. PCI: 00:0f.3: enabled 1
  493. PCI: 00:0f.6: enabled 1
  494. PCI: 00:0f.7: enabled 1
  495. CPU: 00: enabled 1
  496. BS: BS_DEV_INIT times (us): entry 0 run 559157 exit 0
  497. CBMEM:
  498. IMD: root @ 0f7df000 254 entries.
  499. IMD: root @ 0f7dec00 62 entries.
  500. Moving GDT to 0f7dea00...ok
  501. Finalize devices...
  502. Devices finalized
  503. BS: BS_POST_DEVICE times (us): entry 27710 run 10430 exit 0
  504. BS: BS_OS_RESUME_CHECK times (us): entry 0 run 2 exit 0
  505. Copying Interrupt Routing Table to 0x000f0000... done.
  506. PIRQ Entry 0 Dev/Fn: 1 Slot: 0
  507. INT: A link: 1 bitmap: 800  IRQ: 11
  508. INT: B link: 0 bitmap: 0  not routed
  509. INT: C link: 0 bitmap: 0  not routed
  510. INT: D link: 0 bitmap: 0  not routed
  511. Assigning IRQ 11 to 0:1.2
  512. PIRQ Entry 1 Dev/Fn: 9 Slot: 0
  513. INT: A link: 2 bitmap: 400  IRQ: 10
  514. INT: B link: 0 bitmap: 0  not routed
  515. INT: C link: 0 bitmap: 0  not routed
  516. INT: D link: 0 bitmap: 0  not routed
  517. Assigning IRQ 10 to 0:9.0
  518. PIRQ Entry 2 Dev/Fn: A Slot: 0
  519. INT: A link: 3 bitmap: 800  IRQ: 11
  520. INT: B link: 0 bitmap: 0  not routed
  521. INT: C link: 0 bitmap: 0  not routed
  522. INT: D link: 0 bitmap: 0  not routed
  523. PIRQ Entry 3 Dev/Fn: B Slot: 0
  524. INT: A link: 4 bitmap: 200  IRQ: 9
  525. INT: B link: 0 bitmap: 0  not routed
  526. INT: C link: 0 bitmap: 0  not routed
  527. INT: D link: 0 bitmap: 0  not routed
  528. Assigning IRQ 9 to 0:b.0
  529. PIRQ Entry 4 Dev/Fn: C Slot: 0
  530. INT: A link: 1 bitmap: 800  IRQ: 11
  531. INT: B link: 2 bitmap: 400  IRQ: 10
  532. INT: C link: 0 bitmap: 0  not routed
  533. INT: D link: 0 bitmap: 0  not routed
  534. PIRQ Entry 5 Dev/Fn: E Slot: 0
  535. INT: A link: 3 bitmap: 800  IRQ: 11
  536. INT: B link: 4 bitmap: 200  IRQ: 9
  537. INT: C link: 0 bitmap: 0  not routed
  538. INT: D link: 0 bitmap: 0  not routed
  539. PIRQ Entry 6 Dev/Fn: F Slot: 0
  540. INT: A link: 1 bitmap: 800  IRQ: 11
  541. INT: B link: 2 bitmap: 400  IRQ: 10
  542. INT: C link: 3 bitmap: 800  IRQ: 11
  543. INT: D link: 4 bitmap: 200  IRQ: 9
  544. Assigning IRQ 9 to 0:f.4
  545. Assigning IRQ 9 to 0:f.5
  546. PIRQA: 11
  547. PIRQB: 10
  548. PIRQC: 11
  549. PIRQD: 9
  550. Copying Interrupt Routing Table to 0x0f7b5000... done.
  551. PIRQ Entry 0 Dev/Fn: 1 Slot: 0
  552. INT: A link: 1 bitmap: 800  IRQ: 11
  553. INT: B link: 0 bitmap: 0  not routed
  554. INT: C link: 0 bitmap: 0  not routed
  555. INT: D link: 0 bitmap: 0  not routed
  556. Assigning IRQ 11 to 0:1.2
  557. PIRQ Entry 1 Dev/Fn: 9 Slot: 0
  558. INT: A link: 2 bitmap: 400  IRQ: 10
  559. INT: B link: 0 bitmap: 0  not routed
  560. INT: C link: 0 bitmap: 0  not routed
  561. INT: D link: 0 bitmap: 0  not routed
  562. Assigning IRQ 10 to 0:9.0
  563. PIRQ Entry 2 Dev/Fn: A Slot: 0
  564. INT: A link: 3 bitmap: 800  IRQ: 11
  565. INT: B link: 0 bitmap: 0  not routed
  566. INT: C link: 0 bitmap: 0  not routed
  567. INT: D link: 0 bitmap: 0  not routed
  568. PIRQ Entry 3 Dev/Fn: B Slot: 0
  569. INT: A link: 4 bitmap: 200  IRQ: 9
  570. INT: B link: 0 bitmap: 0  not routed
  571. INT: C link: 0 bitmap: 0  not routed
  572. INT: D link: 0 bitmap: 0  not routed
  573. Assigning IRQ 9 to 0:b.0
  574. PIRQ Entry 4 Dev/Fn: C Slot: 0
  575. INT: A link: 1 bitmap: 800  IRQ: 11
  576. INT: B link: 2 bitmap: 400  IRQ: 10
  577. INT: C link: 0 bitmap: 0  not routed
  578. INT: D link: 0 bitmap: 0  not routed
  579. PIRQ Entry 5 Dev/Fn: E Slot: 0
  580. INT: A link: 3 bitmap: 800  IRQ: 11
  581. INT: B link: 4 bitmap: 200  IRQ: 9
  582. INT: C link: 0 bitmap: 0  not routed
  583. INT: D link: 0 bitmap: 0  not routed
  584. PIRQ Entry 6 Dev/Fn: F Slot: 0
  585. INT: A link: 1 bitmap: 800  IRQ: 11
  586. INT: B link: 2 bitmap: 400  IRQ: 10
  587. INT: C link: 3 bitmap: 800  IRQ: 11
  588. INT: D link: 4 bitmap: 200  IRQ: 9
  589. Assigning IRQ 9 to 0:f.4
  590. Assigning IRQ 9 to 0:f.5
  591. PIRQA: 11
  592. PIRQB: 10
  593. PIRQC: 11
  594. PIRQD: 9
  595. PIRQ table: 144 bytes.
  596. smbios_write_tables: 0f7b4000
  597. Root Device (PC Engines ALIX.2D)
  598. DOMAIN: 0000 (AMD LX Northbridge)
  599. PCI: 00:01.0 (AMD LX Northbridge)
  600. PCI: 00:01.1 (AMD LX Northbridge)
  601. PCI: 00:0f.0 (AMD Geode CS5536 Southbridge)
  602. PCI: 00:0f.1 (AMD Geode CS5536 Southbridge)
  603. PCI: 00:0f.2 (AMD Geode CS5536 Southbridge)
  604. PCI: 00:0f.4 (AMD Geode CS5536 Southbridge)
  605. PCI: 00:0f.5 (AMD Geode CS5536 Southbridge)
  606. CPU_CLUSTER: 0 (AMD LX Northbridge)
  607. APIC: 00 (unknown)
  608. PCI: 00:01.2 (unknown)
  609. PCI: 00:09.0 (unknown)
  610. PCI: 00:0b.0 (unknown)
  611. PCI: 00:0f.3 (unknown)
  612. PCI: 00:0f.6 (unknown)
  613. PCI: 00:0f.7 (unknown)
  614. CPU: 00 (unknown)
  615. SMBIOS tables: 339 bytes.
  616. Writing table forward entry at 0x00000500
  617. Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9063
  618. Writing coreboot table at 0x0f7b6000
  619.  0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
  620.  1. 0000000000001000-000000000009ffff: RAM
  621.  2. 00000000000c0000-000000000f7b3fff: RAM
  622.  3. 000000000f7b4000-000000000f7dffff: CONFIGURATION TABLES
  623. CBFS: 'Master Header Locator' located CBFS at [100:7ffc0)
  624. FMAP: Found "FLASH" version 1.1 at 0.
  625. FMAP: base = fff80000 size = 80000 #areas = 3
  626. Wrote coreboot table at: 0f7b6000, 0x1cc bytes, checksum bb6
  627. coreboot table: 484 bytes.
  628. IMD ROOT    0. 0f7df000 00001000
  629. IMD SMALL   1. 0f7de000 00001000
  630. CONSOLE     2. 0f7be000 00020000
  631. COREBOOT    3. 0f7b6000 00008000
  632. IRQ TABLE   4. 0f7b5000 00001000
  633. SMBIOS      5. 0f7b4000 00000800
  634. IMD small region:
  635.   IMD ROOT    0. 0f7dec00 00000400
  636.   GDT         1. 0f7dea00 00000200
  637. BS: BS_WRITE_TABLES times (us): entry 0 run 1189465 exit 0
  638. CBFS: 'Master Header Locator' located CBFS at [100:7ffc0)
  639. CBFS: Locating 'fallback/payload'
  640. CBFS: Found @ offset dac0 size eee0
  641. Loading segment from ROM address 0xfff8dbf8
  642.   code (compression=1)
  643.   New segment dstaddr 0xe4060 memsize 0x1bfa0 srcaddr 0xfff8dc30 filesize 0xeea8
  644. Loading segment from ROM address 0xfff8dc14
  645.   Entry Point 0x000ff06e
  646. Bounce Buffer at 0f73d000, 485264 bytes
  647. Loading Segment: addr: 0x00000000000e4060 memsz: 0x000000000001bfa0 filesz: 0x000000000000eea8
  648. lb: [0x0000000000100000, 0x000000000013b3c8)
  649. Post relocation: addr: 0x00000000000e4060 memsz: 0x000000000001bfa0 filesz: 0x000000000000eea8
  650. using LZMA
  651. [ 0x000e4060, 00100000, 0x00100000) <- fff8dc30
  652. dest 000e4060, end 00100000, bouncebuffer f73d000
  653. Loaded segments
  654. BS: BS_PAYLOAD_LOAD times (us): entry 0 run 319272 exit 0
  655. Jumping to boot code at 000ff06e(0f7b6000)
  656. CPU0: stack: 00112000 - 00113000, lowest used address 00112c20, stack used: 992 bytes
  657. entry    = 0x000ff06e
  658. lb_start = 0x00100000
  659. lb_size  = 0x0003b3c8
  660. buffer   = 0x0f73d000
  661. SeaBIOS (version rel-1.9.1-0-gb3ef39f)
  662. BUILD: gcc: (coreboot toolchain v1.42 August 11th, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
  663. SeaBIOS (version rel-1.9.1-0-gb3ef39f)
  664. BUILD: gcc: (coreboot toolchain v1.42 August 11th, 2016) 5.3.0 binutils: (GNU Binutils) 2.26.1
  665. Found coreboot cbmem console @ f7be000
  666. Found mainboard PC Engines ALIX.2D
  667. Relocating init from 0x000e5480 to 0x0f768bc0 (size 45984)
  668. Found CBFS header at 0xfff80138
  669. multiboot: eax=0, ebx=0
  670. Found 8 PCI devices (max PCI bus is 00)
  671. Copying SMBIOS entry point from 0x0f7b4000 to 0x000f0800
  672. CPU Mhz=498
  673. Scan for VGA option rom
  674. EHCI init on dev 00:0f.5 (regs=0xfe017010)
  675. WARNING - Timeout at i8042_flush:71!
  676. OHCI init on dev 00:0f.4 (regs=0xfe016000)
  677. Found 0 lpt ports
  678. Found 2 serial ports
  679. ATA controller 1 at 1f0/3f4/0 (irq 14 dev 7a)
  680. ATA controller 2 at 170/374/0 (irq 15 dev 7a)
  681. ata0-0: SanDisk SDCFH-004G ATA-0 Hard-Disk (3815 MiBytes)
  682. Searching bootorder for: /pci@i0cf8/*@f,2/drive@0/disk@0
  683. All threads complete.
  684. Scan for option roms
  685. Running option rom at c000:0003
  686. pmm call arg1=1
  687. pmm call arg1=0
  688. pmm call arg1=1
  689. pmm call arg1=0
  690. Running option rom at c100:0003
  691. pmm call arg1=1
  692. pmm call arg1=1
  693. Searching bootorder for: /pci@i0cf8/*@9
  694. Searching bootorder for: /pci@i0cf8/*@b
  695.  
  696. Press ESC for boot menu.
RAW Paste Data
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