library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Lab8_del2_ag_vo is
	port(
		CLOCK_50 : in std_logic;
		KEY      : in std_logic_vector(3 downto 0);
		SW       : in std_logic_vector(17 downto 0);
		GPIO     : inout std_logic_vector(35 downto 0);
		LEDR     : out std_logic_vector(17 downto 0);
		LEDG     : out std_logic_vector(7 downto 0);
		LCD_RS, LCD_EN : out std_logic;
		LCD_RW : out std_logic;
		LCD_ON : out std_logic;
		LCD_DATA : inout std_logic_vector(7 downto 0);
		HEX0, HEX1, HEX2, HEX3, HEX4, HEX5 : out std_logic_vector(6 downto 0)
		);
end entity Lab8_del2_ag_vo;

architecture RTL of Lab8_del2_ag_vo is

	component enable_gen is
		port(
			clock_50    : in std_logic;
			resetn      : in std_logic;
			velg_enable : in std_logic_vector(2 downto 0);
			enable      : out std_logic
			);
	end component enable_gen;

	component reset_synchronizer is
		port(
			clk        : in std_logic;
			reset_key3 : in std_logic;
			reset_clk  : out std_logic
			);
	end component reset_synchronizer;

	component synkronisering is
		port(
			clk      : in std_logic;
			data_inn : in std_logic;
			data_ut  : out std_logic
			);
	end component synkronisering;

	component baudrate_gen is
		port(
			CLOCK_50       : in std_logic;
			resetn         : in std_logic;
			velg_baudrate : in std_logic_vector(2 downto 0);
			start_teller   : in std_logic;

			baud_enable_m  : out std_logic;
			baud_enable_s  : out std_logic
		);
	end component baudrate_gen;

	component LCD_Display is
		port(
		 reset, clk_48Mhz	   : IN STD_LOGIC;
		 Hex_Display_Data			: IN STD_LOGIC_VECTOR(23 DOWNTO 0);
		 LCD_RS, LCD_E				: OUT	STD_LOGIC;
		 LCD_RW						: OUT STD_LOGIC;
		 DATA_BUS					: INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));
	end component LCD_Display;

	component L4_klokke_AG is
		port(
			CLOCK_50                           : in std_logic;
			resetn                             : in std_logic;
			KEY                                : in std_logic_vector(3 downto 0);
			SW                                 : in std_logic_vector(2 downto 0);
			HEX0, HEX1, HEX2, HEX3, HEX4, HEX5 : out std_logic_vector(6 downto 0);
			bcd_hours                          : out std_logic_vector(7 downto 0);
			bcd_minutes                        : out std_logic_vector(7 downto 0);
			bcd_seconds                        : out std_logic_vector(7 downto 0)
			);
	end component L4_klokke_AG;

	signal resetn           : std_logic;
	signal hallo_enable     : std_logic;
	signal hallo            : std_logic;
	signal sender           : std_logic;
	signal mottatt_blink    : std_logic;
	signal vippe_a, vippe_b : std_logic;

	signal start_teller  : std_logic;
	signal baud_enable_m : std_logic;
	signal baud_enable_s : std_logic;

	signal data_inn : std_logic;
	signal data_ut  : std_logic;

	signal start_sender        : std_logic;
	signal start_q, start_qq   : std_logic;
	signal send_shift_register : std_logic_vector(9 downto 0);

	constant START_BIT : std_logic := '0';
	constant STOPP_BIT : std_logic := '1';

	-- sender
	type sender_state_type is (s_idle, s_transmit, s_shift_out, s_finish, s_wait);
	signal sender_state : sender_state_type;


	signal data_inn_q   : std_logic;
	signal data_inn_qq  : std_logic;
	signal data_inn_qqq : std_logic;

	signal error            : std_logic;
	signal mottak_shift_reg : std_logic_vector(10 downto 0);
	signal mottatt_data     : std_logic_vector(7 downto 0);

	-- del 3
		signal bcd_sec  : std_logic_vector(7 downto 0);
		signal bcd_min  : std_logic_vector(7 downto 0);
		signal bcd_hour : std_logic_vector(7 downto 0);
		signal LCD_bcd  : std_logic_vector(23 downto 0);

	-- ram til tid
		type ram_array_bcd is array (0 to 2) of std_logic_vector(7 downto 0);
		signal bcd_tid : ram_array_bcd;

		signal ord_teller   : integer range 0 to 2;
		signal ord_teller_m : integer range 0 to 2;


	-- mottaker
	type mottak_state_type is (s_idle_mottak, s_wait_for_sender, s_shift_in, s_offload, s_error);
	signal mottak_state : mottak_state_type;

	-- del 3
	-- ram til tid
		type mem_array_bcd is array (0 to 2) of std_logic_vector(7 downto 0);
		signal mem : mem_array_bcd;

begin

-- del 3
	bcd_tid(0) <= bcd_sec;
	bcd_tid(1) <= bcd_min;
	bcd_tid(2) <= bcd_hour;

	LCD_ON <= '1';

	LCD_Display_inst : component LCD_Display
		port map(
		 reset                => resetn,
		 clk_48Mhz	          => CLOCK_50,
		 Hex_Display_Data	    => LCD_bcd,
		 LCD_RS               => LCD_RS,
		 LCD_E		      	 => LCD_EN,
		 LCD_RW					 => LCD_RW,
		 DATA_BUS				 => LCD_Data
		 );

	enable_gen_inst : component enable_gen
		port map(
			clock_50    => CLOCK_50,
			resetn      => resetn,
			velg_enable => "000",
			enable      => hallo_enable
			);

		reset_synkroniserer : reset_synchronizer
			port map(
				clk        => CLOCK_50,
				reset_key3 => KEY(3),
				reset_clk  => resetn
				);

		klokke : component L4_klokke_AG
		port map(
			CLOCK_50    => CLOCK_50,
			resetn      => resetn,
			KEY         => KEY,
			SW          => SW(13 downto 11),
			HEX0        => HEX0,
			HEX1        => HEX1,
			HEX2        => HEX2,
			HEX3        => HEX3,
			HEX4        => HEX4,
			HEX5        => HEX5,
			bcd_hours   => bcd_hour,
			bcd_minutes => bcd_min,
			bcd_seconds => bcd_sec
			);

	p_hallo : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				hallo <= '0';
			elsif hallo_enable = '1' then
				hallo <= not hallo;
			end if;
		end if;
	end process p_hallo;

	LEDR(17) <= hallo;

	sender <= SW(17);
	LEDG(0) <= sender;
	LEDG(7) <= mottatt_blink;

	p_send_motta_hallo : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if sender = '1' then
				GPIO(1) <= hallo;
				mottatt_blink <= '0';
			else
				-- mottar hallo
				GPIO(1) <= 'Z';
				vippe_a <= GPIO(1);
				vippe_b <= vippe_a;
				mottatt_blink <= vippe_b;
			end if;
		end if;
	end process p_send_motta_hallo;

	p_baud_rate_gen : component baudrate_gen
		port map(
			CLOCK_50       => CLOCK_50,
			resetn         => resetn,
			velg_baudrate  => SW(16 downto 14),
			start_teller   => start_teller,
			baud_enable_m  => baud_enable_m,
			baud_enable_s  => baud_enable_s
		);

	data_inn <= GPIO(7) when sender = '0' else '1';
	GPIO(7) <= data_ut when sender = '1' else 'Z';

	p_start_teller : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				start_teller <= '0';
				data_inn_q <= '0';
				data_inn_qq <= '0';
				data_inn_qqq <= '0';

			else
				start_teller <= '0';
				data_inn_q <= data_inn;
				data_inn_qq <= data_inn_q;
				data_inn_qqq <= data_inn_qq;
				if data_inn_qqq = '1' and data_inn_qq = '0' then
					-- fallende flanke
					if mottak_state = s_wait_for_sender then
						start_teller <= '1';
					end if;
				end if;
			end if;
		end if;
	end process p_start_teller;

	start_sender <= KEY(0);

	p_synk_start_sender : process(CLOCK_50) is
	begin
		if rising_edge(CLOCK_50) then
			if resetn = '0' then
				start_q <= '0';
				start_qq <= '0';
			else
				start_q <= not start_sender;     -- lager aktiv høy puls
				start_qq <= start_q;
			end if;
		end if;
	end process p_synk_start_sender;

    p_bcd : process(CLOCK_50) is
    begin
        if rising_edge(CLOCK_50) then
            if sender = '1' then
                LCD_bcd <= bcd_tid(2) & bcd_tid(1) & bcd_tid(0);
            else
                LCD_bcd <= mem(2) & mem(1) & mem(0);
            end if;
        end if;
    end process;


	    p_sender_tilstandsmaskin : process(CLOCK_50) is
    begin
        if rising_edge(CLOCK_50) then
            if resetn = '0' then
                sender_state <= s_idle;
                data_ut <= '1';
            else
                if sender = '1' then
                    case sender_state is
                        when s_idle =>
                            data_ut <= '1';
                            --bcd <= bcd_tid(2) & bcd_tid(1) & bcd_tid(0);
                            send_shift_register <= (others => '0');
                            if start_qq = '1' then
                                sender_state <= s_transmit;
                            end if;
                        when s_transmit =>
                            data_ut <= '1';
                            --send_shift_register <= STOPP_BIT & SW(8 downto 1) & START_BIT;
                            case ord_teller is
                                when 0 =>
                                    send_shift_register <= STOPP_BIT & bcd_sec & START_BIT;
                                when 1 =>
                                    send_shift_register <= STOPP_BIT & bcd_min & START_BIT;
                                when 2 =>
                                    send_shift_register <= STOPP_BIT & bcd_hour & START_BIT;
                                when others =>
                                   send_shift_register <= (others => '0');
                                end case;
                            if baud_enable_s = '1' then
                                sender_state <= s_shift_out;
                            end if;
                        when s_shift_out =>
                            if baud_enable_s = '1' then
                                if send_shift_register = "0000000000" then
                                    sender_state <= s_finish;
                                    data_ut <= '1';
                                else
                                    data_ut <= send_shift_register(0);
                                   send_shift_register <= '0' & send_shift_register(9 downto 1);
                                end if;
                            end if;
                        when s_finish =>
                            if (ord_teller = 2) then
                            ord_teller <= 0;
                        else
                            ord_teller <= ord_teller + 1;
                        end if;
                            data_ut <= '1';
                            if baud_enable_s = '1' then
                                sender_state <= s_wait;
                            end if;
                        when s_wait =>
                            data_ut <= '1';
                            if baud_enable_s = '1' then
                                sender_state <= s_transmit;
                            end if;
                    end case;
                else
                    data_ut <= '1';
                end if;
            end if;
        end if;
    end process p_sender_tilstandsmaskin;

	 p_mottak_tilstandsmaskin : process(CLOCK_50) is
    begin
        if rising_edge(CLOCK_50) then
            if resetn = '0' then
                mottak_state <= s_idle_mottak;
                mottatt_data <= "00000000";
            else
                if sender = '0' then
                case mottak_state is
                    when s_idle_mottak =>
                        error <= '0';
                        --bcd <= mem(2) & mem(1) & mem(0);
                        mottak_shift_reg <= "10000000000";
                        if data_inn_qq = '1' then
                            mottak_state <= s_wait_for_sender;
                        end if;
                    when s_wait_for_sender =>
                        if start_teller = '1' then
                            mottak_state <= s_shift_in;
                        end if;
                    when s_shift_in =>
                        if mottak_shift_reg(0) = '1' and mottak_shift_reg(10) = '0' then    --Dette skal aldri skje
                            mottak_state <= s_error;
                        elsif mottak_shift_reg(0) = '1' and mottak_shift_reg(10) = '1' then  --Mottat alle databit
                            mottak_state <= s_offload;
                        elsif baud_enable_m = '1' then
                            mottak_shift_reg <= data_inn_qq & mottak_shift_reg(10 downto 1);
                        end if;
                    when s_offload =>
                        --mottatt_data <= mottak_shift_reg(9 downto 2);
                        mem(ord_teller_m) <= mottak_shift_reg(9 downto 2);
                        if (ord_teller_m = 2) then
                            ord_teller_m <= 0;
                        else
                            ord_teller_m <= ord_teller_m + 1;
                        end if;
                        mottak_state <= s_idle_mottak;
                    when s_error =>
                        error <= '1';
                end case;
              end if;
            end if;
        end if;
    end process p_mottak_tilstandsmaskin;

		LEDR(16) <= error;
		LEDR(8 downto 1) <= mottatt_data;

end architecture;