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  1. /*
  2. * Copyright 2011 Freescale Semiconductor, Inc.
  3. * Copyright 2011 Linaro Ltd.
  4. *
  5. * The code contained herein is licensed under the GNU General Public
  6. * License. You may obtain a copy of the GNU General Public License
  7. * Version 2 or later at the following locations:
  8. *
  9. * http://www.opensource.org/licenses/gpl-license.html
  10. * http://www.gnu.org/copyleft/gpl.html
  11. */
  12.  
  13. /dts-v1/;
  14. #include "imx6dl.dtsi"
  15.  
  16. / {
  17. model = "i.MX6S Hola-PC";
  18. compatible = "sk,imx6dl-hola", "fsl,imx6dl";
  19.  
  20. aliases {
  21. mxcfb0 = &mxcfb1;
  22. };
  23.  
  24. memory {
  25. reg = <0x10000000 0x20000000>;
  26. };
  27.  
  28. regulators {
  29. compatible = "simple-bus";
  30.  
  31. reg_2p5v: 2p5v {
  32. compatible = "regulator-fixed";
  33. regulator-name = "2P5V";
  34. regulator-min-microvolt = <2500000>;
  35. regulator-max-microvolt = <2500000>;
  36. regulator-always-on;
  37. };
  38.  
  39. reg_3p3v: 3p3v {
  40. compatible = "regulator-fixed";
  41. regulator-name = "3P3V";
  42. regulator-min-microvolt = <3300000>;
  43. regulator-max-microvolt = <3300000>;
  44. regulator-always-on;
  45. };
  46.  
  47. reg_usb_h1_vbus: usb_h1_vbus {
  48. compatible = "regulator-fixed";
  49. regulator-name = "usb_h1_vbus";
  50. regulator-min-microvolt = <5000000>;
  51. regulator-max-microvolt = <5000000>;
  52. gpio = <&gpio7 7 0>;
  53. enable-active-high;
  54. };
  55. };
  56.  
  57. mxcfb1: fb@0 {
  58. compatible = "fsl,mxc_sdc_fb";
  59. disp_dev = "hdmi";
  60. interface_pix_fmt = "RGB24";
  61. mode_str = "1280x720M@60";
  62. default_bpp = <32>;
  63. int_clk = <0>;
  64. late_init = <0>;
  65. status = "okay";
  66. };
  67.  
  68. sound-hdmi {
  69. compatible = "fsl,imx6q-audio-hdmi",
  70. "fsl,imx-audio-hdmi";
  71. model = "imx-audio-hdmi";
  72. hdmi-controller = <&hdmi_audio>;
  73. };
  74.  
  75. v4l2_cap_0 {
  76. compatible = "fsl,imx6q-v4l2-capture";
  77. ipu_id = <0>;
  78. csi_id = <0>;
  79. mclk_source = <0>;
  80. status = "okay";
  81. };
  82.  
  83. v4l2_out {
  84. compatible = "fsl,mxc_v4l2_output";
  85. status = "okay";
  86. };
  87. };
  88.  
  89. &fec {
  90. pinctrl-names = "default";
  91. pinctrl-0 = <&pinctrl_enet_hola>;
  92. phy-mode = "rmii";
  93. phy-reset-gpios = <&gpio1 23 0>;
  94. status = "okay";
  95. };
  96.  
  97. &hdmi_audio {
  98. status = "okay";
  99. };
  100.  
  101. &hdmi_cec {
  102. pinctrl-names = "default";
  103. pinctrl-0 = <&pinctrl_hdmi_cec_2>;
  104. status = "okay";
  105. };
  106.  
  107. &hdmi_core {
  108. ipu_id = <0>;
  109. disp_id = <1>;
  110. status = "okay";
  111. };
  112.  
  113. &hdmi_video {
  114. fsl,phy_reg_vlev = <0x0294>;
  115. fsl,phy_reg_cksymtx = <0x800d>;
  116. status = "okay";
  117. };
  118.  
  119. &i2c2 {
  120. pinctrl-names = "default";
  121. pinctrl-0 = <&pinctrl_i2c2_2>;
  122. clock-frequency = <100000>;
  123. status = "okay";
  124.  
  125. hdmi: edid@50 {
  126. compatible = "fsl,imx6-hdmi-i2c";
  127. reg = <0x50>;
  128. };
  129. };
  130.  
  131. &iomuxc {
  132. pinctrl-names = "default";
  133. pinctrl-0 = <&pinctrl_hog>;
  134.  
  135. hog {
  136. pinctrl_hog: hoggrp {
  137. fsl,pins = <
  138. /* USB Host power */
  139. MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x80000000
  140. /* SD1 CD */
  141. MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000
  142. MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x17059
  143. /* PHY Reset */
  144. MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x80000000
  145. >;
  146. };
  147. };
  148.  
  149. usdhc1 {
  150. pinctrl_usdhc1_hola: usdhc1grp-hola {
  151. fsl,pins = <
  152. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
  153. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x17059
  154. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
  155. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
  156. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
  157. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
  158. >;
  159. };
  160.  
  161. pinctrl_usdhc1_hola_100mhz: usdhc1grp-hola-100mhz {
  162. fsl,pins = <
  163. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
  164. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x170B9
  165. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
  166. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
  167. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
  168. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
  169. >;
  170. };
  171.  
  172. pinctrl_usdhc1_hola_200mhz: usdhc1grp-hola-200mhz {
  173. fsl,pins = <
  174. MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9
  175. MX6QDL_PAD_SD1_CLK__SD1_CLK 0x170F9
  176. MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9
  177. MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9
  178. MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9
  179. MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9
  180. >;
  181. };
  182. };
  183.  
  184. fec {
  185. pinctrl_enet_hola: enet-hola {
  186. fsl,pins = <
  187. MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
  188. MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
  189. MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
  190. MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
  191. MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
  192. MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
  193. MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
  194. MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
  195. MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
  196. MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
  197. >;
  198. };
  199. };
  200. };
  201.  
  202. &usbh1 {
  203. vbus-supply = <&reg_usb_h1_vbus>;
  204. status = "okay";
  205. };
  206.  
  207. &usbotg {
  208. pinctrl-names = "default";
  209. pinctrl-0 = <&pinctrl_usbotg_1>;
  210. disable-over-current;
  211. status = "okay";
  212. };
  213.  
  214. &usdhc1 {
  215. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  216. pinctrl-0 = <&pinctrl_usdhc1_hola>;
  217. pinctrl-1 = <&pinctrl_usdhc1_hola_100mhz>;
  218. pinctrl-2 = <&pinctrl_usdhc1_hola_200mhz>;
  219. cd-gpios = <&gpio2 9 0>;
  220. vmmc-supply = <&reg_3p3v>;
  221. status = "okay";
  222. };
  223.  
  224. &uart1 {
  225. pinctrl-names = "default";
  226. pinctrl-0 = <&pinctrl_uart1_1>;
  227. status = "okay";
  228. };
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