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  1. CAPI=1
  2. [main]
  3. description = "TCP/IP controlled VPI JTAG Interface"
  4. simulators = icarus
  5.  
  6. [verilog]
  7. tb_src_files = jtag_vpi.v
  8. tb_private_src_files =
  9.  bench/adv_debugsys/adbg_crc32.v
  10.  bench/adv_debugsys/adbg_jsp_biu.v
  11.  bench/adv_debugsys/adbg_jsp_module.v
  12.  bench/adv_debugsys/adbg_or1k_biu.v
  13.  bench/adv_debugsys/adbg_or1k_module.v
  14.  bench/adv_debugsys/adbg_or1k_status_reg.v
  15.  bench/adv_debugsys/adbg_wb_biu.v
  16.  bench/adv_debugsys/adbg_wb_module.v
  17.  bench/adv_debugsys/adv_dbg_if.v
  18.  bench/adv_debugsys/bytefifo.v
  19.  bench/adv_debugsys/syncflop.v
  20.  bench/adv_debugsys/syncreg.v
  21.  bench/jtag_tap/jtag_tap.v
  22.  bench/ram/ram_wb_b3.v
  23.  bench/jtag_vpi_tb.v
  24. tb_include_files =
  25.  bench/include/adbg_defines.v
  26.  bench/include/adbg_or1k_defines.v
  27.  bench/include/adbg_wb_defines.v
  28.  bench/include/tap_defines.v
  29.  bench/include/timescale.v
  30.  
  31. [vpi]
  32. name = jtag_vpi
  33. src_files = jtag_vpi.c
  34.  
  35. [plusargs]
  36. jtag-vpi-enable = bool "Enable JTAG debug interface"
  37.  
  38. [provider]
  39. name = github
  40. user = fjullien
  41. repo = jtag_vpi
  42. branch = master
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