`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13.05.2019 22:22:16
// Design Name:
// Module Name: seclock
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module final_aue(
        input clk32m,
        input [3:0] btn,
        output [6:0] digit1,
        output [6:0] digit10,
        output [6:0] digit100,
        output [6:0] digit1000,
        output [7:0] led
    );

    seclock(
        .clk(clk32m),
        .enter(btn[0]),
        .exit(btn[1]),
        .next_dig(btn[2]),
        .rotate(btn[3]),

        .q1(digit1[6:0]),
        .q2(digit10[6:0]),
        .q3(digit100[6:0]),
        .q4(digit1000[6:0]),
        .lamp(led[7:0])
    );

endmodule

module seclock(
    input clk,
    input enter,
    //input reset,
    input exit,
    input next_dig,
    input rotate,

    output [6:0] q1,
    output [6:0] q2,
    output [6:0] q3,
    output [6:0] q4,
    output [7:0] lamp
    );

    logic [3:0] num1;
    logic [3:0] num2;
    logic [3:0] num3;
    logic [3:0] num4;

    integer condition = 0;
    integer block = 0;
    int count = 0;

    logic [3:0] pass1 = 4'b0001;
    logic [3:0] pass2 = 4'b0010;
    logic [3:0] pass3 = 4'b0011;
    logic [3:0] pass4 = 4'b0100;

    logic [3:0] code1 = 4'b0000;
    logic [3:0] code2 = 4'b0000;
    logic [3:0] code3 = 4'b0000;
    logic [3:0] code4 = 4'b0000;

    logic [2:0] cur_dig = 3'b000;

    //поiхали
    main_menu c0(
        .cond(condition),
        .block(block),
        .num1(num1),
        .num2(num2),
        .num3(num3),
        .num4(num4),
        .lamp(lamp)
    );

    cond_change c1(
        .clk(clk),
        .enter(enter),
        //.reset(reset),
        .exit(exit),
        .cond_out(condition)
    );

    entering c2(
        .cond(condition),
        .clk(clk),
        .nextd(next_dig),
        .rotate(rotate),
        .pass1(pass1),
        .pass2(pass2),
        .pass3(pass3),
        .pass4(pass4),
        .block(block),
        .count(count),
        .code1(code1),
        .code2(code2),
        .code3(code3),
        .code4(code4),
        .lamp(lamp)
    );

    block_rule c3(
        .block(block),
        .count(count)
    );

    block_module c4(
        //.cond(condition),
        .block(block),
        .num1(num1),
        .num2(num2),
        .num3(num3),
        .num4(num4),
        .count(count),
        .block_out(block)
    );

    digits_conv c5(
        .num(num1),
        .dig(q1)
    );

    digits_conv c6(
        .num(num2),
        .dig(q2)
    );

    digits_conv c7(
        .num(num3),
        .dig(q3)
    );

    digits_conv c8(
        .num(num4),
        .dig(q4)
    );

    show_enter c9(
        .code1(code1),
        .code2(code2),
        .code3(code3),
        .code4(code4),
        .num1(num1),
        .num2(num2),
        .num3(num3),
        .num4(num4)
    );

endmodule

module cond_change(
    input clk,
    input enter,
    input reset,
    input exit,
    output integer cond_out
    );

    always @(posedge clk) begin
        if(enter) begin
            cond_out = 2;
        end
        else if(exit) begin
            cond_out = 0;
        end
    end

endmodule

module main_menu(
    input cond,
    input block,
    output logic [3:0] num1,
    output logic [3:0] num2,
    output logic [3:0] num3,
    output logic [3:0] num4,
    output logic [6:0] lamp
    );

    always @ (cond == 0 && block == 0) begin
        num1 <= 4'b1010;
        num2 <= 4'b1010;
        num3 <= 4'b1010;
        num4 <= 4'b1010;
        lamp <= 7'b0000000;
    end;

endmodule

module block_rule(
        input integer count,
        output integer block
    );

    always @ (count == 3) begin
        block <= 1;
    end

endmodule

module block_module(
    input integer block,
    output logic [3:0] num1,
    output logic [3:0] num2,
    output logic [3:0] num3,
    output logic [3:0] num4,
    output integer block_out,
    //output integer cond,
    output integer count
    );
    always @ (block == 1) begin
        num1 <= 4'b0000;
        num2 <= 4'b0000;
        num3 <= 4'b0000;
        repeat (60) begin
            #50 num4 <= num4 + 1;                   //maybe not 1000000
            if(num4 > 10) begin
                num4 <= 4'b0000;
                num3 <= num3 + 1;
            end;
        end;
        //cond <= 0;
        block_out <= 0;
        count <= 0;
    end;

endmodule

module digits_conv(
    input [3:0]num,
    output logic [6:0] dig
    );

    always_comb begin
        if (num == 4'b0000) dig <= 7'b0111111; // 0d
        if (num == 4'b0001) dig <= 7'b0110000; // 1d
        if (num == 4'b0010) dig <= 7'b1011011; // 2d
        if (num == 4'b0011) dig <= 7'b1001111; // 3d
        if (num == 4'b0100) dig <= 7'b1100110; // 4d
        if (num == 4'b0101) dig <= 7'b1101101; // 5d
        if (num == 4'b0110) dig <= 7'b1111101; // 6d
        if (num == 4'b0111) dig <= 7'b0000111; // 7d
        if (num == 4'b1000) dig <= 7'b1111111; // 8d
        if (num == 4'b1001) dig <= 7'b1101111; // 9d
        if (num == 4'b1010) dig <= 7'b1000000; // -d
    end

endmodule

module show_enter(
        input logic [3:0] code1,
        input logic [3:0] code2,
        input logic [3:0] code3,
        input logic [3:0] code4,
        input integer cond,
        output logic [3:0] num1,
        output logic [3:0] num2,
        output logic [3:0] num3,
        output logic [3:0] num4
    );

    always @ (cond == 2) begin
        num1 <= code1;
        num2 <= code2;
        num3 <= code3;
        num4 <= code4;
    end

endmodule

module entering(
    input cond,
    input clk,
    input nextd,
    input rotate,
    input logic [3:0] pass1,
    input logic [3:0] pass2,
    input logic [3:0] pass3,
    input logic [3:0] pass4,
    output integer count,
    input integer block,
    output logic [3:0] code1,
    output logic [3:0] code2,
    output logic [3:0] code3,
    output logic [3:0] code4,
    output logic [7:0] lamp
    //output logic [2:0] dig

    );

    logic [2:0] dig;
    initial dig = 3'b000;
    initial code1 = 4'b0000;
    initial code2 = 4'b0000;
    initial code3 = 4'b0000;
    initial code4 = 4'b0000;

    always @ (posedge clk) begin
        if((rotate) & (cond == 2) & (block == 0) & (dig == 0)) begin
            code1 <= code1 + 1;
            if(code1 > 9) begin
                code1 <= 4'b0000;
            end
        end
        if((rotate) & (cond == 2) & (block == 0) & (dig == 1)) begin
            code1 <= code1 + 1;
            if(code1 > 9) begin
                code1 <= 4'b0000;
            end
        end
        if((rotate) & (cond == 2) & (block == 0) & (dig == 2)) begin
            code1 <= code1 + 1;
            if(code1 > 9) begin
                code1 <= 4'b0000;
            end
        end
        if((rotate) & (cond == 2) & (block == 0) & (dig == 3)) begin
            code1 <= code1 + 1;
            if(code1 > 9) begin
                code1 <= 4'b0000;
            end
        end

        if((nextd) & (cond == 2) & (block == 0) & (dig == 3)) begin
            if(code1 == pass1 && code2 == pass2 && code3 == pass3 && code4 == pass4) begin
                lamp <= 8'b11111111;
                dig <= 3'b000;
            end
            else begin
                lamp <= 8'b10000001;
                count <= count + 1;
                dig <= 3'b000;
            end
        end
        else if((nextd) & (cond == 2) & (block == 0)) begin
            dig <= dig + 1;
        end
    end

endmodule

//module dig_cur(
//        input [2:0] dig1,
//        output logic [2:0] dig2
//    );

//    if(dig1 == 4) begin

//    end
//endmodule
//module clicker(
//    input btn,
//    input clk,
//    output logic q
//    );

//    logic t1;
//    logic t2;

//    always_ff @(posedge clk) begin
//        {t2,t1} <= {t1,!btn};
//    end

//    assign q = t1 & !t2;
//endmodule