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  1. signal b :  std_logic_vector(31 downto 0);
  2.     signal e :  std_logic_vector(23 downto 0);
  3. signal right : std_logic_vector((DATA_WIDTH)-1 downto 0);
  4. signal left  :  std_logic_vector((DATA_WIDTH)-1 downto 0);
  5. signal left_shifted  :  std_logic_vector((2*DATA_WIDTH)-1 downto 0);
  6. signal new_right  :  std_logic_vector((2*DATA_WIDTH)-1 downto 0);
  7.    
  8. a => a(15 downto 0),
  9. **b => b(15 downto 0),**   here is error line 42
  10. c => right
  11.    
  12. MULTIPLIER_left:entity work.mult16bit
  13.    
  14. a => a(31 downto 16),
  15. b => b(31 downto 16),
  16. c => left
  17.    
  18. left_shifted <= left & "00000000000000000000000000000000" ;
  19.     -- left_shifted <= std_logic_vector("sll"(unsigned(left), 8));
  20.  
  21.      new_right <= "00000000000000000000000000000000" & right;
  22.  
  23.  
  24.      c <= unsigned(new_right) + unsigned(left_shifted) ;
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