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- // -------------------------
- // Somador Completo para um bit
- // Output carryOut("vai um")
- // Output soma(resultado da soma)
- // inputs a,b,CarryIn("Vem um")
- // -------------------------
- module fullAdder ( output carryOut,output soma,input a,input b,input carryIn );
- wire nota;
- wire notb;
- wire notcarryIn;
- wire and1;
- wire and2;
- wire and3;
- wire and4;
- wire and5;
- wire and6;
- wire and7;
- wire and8;
- not notA(nota,a);
- not notB(notb,b);
- not notcarry(notcarryIn,carryIn);
- and and1(and1,nota,notb,carryIn);
- and and2(and2,nota,b,notcarryIn);
- and and3(and3,a,notb,notcarryIn);
- and and4(and4,a,b,carryIn);
- or or1(soma,and1,and2,and3,and4);
- and and5(and5,nota,b,carryIn);
- and and6(and6,a,notb,notcarryIn);
- and and7(and7,a,b,notcarryIn);
- and and8(and8,a,b,carryIn);
- or or2(carryOut,a,b,carryIn);
- endmodule // fullAdder
- module test_fullAdder;
- // ------------------------- definir dados
- reg [3:0] a;
- reg [3:0] b;
- wire [3:0] carryOut; // “vai-um”
- wire [4:0] soma;
- fullAdder FA0 ( carryOut[0], soma[0], a[0], b[0],1'b0);
- fullAdder FA1 ( carryOut[1], soma[1], a[1], b[1],carryOut[0]);
- fullAdder FA2 ( carryOut[2], soma[2], a[2], b[2],carryOut[1]);
- fullAdder FA3 ( carryOut[3], soma[3], a[3], b[3],carryOut[2]);
- assign soma[4]=carryOut[3];
- // ------------------------- parte principal
- initial begin
- $display(" a b soma vai(carry)");
- $monitor("%4b %4b %4b %4b", a, b, soma, carryOut);
- a = 4'b0000; b = 4'b0000;
- #1 a = 4'b0001; b = 4'b0001;
- #1 a = 4'b0010; b = 4'b0010;
- #1 a = 4'b0011; b = 4'b0011;
- end
- endmodule // test_fullAdder
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