Command Line: /opt/xilinx/13.2/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -p
xc6slx16-3csg324 -uc ..//backend/nexys3_master.ucf -aul minsoc_top.ngc
minsoc.ngd

Reading NGO file "/home/jay/openrisc/minsoc/syn/minsoc_top.ngc" ...
Loading design module "/home/jay/openrisc/minsoc/syn/uart_top.ngc"...
Loading design module "/home/jay/openrisc/minsoc/syn/adbg_top.ngc"...
Loading design module "/home/jay/openrisc/minsoc/syn/or1200_top.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "..//backend/nexys3_master.ucf"
...
Resolving constraint associations...
Checking Constraint Associations...
Done...

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'tap_top' with type
   'minsoc_xilinx_internal_jtag' could not be resolved. A pin name misspelling
   can cause this, a missing edif or ngc file, case mismatch between the block
   name and the edif or ngc file name, or the misspelling of a type name. Symbol
   'minsoc_xilinx_internal_jtag' is not supported in target 'spartan6'.

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:   0

Total REAL time to NGDBUILD completion:  8 sec
Total CPU time to NGDBUILD completion:   8 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "minsoc.bld"...
make: *** [minsoc.ngd] Error 2