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- module comp(
- output lt, eq, gt,
- input a, b);
- xnor x1(eq, a, b);
- wire o1, o2;
- not n1(o1, a);
- not n2(o2, b);
- and nd1(lt, o1, b);
- and nd2(gt, o2, a);
- endmodule
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