module test_wires(
  input wire [3:0] key,
  input wire clock,
  output wire [7:0] led
);

reg[12:0] counter;
reg[12:0] counter2;
reg on;
reg on2;

assign led[0] = on2;

always @(posedge clock)
begin
  counter = counter+1'b1;
  if (counter == 4095)
  begin
    on = !on;
  end;
end

always @(posedge on)
begin
  counter2 = counter2+1'b1;
  if (counter2 == 4095)
  begin
    on2 = !on2;
  end;
end

endmodule