API tools faq
paste
Guest User

ipq5018-express-UX.dts

a guest
Feb 27th, 2025
41
0
Never
Add comment
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
text 8.64 KB | None | 0 0
raw download clone embed print report
  1. /dts-v1/;
  2.  
  3. #include "ipq5018.dtsi"
  4. #include "ipq5018-ess.dtsi"
  5.  
  6. #include <dt-bindings/gpio/gpio.h>
  7. #include <dt-bindings/input/input.h>
  8. #include <dt-bindings/leds/common.h>
  9.  
  10. / {
  11. model = "Unifi Express UX/UXG Lite";
  12. compatible = "unifi,express-ux", "qcom,ipq5018";
  13.  
  14. aliases {
  15. ethernet0 = &dp1;
  16. ethernet1 = &dp2;
  17. led-boot = &led_system_blue;
  18. led-failsafe = &led_system_red;
  19. led-running = &led_system_blue;
  20. led-upgrade = &led_system_red;
  21. serial0 = &blsp1_uart1;
  22. };
  23.  
  24. chosen {
  25. bootargs-append = " root=/dev/ubiblock0_0 coherent_pool=2M";
  26. stdout-path = "serial0:115200n8";
  27. };
  28.  
  29. keys {
  30. compatible = "gpio-keys";
  31. pinctrl-0 = <&button_pins>;
  32. pinctrl-names = "default";
  33.  
  34. wps-button {
  35. label = "wps";
  36. gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
  37. linux,code = <KEY_WPS_BUTTON>;
  38. };
  39.  
  40. reset-button {
  41. label = "reset";
  42. gpios = <&tlmm 28 GPIO_ACTIVE_LOW>;
  43. linux,code = <KEY_RESTART>;
  44. };
  45. };
  46.  
  47. leds {
  48. compatible = "pwm-leds";
  49.  
  50. led_system_red: red {
  51. color = <LED_COLOR_ID_RED>;
  52. function = LED_FUNCTION_POWER;
  53. pwms = <&pwm 3 1250000>;
  54. max-brightness = <255>;
  55. };
  56.  
  57. green {
  58. color = <LED_COLOR_ID_GREEN>;
  59. function = LED_FUNCTION_POWER;
  60. pwms = <&pwm 0 1250000>;
  61. max-brightness = <255>;
  62. };
  63.  
  64. led_system_blue: blue {
  65. color = <LED_COLOR_ID_BLUE>;
  66. function = LED_FUNCTION_POWER;
  67. pwms = <&pwm 1 1250000>;
  68. max-brightness = <255>;
  69. };
  70. };
  71.  
  72. reserved-memory {
  73. q6_mem_regions: q6_mem_regions@4b000000 {
  74. no-map;
  75. reg = <0x0 0x4b000000 0x0 0x3000000>;
  76. };
  77. };
  78. };
  79.  
  80. &sleep_clk {
  81. clock-frequency = <32000>;
  82. };
  83.  
  84. &xo_board_clk {
  85. clock-frequency = <24000000>;
  86. };
  87.  
  88. &blsp1_uart1 {
  89. status = "okay";
  90.  
  91. pinctrl-0 = <&serial_0_pins>;
  92. pinctrl-names = "default";
  93. };
  94.  
  95. &crypto {
  96. status = "okay";
  97. };
  98.  
  99. &cryptobam {
  100. status = "okay";
  101. };
  102.  
  103. &prng {
  104. status = "okay";
  105. };
  106.  
  107. &pwm {
  108. status = "okay";
  109.  
  110. #pwm-cells = <2>;
  111. pinctrl-0 = <&pwm_pins>;
  112. pinctrl-names = "default";
  113. };
  114.  
  115. &qfprom {
  116. status = "okay";
  117. };
  118.  
  119. &qpic_bam {
  120. status = "okay";
  121. };
  122.  
  123. &qpic_nand {
  124. pinctrl-0 = <&qpic_pins>;
  125. pinctrl-names = "default";
  126. status = "okay";
  127.  
  128. partitions {
  129. status = "disabled";
  130. };
  131.  
  132. nand@0 {
  133. compatible = "spi-nand";
  134. reg = <0>;
  135. #address-cells = <1>;
  136. #size-cells = <1>;
  137.  
  138. nand-ecc-engine = <&qpic_nand>;
  139.  
  140. nand-ecc-strength = <8>;
  141. nand-ecc-step-size = <512>;
  142. nand-bus-width = <8>;
  143.  
  144. partitions {
  145. compatible = "fixed-partitions";
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148.  
  149. partition-sbl1@0 {
  150. label = "SBL1";
  151. reg = <0x00000000 0x30000>;
  152. read-only;
  153. };
  154.  
  155. partition-mibib@30000 {
  156. label = "MIBIB";
  157. reg = <0x00030000 0x10000>;
  158. read-only;
  159. };
  160.  
  161. partition-bootconfig@40000 {
  162. label = "BOOTCONFIG";
  163. reg = <0x00040000 0x100000>;
  164. read-only;
  165. };
  166.  
  167. partition-qsee@50000 {
  168. label = "QSEE";
  169. reg = <0x00050000 0xa0000>;
  170. read-only;
  171. };
  172.  
  173. partition-devcfg@f0000 {
  174. label = "DEVCFG";
  175. reg = <0x000f0000 0x10000>;
  176. read-only;
  177. };
  178.  
  179. partition-cdt@100000 {
  180. label = "CDT";
  181. reg = <0x00100000 0x10000>;
  182. read-only;
  183. };
  184.  
  185. partition-appsblenv@110000 {
  186. label = "APPSBLENV";
  187. reg = <0x00110000 0x10000>;
  188. read-only;
  189. };
  190.  
  191. partition-appsbl@120000 {
  192. label = "APPSBL";
  193. reg = <0x00120000 0xa0000>;
  194. read-only;
  195. };
  196.  
  197. partition-art@1c0000 {
  198. label = "ART";
  199. reg = <0x001c0000 0x70000>;
  200. read-only;
  201.  
  202. nvmem-layout {
  203. compatible = "fixed-layout";
  204. #address-cells = <1>;
  205. #size-cells = <1>;
  206.  
  207. mac_base: mac-address@33000 {
  208. reg = <0x0 0x6>;
  209. };
  210. };
  211. };
  212.  
  213. partition-eeprom@230000 {
  214. label = "EEPROM";
  215. reg = <0x00230000 0x10000>;
  216. read-only;
  217. };
  218.  
  219. partition-config@240000 {
  220. label = "config";
  221. reg = <0x00240000 0x5c0000>;
  222. };
  223. };
  224. };
  225. };
  226.  
  227. /*
  228. * =================================================================
  229. * _______________________ _______________________
  230. * | IPQ5018 | | |
  231. * | +------+ +--------+ | | +------+ |
  232. * | | MAC0 |---| GE Phy |-+--- MDI ---+ | MAC | |
  233. * | +------+ +--------+ | | +------+ |
  234. * | | |_______________________|
  235. * | | _______________________
  236. * | | | QCA8081 |
  237. * | +------+ +--------+ | | +--------+ +------+ |
  238. * | | MAC1 |---| Uniphy |-+-- SGMII+--+ | Phy |---| MAC | |
  239. * | +------+ +--------+ | | +--------+ +------+ |
  240. * |_______________________| |_______________________|
  241. *
  242. * =================================================================
  243. */
  244.  
  245. &switch {
  246. status = "okay";
  247.  
  248. switch_mac_mode = <MAC_MODE_SGMII_CHANNEL0>;
  249.  
  250. qcom,port_phyinfo {
  251. // MAC0 -> GE Phy
  252. port@0 {
  253. port_id = <1>;
  254. mdiobus = <&mdio0>;
  255. phy_address = <7>;
  256. };
  257.  
  258. // MAC1 -> Uniphy --- SGMII --- QCA8081
  259. port@1 {
  260. port_id = <2>;
  261. mdiobus = <&mdio1>;
  262. phy_address = <28>;
  263. port_mac_sel = "QGMAC_PORT";
  264. };
  265. };
  266. };
  267.  
  268. // MAC0 -> GE Phy
  269. &dp1 {
  270. status = "okay";
  271.  
  272. nvmem-cells = <&mac_addr>;
  273. nvmem-cell-names = "mac-address";
  274. };
  275.  
  276. // MAC1 ---SGMII---> QCA8081
  277. &dp2 {
  278. status = "okay";
  279.  
  280. label = "wan";
  281. phy-handle = <&qca8081>;
  282. nvmem-cells = <&mac_base>;
  283. nvmem-cell-names = "mac-address";
  284. };
  285.  
  286. &mdio0 {
  287. status = "okay";
  288. };
  289.  
  290. &mdio1 {
  291. status = "okay";
  292.  
  293. pinctrl-0 = <&mdio1_pins>;
  294. pinctrl-names = "default";
  295.  
  296. // QCA8081 Phy -> WAN
  297. qca8081: ethernet-phy@28 {
  298. compatible = "ethernet-phy-id004d.d101";
  299. reg = <28>;
  300. reset-deassert-us = <10000>;
  301. reset-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
  302. };
  303. };
  304.  
  305. &tlmm {
  306. button_pins: button-state {
  307. pins = "gpio27", "gpio28";
  308. function = "gpio";
  309. drive-strength = <8>;
  310. bias-pull-up;
  311. };
  312.  
  313. mdio1_pins: mdio-state {
  314. mdc-pins {
  315. pins = "gpio36";
  316. function = "mdc";
  317. drive-strength = <8>;
  318. bias-pull-up;
  319. };
  320.  
  321. mdio-pins {
  322. pins = "gpio37";
  323. function = "mdio";
  324. drive-strength = <8>;
  325. bias-pull-up;
  326. };
  327. };
  328.  
  329. pwm_pins: pwm-state {
  330. mux_1 {
  331. pins = "gpio1";
  332. function = "pwm1";
  333. drive-strength = <8>;
  334. };
  335.  
  336. mux_2 {
  337. pins = "gpio30";
  338. function = "pwm3";
  339. drive-strength = <8>;
  340. };
  341.  
  342. mux_3 {
  343. pins = "gpio46";
  344. function = "pwm0";
  345. drive-strength = <8>;
  346. };
  347. };
  348.  
  349. qpic_pins: qpic-state {
  350. clock-pins {
  351. pins = "gpio9";
  352. function = "qspi_clk";
  353. drive-strength = <8>;
  354. bias-disable;
  355. };
  356.  
  357. cs-pins {
  358. pins = "gpio8";
  359. function = "qspi_cs";
  360. drive-strength = <8>;
  361. bias-disable;
  362. };
  363.  
  364. data-pins {
  365. pins = "gpio4", "gpio5", "gpio6", "gpio7";
  366. function = "qspi_data";
  367. drive-strength = <8>;
  368. bias-disable;
  369. };
  370. };
  371.  
  372. serial_0_pins: uart0-state {
  373. pins = "gpio20", "gpio21";
  374. function = "blsp0_uart0";
  375. bias-disable;
  376. };
  377. };
  378.  
  379. &tsens {
  380. status = "okay";
  381. };
  382.  
  383. &pcie0_phy {
  384. status = "okay";
  385. };
  386.  
  387. &pcie0 {
  388. status = "okay";
  389.  
  390. perst-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>;
  391.  
  392. bridge@0,0 {
  393. reg = <0x00000000 0 0 0 0>;
  394. #address-cells = <3>;
  395. #size-cells = <2>;
  396. ranges;
  397.  
  398. wifi@1,0 {
  399. status = "okay";
  400.  
  401. /* QCN9074: ath11k lacks DT compatible for PCI cards */
  402. compatible = "pci17cb,1104";
  403. reg = <0x00010000 0 0 0 0>;
  404.  
  405. qcom,ath11k-calibration-variant = "Unifi-Express-UX";
  406. };
  407. };
  408. };
  409.  
  410. &q6v5_wcss {
  411. status = "okay";
  412.  
  413. memory-region = <&q6_mem_regions>;
  414. firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt",
  415. "ath11k/IPQ5018/hw1.0/m3_fw.mdt";
  416.  
  417. // IPQ5018
  418. q6_wcss_pd1: pd-1 {
  419. firmware-name = "ath11k/IPQ5018/hw1.0/q6_fw.mdt";
  420.  
  421. resets =
  422. <&gcc GCC_WCSSAON_RESET>,
  423. <&gcc GCC_WCSS_BCR>,
  424. <&gcc GCC_CE_BCR>;
  425. reset-names =
  426. "wcss_aon_reset",
  427. "wcss_reset",
  428. "ce_reset";
  429.  
  430. clocks =
  431. <&gcc GCC_WCSS_AHB_S_CLK>,
  432. <&gcc GCC_WCSS_ACMT_CLK>,
  433. <&gcc GCC_WCSS_AXI_M_CLK>;
  434. clock-names =
  435. "gcc_wcss_ahb_s_clk",
  436. "gcc_wcss_acmt_clk",
  437. "gcc_wcss_axi_m_clk";
  438.  
  439. interrupts-extended =
  440. <&wcss_smp2p_in 8 0>,
  441. <&wcss_smp2p_in 9 0>,
  442. <&wcss_smp2p_in 12 0>,
  443. <&wcss_smp2p_in 11 0>;
  444. interrupt-names =
  445. "fatal",
  446. "ready",
  447. "spawn-ack",
  448. "stop-ack";
  449.  
  450. qcom,smem-states =
  451. <&wcss_smp2p_out 8>,
  452. <&wcss_smp2p_out 9>,
  453. <&wcss_smp2p_out 10>;
  454. qcom,smem-state-names =
  455. "shutdown",
  456. "stop",
  457. "spawn";
  458. };
  459. };
  460.  
  461. &wifi0 {
  462. // IPQ5018
  463. qcom,rproc = <&q6_wcss_pd1>;
  464. qcom,ath11k-calibration-variant = "Unifi-Express-UX";
  465. qcom,ath11k-fw-memory-mode = <2>;
  466. qcom,bdf-addr = <0x4c400000>;
  467.  
  468. status = "okay";
  469. };
  470.  
Advertisement
Add Comment
Please, Sign In to add comment
Public Pastes
We use cookies for various purposes including analytics. By continuing to use Pastebin, you agree to our use of cookies as described in the Cookies Policy.  OK, I Understand
Not a member of Pastebin yet?
Sign Up, it unlocks many cool features!