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- #include "stm32f3xx.h"
- int main(void)
- {
- // Initialize the HSI:
- RCC->CR |= RCC_CR_HSION;
- while(!(RCC->CR&RCC_CR_HSIRDY));
- // Initialize the LSI:
- // RCC->CSR |= RCC_CSR_LSION;
- // while(!(RCC->CSR & RCC_CSR_LSIRDY));
- // PLL configuration:
- RCC->CFGR &= ~RCC_CFGR_PLLSRC; // HSI / 2 selected as the PLL input clock.
- RCC->CFGR |= RCC_CFGR_PLLMUL16; // HSI / 2 * 16 = 64 MHz
- RCC->CR |= RCC_CR_PLLON; // Enable PLL
- while(!(RCC->CR&RCC_CR_PLLRDY)); // Wait until PLL is ready
- // Flash configuration:
- FLASH->ACR |= FLASH_ACR_PRFTBE;
- FLASH->ACR |= FLASH_ACR_LATENCY_1;
- // Main clock output (MCO):
- RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
- GPIOA->MODER |= GPIO_MODER_MODER8_1;
- GPIOA->OTYPER &= ~GPIO_OTYPER_OT_8;
- GPIOA->PUPDR &= ~GPIO_PUPDR_PUPDR8;
- GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR8;
- GPIOA->AFR[0] &= ~GPIO_AFRL_AFRL0;
- // Output on the MCO pin:
- //RCC->CFGR |= RCC_CFGR_MCO_HSI;
- //RCC->CFGR |= RCC_CFGR_MCO_LSI;
- //RCC->CFGR |= RCC_CFGR_MCO_PLL;
- RCC->CFGR |= RCC_CFGR_MCO_SYSCLK;
- // PLL as the system clock
- RCC->CFGR &= ~RCC_CFGR_SW; // Clear the SW bits
- RCC->CFGR |= RCC_CFGR_SW_PLL; //Select PLL as the system clock
- while ((RCC->CFGR & RCC_CFGR_SWS_PLL) != RCC_CFGR_SWS_PLL); //Wait until PLL is used
- // Bit-bang monitoring:
- RCC->AHBENR |= RCC_AHBENR_GPIOEEN;
- GPIOE->MODER |= GPIO_MODER_MODER10_0;
- GPIOE->OTYPER &= ~GPIO_OTYPER_OT_10;
- GPIOE->PUPDR &= ~GPIO_PUPDR_PUPDR10;
- GPIOE->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR10;
- while(1)
- {
- GPIOE->BSRRL |= GPIO_BSRR_BS_10;
- GPIOE->BRR |= GPIO_BRR_BR_10;
- }
- }
- arm-none-eabi-objdump -S yourprog.elf
- arm-none-eabi-gcc
- -O1 ## your optimization level
- -S ## stop after generating assembly, i.e. don't run `as`
- -I/path/to/CMSIS/ST/STM32F3xx/ -I/path/to/CMSIS/include
- test.c
- .L5:
- ldr r2, [r3, #24]
- orr r2, r2, #1024
- str r2, [r3, #24]
- ldr r2, [r3, #40]
- orr r2, r2, #1024
- str r2, [r3, #40]
- b .L5
- GPIOE->BSRRL |= GPIO_BSRR_BS_10;
- GPIOE->BRR |= GPIO_BRR_BR_10;
- GPIOE->BSRRL = GPIO_BSRR_BS_10;
- GPIOE->BRR = GPIO_BRR_BR_10;
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