Lab1Zadanie2UcyfB

ZADANIE B1
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity B1 is
port
(
	A1, B1, S1 : in std_logic_vector (7 downto 0);
	F1 : out std_logic_vector(1 downto 0);
	X1 : out std_logic_vector(7 downto 0)
);
end entity;

architecture structB1 of B1 is
signal temp : std_logic_vector (8 downto 0);
begin
	temp <= ('0' & std_logic_vector(unsigned(A1) + unsigned(B1) + 1)) when S1(0) = '0' else
		  ('0' & std_logic_vector(unsigned(A1) - unsigned(B1)));
	X1 <= std_logic_vector(unsigned(A1) + unsigned(B1) + 1) when S1(0) = '0' else
		  std_logic_vector(unsigned(A1) - unsigned(B1));

	process(temp)
	begin
	if(temp(8) = '1') then F1 <= "10"; else
						  F1 <= "01";
						  end if;
	end process;


end architecture;
ZADANIE B2
library IEEE;
use IEEE.std_logic_1164.all;

entity B2 is
port
(
	C2, D2, S2, X2 : in std_logic_vector (7 downto 0);
	F2_i : in std_logic_vector(1 downto 0);
	M2 : out std_logic_vector(7 downto 0);
	F2_o : out std_logic_vector(0 downto 0)
);
end entity;

architecture structB2 of B2 is
begin

process(F2_i)
begin
	if(F2_i = "10") then M2 <= "11111111"; else
		case(S2(2 downto 1)) is
			 when "01" => M2 <= C2;
			 when "10" => M2 <= D2;
			 when others => M2 <= X2;
		end case;
	end if;
end process;

F2_o <= "1" when F2_i = "10";

end architecture;
ZADANIE B3
library IEEE;
use IEEE.std_logic_1164.all;

entity B3 is
port
(
	M3, S3 : in std_logic_vector (7 downto 0);
	H0_3, H1_3, H2_3, H3_3 : out std_logic_vector(3 downto 0)
);
end entity;

architecture structB3 of B3 is
begin

process(S3)
begin
	if(S3(7 downto 6) = "01") then
		H0_3 <= M3(7 downto 4);
		H1_3 <= M3(3 downto 0);
		H2_3 <= "0000";
		H3_3 <= "0000";
	elsif(S3(7 downto 6) = "00") then
		H0_3 <= M3(7 downto 4);
		H1_3 <= "0000";
	    H2_3 <= M3(3 downto 0);
	    H3_3 <= "0000";
	else
	    H0_3 <= M3(7 downto 4);
	    H1_3 <= "0000";
		H2_3 <= "0000";
	    H3_3 <= M3(3 downto 0);

end if;
end process;

end architecture;
ZADANIE ZB
library IEEE;
use IEEE.std_logic_1164.all;

entity zB is
port
(
	A,B,C,D,s : in std_logic_vector(7 downto 0);
	X : out std_logic_vector(7 downto 0);
	F : out std_logic_vector(3 downto 0);
	H0, H1, H2, H3 : out std_logic_vector(3 downto 0)
);
end entity;

architecture structure of zB is
component B1
port
(
	A1, B1, S1 : in std_logic_vector (7 downto 0);
	F1 : out std_logic_vector(1 downto 0);
	X1 : out std_logic_vector(7 downto 0)
);
end component;

component B2
port
(
	C2, D2, S2, X2 : in std_logic_vector (7 downto 0);
	F2_i : in std_logic_vector(1 downto 0);
	M2 : out std_logic_vector(7 downto 0);
	F2_o : out std_logic_vector(0 downto 0)
);
end component;

component B3
port
(
	M3, S3 : in std_logic_vector (7 downto 0);
	H0_3, H1_3, H2_3, H3_3 : out std_logic_vector(3 downto 0)
);
end component;

signal XX, MM : std_logic_vector(7 downto 0);
signal FF : std_logic_vector(1 downto 0);

begin

blokB1 : B1
	port map(A1 => A, B1 => B, S1 => S, X1 => X, F1 => F(3 downto 2));

blokB2 : B2
	port map(C2 => C, D2 => D, X2 => XX, S2 => S, F2_i => FF, M2 => MM, F2_o => F(0 downto 0));

blokB3 : B3
	port map(M3 => MM, S3 => S, H0_3 => H0, H1_3 => H1, H2_3 => H2, H3_3 => H3);
end architecture;