-- TestBench Template

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;

  ENTITY testbench IS
  END testbench;

  ARCHITECTURE behavior OF testbench IS

  -- Component Declaration
          COMPONENT kod
          PORT(
				X : in STD_LOGIC;
				Y : out STD_LOGIC;
				CLR : in STD_LOGIC;
				CLK : in STD_LOGIC;
				CE : in STD_LOGIC;
        );
    END COMPONENT;


   --Inputs
   signal X : std_logic := '0';
   signal Y : std_logic := '0';
   signal CLR : std_logic := '0';
	signal CLK : std_logic := '0';
	signal CE : std_logic := '0';

  --Outputs
   signal Y : std_logic;

   -- Clock period definitions
   constant clock_period : time := 10 ns;




  BEGIN

-- Clock process definitions
   clock_process :process
   begin
	  clock <= '0';
	  wait for clock_period;
	  clock <= '1';
	  wait for clock_period;
   end process;


  END;