// gcc -m32 -S -O2 testra.c
extern __attribute__((fastcall)) void bar0(int);
extern __attribute__((fastcall)) void bar1(int, int);
extern __attribute__((fastcall)) void bar2(int, int);
extern __attribute__((fastcall)) int bar3(int, int);
void __attribute__((fastcall)) foo(int a, int b) {
  int c = a * b;
  int d = bar3(a, b);
  bar0(c);
  bar1(a, c);
  bar2(b, c);
  bar2(b, d);
  bar2(a, d);
}
/*
which shows (with d spilled， and r89 is d):
********** Inheritance #1: **********

EBB 2
    <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      Creating newreg=93 from oldreg=89, assigning class GENERAL_REGS to inheritance r93
    Original reg change 89->93 (bb2):
   24: dx:SI=r93:SI
    Add inheritance<-original before:
   38: r93:SI=r89:SI

    Inheritance reuse change 89->93 (bb2):
   28: dx:SI=r93:SI
      REG_DEAD r93:SI
	  >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
    <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
      Creating newreg=94 from oldreg=89, assigning class GENERAL_REGS to inheritance r94
    Original reg change 89->94 (bb2):
   12: r94:SI=ax:SI
      REG_DEAD ax:SI
    Add original<-inheritance after:
   39: r89:SI=r94:SI

    Inheritance reuse change 89->94 (bb2):
   38: r93:SI=r94:SI
	  >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
	    Removing dead insn:
    39: r89:SI=r94:SI
deleting insn with uid = 39.
...
********** Assignment #1: **********

	 Assigning to 92 (cl=GENERAL_REGS, orig=88, freq=3000, tfirst=92, tfreq=3000)...
	   Assign 6 to reload r92 (freq=3000)
	 Assigning to 93 (cl=GENERAL_REGS, orig=89, freq=3000, tfirst=93, tfreq=3000)...
	   Assign 6 to inheritance r93 (freq=3000)
	Hard reg 0 is preferable by r94 with profit 1000
	Hard reg 6 is preferable by r94 with profit 1000
	 Assigning to 94 (cl=GENERAL_REGS, orig=89, freq=2000, tfirst=93, tfreq=3000)...
  Reassigning non-reload pseudos

********** Undoing inheritance #1: **********

Inherit 1 out of 2 (50.00%)
   Insn after restoring regs:
   38: r93:SI=r89:SI
      REG_DEAD r89:SI
   Insn after restoring regs:
   12: r89:SI=ax:SI
      REG_DEAD ax:SI
*/