module ram1(

input clk,
input [11:0] addr,
input [15:0] din,
input write_en,
output reg [15:0] dout

);

 parameter addr_width = 12;
 parameter data_width = 16;

 integer i;
 reg [data_width-1:0] dout; // Register for output.
 reg [data_width-1:0] mem1 [0:4095];
 initial begin
	for (i = 0; i < 4096; i = i + 1) begin
 		mem1[i] <= 0; // Initialize the RAM with 0
 	end
 end //mem[1:0] <= "A";
 always @(posedge clk)
 begin
 if (write_en)
 	mem1[(addr)] <= din;
 dout = mem1[addr]; // Output register controlled by clock.
 end


endmodule