-- Module: XC3S_RAMB_1_PORT
-- Description: 18Kb Block SelectRAM example
-- Single Port 512 x 36 bits
-- Use template "SelectRAM_A36.vhd"
--
-- Device: Spartan-3 Family
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--
-- Syntax for Synopsys FPGA Express
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--
entity dual_port_ram is
  port (
    data_in : in std_logic_vector (0 downto 0) := (others => '0');
    write_address : in std_logic_vector (13 downto 0) := (others => '0');
    write_enable : in std_logic := '0';
    ram_write_mask : in std_logic_vector(7 downto 0) := (others => '0');

    enable : in std_logic := '0';
    clk : in std_logic := '0';
    reset : in std_logic := '0';

    ram_read_mask : in std_logic_vector(7 downto 0) := (others => '0');
    read_address : in std_logic_vector(13 downto 0) := (others => '0');
    data_out : out std_logic_vector (0 downto 0) := (others => '0')

  );
end dual_port_ram;
--
architecture dual_port_ram_arq of dual_port_ram is

  signal clk_signal : std_logic := '0';

  signal read_enable_0 : std_logic := '0';
  signal write_enable_0 : std_logic := '0';
  signal read_enable_1 : std_logic := '0';
  signal write_enable_1 : std_logic := '0';
  signal read_enable_2 : std_logic := '0';
  signal write_enable_2 : std_logic := '0';
  signal read_enable_3 : std_logic := '0';
  signal write_enable_3 : std_logic := '0';
  signal read_enable_4 : std_logic := '0';
  signal write_enable_4 : std_logic := '0';
  signal read_enable_5 : std_logic := '0';
  signal write_enable_5 : std_logic := '0';
  signal read_enable_6 : std_logic := '0';
  signal write_enable_6 : std_logic := '0';
  signal read_enable_7 : std_logic := '0';
  signal write_enable_7 : std_logic := '0';

  signal data_out_0 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_1 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_2 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_3 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_4 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_5 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_6 : std_logic_vector(0 downto 0) := (others => '0');
  signal data_out_7 : std_logic_vector(0 downto 0) := (others => '0');


   --Syntax for Synopsys FPGA Express
  component RAMB16_S1_S1
   --pragma translate_off
    -- pragma translate_on
    port(
      DOA  : out std_logic_vector(0 downto 0);
      DOB  : out std_logic_vector(0 downto 0);
      ADDRA : in std_logic_vector(13 downto 0);
      ADDRB : in std_logic_vector(13 downto 0);
      CLKA  : in std_ulogic;
      CLKB  : in std_ulogic;
      DIA   : in std_logic_vector(0 downto 0);
      DIB   : in std_logic_vector(0 downto 0);
      ENA   : in std_ulogic;
      ENB   : in std_ulogic;
      SSRA  : in std_ulogic;
      SSRB  : in std_ulogic;
      WEA   : in std_ulogic;
      WEB   : in std_ulogic
    );
  end component;

  for ram_0 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_1 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_2 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_3 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_4 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_5 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_6 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;
  for ram_7 : RAMB16_S1_S1 use entity unisim.RAMB16_S1_S1;

  --
  begin

    --WRITE ON A READ ON B
    --WRITE ON A READ ON B
    --WRITE ON A READ ON B
    --WRITE ON A READ ON B

    -- Block SelectRAM Instantiation
    ram_0: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_0,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_0,
      ENB  => read_enable_0,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    ram_1: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_1,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_1,
      ENB  => read_enable_1,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    ram_2: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_2,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_2,
      ENB  => read_enable_2,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    ram_3: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_3,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_3,
      ENB  => read_enable_3,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    ram_4: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_4,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_4,
      ENB  => read_enable_4,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );


    ram_5: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_5,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_5,
      ENB  => read_enable_5,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    ram_6: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_6,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_6,
      ENB  => read_enable_6,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    ram_7: RAMB16_S1_S1
    port map (
      DOA  => open,
      DOB  => data_out_7,
      ADDRA => write_address,
      ADDRB => read_address,
      CLKA  => clk_signal,
      CLKB => clk_signal,
      DIA  => data_in,
      DIB  => "0",
      ENA  => write_enable_7,
      ENB  => read_enable_7,
      SSRA  => reset,
      SSRB => reset,
      WEA  => write_enable,
      WEB  => '0'
    );

    read_enable_0 <= enable and ram_read_mask(0);
    write_enable_0 <= enable and ram_write_mask(0);
    read_enable_1 <= enable and ram_read_mask(1);
    write_enable_1 <= enable and ram_write_mask(1);
    read_enable_2 <= enable and ram_read_mask(2);
    write_enable_2 <= enable and ram_write_mask(2);
    read_enable_3 <= enable and ram_read_mask(3);
    write_enable_3 <= enable and ram_write_mask(3);
    read_enable_4 <= enable and ram_read_mask(4);
    write_enable_4 <= enable and ram_write_mask(4);
    read_enable_5 <= enable and ram_read_mask(5);
    write_enable_5 <= enable and ram_write_mask(5);
    read_enable_6 <= enable and ram_read_mask(6);
    write_enable_6 <= enable and ram_write_mask(6);
    read_enable_7 <= enable and ram_read_mask(7);
    write_enable_7 <= enable and ram_write_mask(7);

    data_out(0) <= (data_out_0(0) and ram_read_mask(0)) or (data_out_1(0) and ram_read_mask(1)) or (data_out_2(0) and ram_read_mask(2)) or (data_out_3(0) and ram_read_mask(3)) or (data_out_4(0) and ram_read_mask(4)) or (data_out_5(0) and ram_read_mask(5)) or (data_out_6(0) and ram_read_mask(6)) or (data_out_7(0) and ram_read_mask(7));


--
end dual_port_ram_arq;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dual_port_ram_tb is
end entity;

architecture dual_port_ram_tb_arq of dual_port_ram_tb is

    signal data_in : std_logic_vector (0 downto 0) := (others => '0');
  signal write_address : std_logic_vector (13 downto 0) := (others  => '0');
  signal write_enable : std_logic := '0';
  signal ram_write_mask : std_logic_vector(7 downto 0) := (others => '0');
  signal enable : std_logic := '0';
  signal reset : std_logic := '0';
  signal clk : std_logic := '0';
  signal ram_read_mask : std_logic_vector(7 downto 0) := (others => '0');
  signal read_address : std_logic_vector(13 downto 0) := (others => '0');
  signal data_out : std_logic_vector (0 downto 0) := (others => '0');

    component dual_port_ram is
    port (
    data_in : in std_logic_vector (0 downto 0) := (others => '0');
    write_address : in std_logic_vector (13 downto 0) := (others => '0');
    write_enable : in std_logic := '0';
    ram_write_mask : in std_logic_vector(7 downto 0) := (others => '0');

    enable : in std_logic := '0';
    clk : in std_logic := '0';
    reset : in std_logic := '0';

    ram_read_mask : in std_logic_vector(7 downto 0) := (others => '0');
    read_address : in std_logic_vector(13 downto 0) := (others => '0');
    data_out : out std_logic_vector (0 downto 0) := (others => '0')
  );
    end component;

begin

    dual_port_ram_0 : dual_port_ram
        port map(
            data_in => data_in,
        write_address => write_address,
        write_enable => write_enable,
        ram_write_mask => ram_write_mask,
        enable => enable,
        reset => reset,
        clk => clk,
        ram_read_mask => ram_read_mask,
        read_address => read_address,
        data_out => data_out
        );

    process

        type pattern_type is record
            din : std_logic_vector(0 downto 0);
            wa : std_logic_vector(13 downto 0);
            wen : std_logic;
            rwm : std_logic_vector(7 downto 0);

            rrm : std_logic_vector(7 downto 0);
            ra : std_logic_vector(13 downto 0);
            dot : std_logic_vector(0 downto 0);
        end record;
        --  The patterns to apply.
        type pattern_array is array (natural range <>) of pattern_type;
        constant patterns : pattern_array := (
            ("1",
             "00000000000001",
             '1',
             "00000001",
             "00000000",
             "00000000000000",
             "0"),
            ("0",
             "00000000000000",
             '0',
             "00000000",
             "00000001",
             "00000000000001",
             "1"),
            ("1",
             "00000001000000",
             '1',
             "00010000",
             "00000000",
             "00000000000000",
             "0"),
            ("1",
             "10000000000000",
             '1',
             "10000000",
             "00000000",
             "00000000000000",
             "0"),
            ("0",
             "00000000000000",
             '0',
             "00000000",
             "00010000",
             "00000001000000",
             "1"),
            ("0",
             "00000000000000",
             '0',
             "00000000",
             "10000000",
             "10000000000000",
             "1"),
            ("1",
             "11111111111111",
             '0',
             "11111111",
             "10000000",
             "10000000000000",
             "1")
            );


    begin
        clk <= '0';
        enable <= '1';
        reset <= '0';

        for i in patterns'range loop

            clk <= '0';
            wait for 1 ns;

            --  Set the inputs.
            data_in <= patterns(i).din;
            write_address <= patterns(i).wa;
            write_enable <= patterns(i).wen;
            ram_write_mask <= patterns(i).rwm;
            ram_read_mask <= patterns(i).rrm;
            read_address <= patterns(i).ra;

            clk <= '1';

            wait for 1 ns;

            assert patterns(i).dot = data_out report "BAD SAVED VALUE, EXPECTED: " & std_logic'image(patterns(i).dot(0)) & " GOT: " & std_logic'image(data_out(0));


            --  Check the outputs.
        end loop;
        assert false report "end of test" severity note;
        wait;
    end process;
end;

process(data_in, clk, enable,read_address, write_address, write_enable)
begin
   clk_signal <= clk;
end process;