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Jan 7th, 2020
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  1. ++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
  2.  
  3. Path Begin : hyper_xface_0/addr_sr_reg[2].ff_inst/Q (SLICE_R41C55C)
  4. Path End : hyper_xface_0/addr_sr_reg[10].ff_inst/DF (SLICE_R41C55B)
  5. Source Clock : clk
  6. Destination Clock: clk
  7. Logic Level : 1
  8. Delay Ratio : 37.8% (route), 62.2% (logic)
  9. Clock Skew : 0.340 ns
  10. Hold Constraint : 0.000 ns
  11. Path Slack : -0.146 ns (Failed)
  12.  
  13.  
  14. Name Cell/Site Name Delay Name Delay Arrival Time Fanout
  15. ---------------------------------------- ---------------- ------------- ------ ------------ ------
  16. pll_I.lscc_pll_inst.u0_PLL.PLL_inst/CLKOP
  17. PLL_CORE_PLL_LLC CLOCK LATENCY -1.206 -1.206 514
  18. pll_I/lscc_pll_inst/clk NET DELAY 1.407 0.201 1
  19.  
  20.  
  21.  
  22.  
  23. hyper_xface_0/addr_sr_reg[2].ff_inst/CLK->hyper_xface_0/addr_sr_reg[2].ff_inst/Q
  24. SLICE_R41C55C REG_DEL 0.186 0.387 1
  25. hyper_xface_0/addr_sr[2] ( M0 ) NET DELAY 0.113 0.500 1
  26.  
  27.  
  28.  
  29.  
  30. CONSTRAINT 0.000 0.000 1
  31. pll_I.lscc_pll_inst.u0_PLL.PLL_inst/CLKOP
  32. PLL_CORE_PLL_LLC CLOCK LATENCY -1.011 -1.011 514
  33. pll_I/lscc_pll_inst/clk ( CLK ) NET DELAY 1.552 0.541 1
  34. Uncertainty 0.000 0.541
  35. Hold time 0.105 0.646
  36. ---------------------------------------- ---------------- ------------- ------ ------------ ------
  37. Required Time -0.646
  38. Arrival Time 0.500
  39. ---------------------------------------- ---------------- ------------- ------ ------------ ------
  40. Path Slack (Failed) -0.146
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