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- ++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
- Path Begin : hyper_xface_0/addr_sr_reg[2].ff_inst/Q (SLICE_R41C55C)
- Path End : hyper_xface_0/addr_sr_reg[10].ff_inst/DF (SLICE_R41C55B)
- Source Clock : clk
- Destination Clock: clk
- Logic Level : 1
- Delay Ratio : 37.8% (route), 62.2% (logic)
- Clock Skew : 0.340 ns
- Hold Constraint : 0.000 ns
- Path Slack : -0.146 ns (Failed)
- Name Cell/Site Name Delay Name Delay Arrival Time Fanout
- ---------------------------------------- ---------------- ------------- ------ ------------ ------
- pll_I.lscc_pll_inst.u0_PLL.PLL_inst/CLKOP
- PLL_CORE_PLL_LLC CLOCK LATENCY -1.206 -1.206 514
- pll_I/lscc_pll_inst/clk NET DELAY 1.407 0.201 1
- hyper_xface_0/addr_sr_reg[2].ff_inst/CLK->hyper_xface_0/addr_sr_reg[2].ff_inst/Q
- SLICE_R41C55C REG_DEL 0.186 0.387 1
- hyper_xface_0/addr_sr[2] ( M0 ) NET DELAY 0.113 0.500 1
- CONSTRAINT 0.000 0.000 1
- pll_I.lscc_pll_inst.u0_PLL.PLL_inst/CLKOP
- PLL_CORE_PLL_LLC CLOCK LATENCY -1.011 -1.011 514
- pll_I/lscc_pll_inst/clk ( CLK ) NET DELAY 1.552 0.541 1
- Uncertainty 0.000 0.541
- Hold time 0.105 0.646
- ---------------------------------------- ---------------- ------------- ------ ------------ ------
- Required Time -0.646
- Arrival Time 0.500
- ---------------------------------------- ---------------- ------------- ------ ------------ ------
- Path Slack (Failed) -0.146
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