SIG_4 ( LSFR_4 + GR10 + SISR_4)

module d_ff // D flip flop
  (
  input d, rst_b, set_b, clk,
  output reg q

  );

always @ (posedge clk, negedge rst_b, negedge set_b)
  begin
    if(rst_b == 0)
      q <= 1'd0;
    else if(set_b == 0)
     q <= 1'd1;
    else
     q <= d;
  end

endmodule
//-----------------------------------------------------------
module lsfr_4
  (
  input clk, rst_b,
  output  [3:0] q
  );



  d_ff a
  (
  .d(q[3]),
  .rst_b(1'd1), //rst_b este legat la 1
  .set_b(rst_b), //set_b este legat la rst_b
  .clk(clk),
  .q(q[0])
  );

  d_ff b
  (
  .d(q[3]^q[0]),
  .rst_b(1'd1),
  .set_b(rst_b),
  .clk(clk),
  .q(q[1])
  );

  d_ff c
  (
  .d(q[1]),
  .rst_b(1'd1),
  .set_b(rst_b),
  .clk(clk),
  .q(q[2])
  );

  d_ff d
  (
  .d(q[2]),
  .rst_b(1'd1),
  .set_b(rst_b),
  .clk(clk),
  .q(q[3])
  );

endmodule

//----------------------------------------------------------------

module sisr_4 //week 10 pag 9
  (
  input i,
  input clk, rst_b,
  output  [3:0] q
  );



  d_ff e
  (
  .d(q[3] ^ i),
  .rst_b(rst_b), //rst_b este legat la 1
  .set_b(1'd1), //set_b este legat la rst_b
  .clk(clk),
  .q(q[0])
  );

  d_ff f
  (
  .d(q[3]^q[0]),
  .rst_b(rst_b),
  .set_b(1'd1),
  .clk(clk),
  .q(q[1])
  );

  d_ff g
  (
  .d(q[1]),
  .rst_b(rst_b),
  .set_b(1'd1),
  .clk(clk),
  .q(q[2])
  );

  d_ff h
  (
  .d(q[2]),
  .rst_b(rst_b),
  .set_b(1'd1),
  .clk(clk),
  .q(q[3])
  );

endmodule
//------------------------------------------------------------

module gr10
  (
  input [3:0] i,
  output reg o
  );
  always @(*) begin
  if((i[3] && i[2]) || (i[3] && i[2]))
    assign o = 1'd1;
  else
    assign o = 1'd0;
  end
endmodule
//----------------------------------------------------------

module sig_4
(
input clk, rst_b,
output [3:0] sig
);
wire [3:0] f;
wire g;
lsfr_4 component1
(
.clk(clk),
.rst_b(rst_b),
.q(f)
);

gr10 component2
(
.i(f),
.o(g)
);

sisr_4 component3
(
.i(g),
.clk(clk),
.rst_b(rst_b),
.q(sig)
);

endmodule

module sig_4_tb
  (
  output reg clk, rst_b,
  output [3:0] sig
  );

  sig_4 test
  (
  .clk(clk),
  .rst_b(rst_b),
  .sig(sig)
  );

  initial begin
    clk = 1'd0;
    repeat (32)
      #25 clk = ~clk;
  end

  initial begin
    rst_b = 1'd0;
    #5 rst_b = 1'd1;
  end
endmodule