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emin_int11

AMD

emin_int11
Mar 7th, 2016
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  1. Memory
  2. |
  3. |
  4. ↓
  5. -----------------------------------------------------------------------
  6. | L2 |
  7. -----------------------------------------------------------------------
  8. ↑ ↑ ↑ ↑ ↑ ↑
  9. | | | | | |
  10. | | | | | |
  11. ↓ ↓ | ↓ | |
  12. ------------- -------------- | ------------- | |
  13. | L1 instr | | L2 ITLB | | | L2 DTLB | | |
  14. |cache 64 kb| |512 entries | | |512 entries| | |
  15. ------------- -------------- | ------------- | |
  16. ↑ | ↑ | |
  17. | | | | |
  18. ↓ ↓ ↓ ↓ ↓
  19. ----------------------- ----------------------- ------------------
  20. | L1 ITLB | | L1 DTLB | | L1 Data Cache |
  21. |---------------------- |---------------------- | 64KB |
  22. | 4kB |4/2 MB | | 4KB |4/2 MB | ------------------
  23. |32 entries|8 entries | |32 entries|8 entries |
  24. |full assoc|full assoc| |full assoc|full assoc|
  25. ----------------------- -----------------------
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