U-Boot 2012.10 (Mar 28 2021 - 23:36:32)Meraki MX64 Boot Kernel Loader

DEV ID = 0xcf1e
PCIE CFG DEV ID = 0x8025
OTP offset(0x8): 0x78f01c01
OTP offset(0x9): 0xfe200818
OTP offset(0xa): 0xc01b0
OTP offset(0xb): 0x0
OTP offset(0xc): 0x4a00000
OTP offset(0xd): 0xffede230
OTP offset(0xe): 0x1035d17f
OTP offset(0xf): 0x4000
NSP25 32bit DDR
SKU ID = 0x0
DDR type: DDR3
MEMC 0 DDR speed = 800MHz
ddr_init2: Calling soc_ddr40_set_shmoo_dram_config
ddr_init2: Calling soc_ddr40_phy_calibrate
C01. Check Power Up Reset_Bar
C02. Config and Release PLL from reset
C03. Poll PLL Lock
C04. Calibrate ZQ (ddr40_phy_calib_zq)
C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT
C06. DDR40_PHY_DDR3_MISC
C07. VDL Calibration
C07.1
C07.2
C07.4
C07.4.1
C07.4.4
VDL calibration result: 0x30000003 (cal_steps = 0)
C07.4.5
C07.4.6
C07.5
C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....
C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....
C10. Wait for Phy Ready
Programming controller register
ddr_init2: Calling soc_ddr40_shmoo_ctl
Validate Shmoo parameters stored in flash ..... OK
Press Ctrl-C to run Shmoo ..... skipped
Restoring Shmoo parameters from flash ..... done
Running simple memory test ..... OK
DDR Tune Completed
DRAM:  31.9 MiB
WARNING: Caches not enabled
NAND:   Micron MT29F8G08ABACA,