Advertisement
Guest User

Untitled

a guest
Jan 9th, 2022
54
Never
Not a member of Pastebin yet? Sign Up, it unlocks many cool features!
  1. U-Boot 2012.10 (Mar 28 2021 - 23:36:32)Meraki MX64 Boot Kernel Loader
  2.  
  3. DEV ID = 0xcf1e
  4. PCIE CFG DEV ID = 0x8025
  5. OTP offset(0x8): 0x78f01c01
  6. OTP offset(0x9): 0xfe200818
  7. OTP offset(0xa): 0xc01b0
  8. OTP offset(0xb): 0x0
  9. OTP offset(0xc): 0x4a00000
  10. OTP offset(0xd): 0xffede230
  11. OTP offset(0xe): 0x1035d17f
  12. OTP offset(0xf): 0x4000
  13. NSP25 32bit DDR
  14. SKU ID = 0x0
  15. DDR type: DDR3
  16. MEMC 0 DDR speed = 800MHz
  17. ddr_init2: Calling soc_ddr40_set_shmoo_dram_config
  18. ddr_init2: Calling soc_ddr40_phy_calibrate
  19. C01. Check Power Up Reset_Bar
  20. C02. Config and Release PLL from reset
  21. C03. Poll PLL Lock
  22. C04. Calibrate ZQ (ddr40_phy_calib_zq)
  23. C05. DDR PHY VTT On (Virtual VTT setup) DISABLE all Virtual VTT
  24. C06. DDR40_PHY_DDR3_MISC
  25. C07. VDL Calibration
  26. C07.1
  27. C07.2
  28. C07.4
  29. C07.4.1
  30. C07.4.4
  31. VDL calibration result: 0x30000003 (cal_steps = 0)
  32. C07.4.5
  33. C07.4.6
  34. C07.5
  35. C08. DDR40_PHY_DDR3_MISC : Start DDR40_PHY_RDLY_ODT....
  36. C09. Start ddr40_phy_autoidle_on (MEM_SYS_PARAM_PHY_AUTO_IDLE) ....
  37. C10. Wait for Phy Ready
  38. Programming controller register
  39. ddr_init2: Calling soc_ddr40_shmoo_ctl
  40. Validate Shmoo parameters stored in flash ..... OK
  41. Press Ctrl-C to run Shmoo ..... skipped
  42. Restoring Shmoo parameters from flash ..... done
  43. Running simple memory test ..... OK
  44. DDR Tune Completed
  45. DRAM: 31.9 MiB
  46. WARNING: Caches not enabled
  47. NAND: Micron MT29F8G08ABACA,
  48.  
Advertisement
RAW Paste Data Copied
Advertisement