module Controle(input wire [5:0] Opcode,
input wire [5:0] func,
input wire [0:0] clk,
output reg [0:0] PCWrite,
output reg [0:0] PCWriteCond,
output reg [1:0] PCWriteCondMux,
output reg [2:0] MuxBranch,
output reg [2:0] MuxMemoriaEnd,
output reg [0:0] IRWrite,
output reg [0:0] RegWrite,
output reg [1:0] RegDst,
output reg [2:0] MuxULA1,
output reg [2:0] ALUControl,
output reg [0:0] ALUOutControl,
output reg [0:0] DivControl,
output reg [2:0] MuxULA2,
output reg [1:0] MuxMemoriaDado,
output reg [0:0] AControl,
output reg [0:0] BControl,
output reg [0:0] EPCCont,
output reg [0:0] MultControl,
output reg [2:0] RDControl,
output reg [0:0] MuxRD,
output reg [0:0] MuxSaidaLO,
output reg [0:0] MuxSaidaHI,
output reg [1:0] ContShifts,
output reg [3:0] MuxWriteData,
output reg [0:0] MuxHILO,
output reg [0:0] LuiControl,
output reg [0:0] MuxMDR,
output reg [2:0] ControleBits,
output reg [0:0] CHi,
output reg [0:0] CLo,
output reg [0:0] MemRead,
output reg [0:0] MDRControl);

reg [31:0] state;

parameter TipoR = 32'd07;
parameter Add = 32'd32;
parameter Sub = 32'd34;
parameter Addi = 32'd8;
parameter Addi1 = 32'd9;
parameter Addi2 = 32'd10;
parameter Addi3 = 32'd11;
parameter Add1 = 32'd09;

	always @(posedge clk)begin

			case(state)
				//RESET
				32'd0:
				begin
					state <= 32'd1;
				end

				32'd1:
				begin
					RegDst <= 2'b11;
					RegWrite <= 1'd1;
					MuxWriteData <= 4'b1000;
					state <= 32'd2;
				end

				32'd2:
				begin
					RegWrite <= 1'd0;
					state <= 32'd3;
				end
				//PC+4
				32'd3:
				begin
					MuxULA1 <= 3'b000;
					MuxULA2 <= 3'b001;
					MuxMemoriaEnd <= 3'b000;
					ALUControl <= 3'b001;
					MemRead <= 1'b0;
					state <= 32'd4;
				end

				32'd4:
				begin
					MuxBranch <= 2'b00;
					PCWrite <= 1'b1;
					state <= 32'd5;
				end

				32'd5:
				begin
					PCWrite <= 1'b0;
					state <= 32'd6;
				end

				32'd6:
				begin
					IRWrite <= 1'b1;
					state <= 32'd7;
				end
				32'd7:
				begin
					case(Opcode)
						TipoR:
						begin
							case(func)
							//ADD
								Add:
								begin
									RegWrite <= 1'b0;
									state <= Add1;
								end
							//SUB
							endcase
						end
						//ADDI
						Addi:
						begin
							state <= Addi;
						end
					endcase
				end
				Addi:
				begin
					AControl <= 1'b1;
					MuxULA1 <= 3'b100;
					MuxULA2 <= 3'b010;
					ALUControl <= 3'b001;
					ALUOutControl <= 1'b1;
					state <= 32'd7;
				end
				Addi2:
				begin
					MuxWriteData <= 3'b000;
					RegWrite <= 1'b1;
					ALUOutControl <= 1'b0;
					RegDst <= 2'b01;
					AControl <= 1'b0;
					BControl <= 1'b0;
					state <= Addi3;
				end
				Addi3:
				begin
					RegWrite <= 1'b0;
					state <= 32'd3;
				end
			endcase
		end
endmodule