unit2

Unit 2

The ARM architecture
ARM (Advance RISC Machines)
	Is the most widely used 32-bit RISC instruction set architecture. The relative simplicity makes it suitable for low power devices. Used extensively in consumer electronics, mobile phones, hand held game consoles, calculators etc.
ARM design philosophy:
-Small processor for lower power consumption (for embedded systems)
-High code density for limited memory and physical size restrictions
-The ability to use show and low-cost memory
-Reduced die size for reducing manufacture cost and accommodating more peripherals
Fixed length 32-bit architecture
Processor can run in either ARM state or in Thumb state.
Instruction Set of most ARMs:
ARM state : all instructions are 32 bits wide, all instructions must be word aligned (32 bits or 4 bytes)
Thumb state: all instructions are 16 bits wide, all instructions must be half word aligned (16 bits or 2 bytes)
	Processor Modes
-User: The only non-privileged mode.
-FIQ: entered when a high priority (fast) interrupt is raised
-IRQ: entered when a low priority (normal) interrupt is raised
-Supervisor: entered on reset and when a software interrupt instruction is executed
-Abort: used to handle memory access violations
-Undefined: used to handle undefined instructions
-System: priviledged mode using the same registers as user mode
	Features of the ARM Instruction Set:
-LOAD/STORE architecture
-Conditional execution of every instruction
-Load and store multiple register
-Very dense 16-bit compressed instruction set (Thumb)
	Pipelining: Initially implemented a 3 stage pipeline organization (up to ARM7):
Fetch-Decode-Execute
The drawback is that every data transfer instruction causes a pipeline “stall”.
5-stage Pipeline Organization (implemented in ARM9TDMI)
-Fetch: the instruction is fetched from the memory and placed in the instruction pipeline
-Decode: the instruction is decoded and register operands read from the register files
-Execute: An operand is shifted and the ALU result generated.
-Buffer/Data: Data memory is accessed if required. Otherwise the ALU is simply buffered for one cycle.
-Write back: the results generated by the instruction are written back to the register file, including any data loaded from memory.
Results: better balance pipeline with minimized latencies between stages, which can run at faster clock speed.
Regarding Structural Hazards (some combinations of instruction cannot be accommodated because of resource conflict) is using separate instruction and data memories. ARM has moved from the von-Neumann architecture to the Harvard architecture in ARM9 (implemented 5-stage pipleline and separate data and instruction memory).
	Little/Big Endian: ARM can be set up to access data in either little-endian or big-endian forma, default to little-endian
	Coprocessors:
Up to 16 coprocessors can be defined. Expands the ARM instruction set.