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Apr 13th, 2014
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  1. /* Lighweight arbiter between instruction and data busses going
  2.     into the cellram controller */
  3. reg [9:0] cellram_arb_timeout;
  4.  
  5. always @(posedge wb_clk)
  6.  if (wb_rst)
  7.    cellram_arb_timeout <= 0;
  8.  else if (wb_s2m_mem_ack)
  9.    cellram_arb_timeout <= 0;
  10.  else if (wb_m2s_mem_stb & wb_m2s_mem_cyc)
  11.    cellram_arb_timeout <= cellram_arb_timeout + 1;
  12.  
  13. assign cellram_arb_reset = (&cellram_arb_timeout);
  14.  
  15. cellram_ctrl
  16.  /* Use the simple flash interface */
  17.  #(
  18.    .cellram_read_cycles(11), // 70ns in cycles, at 100MHz = 7 (70 ns)
  19.    .cellram_write_cycles(11)) // 70ns in cycles, at 100Mhz = 7 (70 ns)
  20.  cellram_ctrl0
  21.  (
  22.   .wb_clk_i(wb_clk),
  23.   .wb_rst_i(wb_rst | cellram_arb_reset),
  24.  
  25.   .wb_adr_i(wb_m2s_mem_adr),
  26.   .wb_dat_i(wb_m2s_mem_dat),
  27.   .wb_stb_i(wb_m2s_mem_stb),
  28.   .wb_cyc_i(wb_m2s_mem_cyc),
  29.   .wb_we_i (wb_m2s_mem_we ),
  30.   .wb_sel_i(wb_m2s_mem_sel),
  31.   .wb_dat_o(wb_s2m_mem_dat),
  32.   .wb_ack_o(wb_s2m_mem_ack),
  33.   .wb_err_o(wb_s2m_mem_err),
  34.   .wb_rty_o(wb_s2m_mem_rty),
  35.  
  36.   .cellram_dq_io(cellram_data_io),
  37.   .cellram_adr_o(cellram_adr_o),
  38.   .cellram_adv_n_o(cellram_adv_n_o),
  39.   .cellram_ce_n_o(cellram_ce_n_o),
  40.   .cellram_clk_o(cellram_clk_o),
  41.   .cellram_oe_n_o(cellram_oe_n_o),
  42.   .cellram_rst_n_o(),
  43.   .cellram_wait_i(cellram_wait_i),
  44.   .cellram_we_n_o(cellram_we_n_o),
  45.   .cellram_wp_n_o(),
  46.   .cellram_lb_n_o(cellram_lb_n_o),
  47.   .cellram_ub_n_o(cellram_ub_n_o),
  48.   .cellram_cre_o(cellram_cre_o)
  49.   );
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