[14:03:10:308] <break>
[14:03:10:308] <break>
[14:03:18:217] <break>
[14:03:18:806] ␍␊
[14:03:18:806] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:18:841] DRAM:PLL = b0003600␍␊
[14:03:18:841] DRAM PHY PGSR0 = 20003d␍␊
[14:03:18:841] DRAM PHY DX0RSR0 = 0␍␊
[14:03:18:841] DRAM PHY DX1RSR0 = 0␍␊
[14:03:18:841] DRAM PHY DX2RSR0 = 0␍␊
[14:03:18:841] DRAM PHY DX3RSR0 = 0␍␊
[14:03:18:841] Error while initializing DRAM PHY!␍␊
[14:03:18:841] ␍␊
[14:03:18:926] resetting ...␍␊
[14:03:19:537] ␍␊
[14:03:19:537] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:19:547] DRAM:PLL = b0003600␍␊
[14:03:19:547] DRAM PHY PGSR0 = 20003d␍␊
[14:03:19:547] DRAM PHY DX0RSR0 = 0␍␊
[14:03:19:550] DRAM PHY DX1RSR0 = 0␍␊
[14:03:19:551] DRAM PHY DX2RSR0 = 0␍␊
[14:03:19:553] DRAM PHY DX3RSR0 = 0␍␊
[14:03:19:555] Error while initializing DRAM PHY!␍␊
[14:03:19:557] ␍␊
[14:03:19:657] resetting ...␍␊
[14:03:20:268] ␍␊
[14:03:20:268] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:20:273] DRAM:PLL = b0003600␍␊
[14:03:20:282] DRAM PHY PGSR0 = 20003d␍␊
[14:03:20:282] DRAM PHY DX0RSR0 = 0␍␊
[14:03:20:282] DRAM PHY DX1RSR0 = 0␍␊
[14:03:20:282] DRAM PHY DX2RSR0 = 0␍␊
[14:03:20:288] DRAM PHY DX3RSR0 = 0␍␊
[14:03:20:288] Error while initializing DRAM PHY!␍␊
[14:03:20:294] ␍␊
[14:03:20:388] resetting ...␍␊
[14:03:20:998] ␍␊
[14:03:21:008] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:21:008] DRAM:PLL = b0003600␍␊
[14:03:21:008] DRAM PHY PGSR0 = 20003d␍␊
[14:03:21:019] DRAM PHY DX0RSR0 = 0␍␊
[14:03:21:019] DRAM PHY DX1RSR0 = 0␍␊
[14:03:21:019] DRAM PHY DX2RSR0 = 0␍␊
[14:03:21:019] DRAM PHY DX3RSR0 = 0␍␊
[14:03:21:019] Error while initializing DRAM PHY!␍␊
[14:03:21:019] ␍␊
[14:03:21:119] resetting ...␍␊
[14:03:21:729] ␍␊
[14:03:21:738] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:21:738] DRAM:PLL = b0003600␍␊
[14:03:21:738] DRAM PHY PGSR0 = 20003d␍␊
[14:03:21:742] DRAM PHY DX0RSR0 = 0␍␊
[14:03:21:742] DRAM PHY DX1RSR0 = 0␍␊
[14:03:21:746] DRAM PHY DX2RSR0 = 0␍␊
[14:03:21:746] DRAM PHY DX3RSR0 = 0␍␊
[14:03:21:750] Error while initializing DRAM PHY!␍␊
[14:03:21:750] ␍␊
[14:03:21:850] resetting ...␍␊
[14:03:22:460] ␍␊
[14:03:22:469] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:22:469] DRAM:PLL = b0003600␍␊
[14:03:22:469] DRAM PHY PGSR0 = 20003d␍␊
[14:03:22:472] DRAM PHY DX0RSR0 = 0␍␊
[14:03:22:472] DRAM PHY DX1RSR0 = 0␍␊
[14:03:22:477] DRAM PHY DX2RSR0 = 0␍␊
[14:03:22:477] DRAM PHY DX3RSR0 = 0␍␊
[14:03:22:482] Error while initializing DRAM PHY!␍␊
[14:03:22:482] ␍␊
[14:03:22:581] resetting ...␍␊
[14:03:23:192] ␍␊
[14:03:23:200] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:23:200] DRAM:PLL = b0003600␍␊
[14:03:23:200] DRAM PHY PGSR0 = 20003d␍␊
[14:03:23:204] DRAM PHY DX0RSR0 = 0␍␊
[14:03:23:204] DRAM PHY DX1RSR0 = 0␍␊
[14:03:23:209] DRAM PHY DX2RSR0 = 0␍␊
[14:03:23:209] DRAM PHY DX3RSR0 = 0␍␊
[14:03:23:209] Error while initializing DRAM PHY!␍␊
[14:03:23:213] ␍␊
[14:03:23:312] resetting ...␍␊
[14:03:23:922] ␍␊
[14:03:23:931] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:23:931] DRAM:PLL = b0003600␍␊
[14:03:23:931] DRAM PHY PGSR0 = 20003d␍␊
[14:03:23:935] DRAM PHY DX0RSR0 = 0␍␊
[14:03:23:935] DRAM PHY DX1RSR0 = 0␍␊
[14:03:23:940] DRAM PHY DX2RSR0 = 0␍␊
[14:03:23:940] DRAM PHY DX3RSR0 = 0␍␊
[14:03:23:940] Error while initializing DRAM PHY!␍␊
[14:03:23:944] ␍␊
[14:03:24:043] resetting ...␍␊
[14:03:24:653] ␍␊
[14:03:24:653] U-Boot SPL 2019.10 (Mar 09 2020 - 10:02:35 +0100)␍␊
[14:03:24:662] DRAM:PLL = b0003600␍␊
[14:03:24:662] DRAM PHY PGSR0 = 20003d␍␊
[14:03:24:666] DRAM PHY DX0RSR0 = 0␍␊
[14:03:24:666] DRAM PHY DX1RSR0 = 0␍␊
[14:03:24:671] DRAM PHY DX2RSR0 = 0␍␊
[14:03:24:671] DRAM PHY DX3RSR0 = 0␍␊
[14:03:24:671] Error while initializing DRAM PHY!␍␊
[14:03:24:675] ␍␊
[14:03:24:774] resetting ...␍␊
[14:03:25:078] <break>