LAB3 CN 07.03.2019

hello_world.v////////////////////////////////////////////////////////////////////////////////////////////////

module hello_world;

initial begin
    $display ("Hello_world!");
    #10 $finish;
end

endmodule


and_from_nand_gates.v////////////////////////////////////////////////////////////////////////////////////////////////
module NAND (in1, in2, out);

input in1, in2;
output out;

assign out= ~(in1 & in2);

endmodule

module AND (in1, in2, out);

input in1, in2;
output out;
wire w1;

NAND NAND1 (in1, in2, w1);
NAND NAND2 (w1, w1, out);

endmodule

module Testbench;
reg a, b;
wire out1, out2;

initial begin

a=0; b=0;
#1 a=1;
#1 b=1;
#1 a=0;

end

initial begin
$monitor ("Time=%0d a=%b out1=%b out2=%b", $time, a,b, out1, out2);
end

//instantele modulelor AND si NAND
AND and_gate(a, b, out1);
NAND nand_gate(a, b, out2);

endmodule




4bit_adder.v////////////////////////////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module Adder(A, B, Result);

    input [3:0] A;
    input [3:0] B;
    output [3:0] Result;
    reg [3:0] Result;

    always @ (A or B)
    begin

        Result <= A + B;
    end

endmodule

module Testbench;

    reg [3:0] A_t;
    reg [3:0] B_t;
    wire [3:0] Result_t;

    Adder Adder_1(A_t, B_t, Result_t);

    initial
    begin

        //case 0
        A_t <= 0; B_t <= 0;
        #1 $display("Result_t = %b", Result_t);

        //case 1
        A_t <= 6; B_t <= 1;
        #1 $display("Result_t = %b", Result_t);

        //case 2
        A_t <= 1; B_t <= 0;
        #1 $display("Result_t = %b", Result_t);

        //case 3 (overflow should occur)
        A_t <= 10; B_t <= 10;
        #1 $display("Result_t = %b", Result_t);

    end
endmodule