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Outfox Semiconductor FPGA Source Code
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- On lines 7 through 11, change:
- Module MyLogicBlock(Side0, Side1, Side2, Side3);
- Inout wire [6:0] Side0;
- Inout wire [6:0] Side1;
- Inout wire [6:0] Side2;
- Inout wire [6:0] Side3;
- to
- module MyLogicBlock(Side0, Side1, Side2, Side3);
- inout wire [6:0] Side0;
- inout wire [6:0] Side1;
- inout wire [6:0] Side2;
- inout wire [6:0] Side3;
- For it to synthesize.
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