LAB3 - Calc Numerice

module NAND(in1, in2, out);

input in1, in2;
output out;

assign out = ~(in1 & in2);

endmodule

module AND(in1, in2, out);

input in1, in2;
output out;
wire w1;

NAND NAND1(in1, in2, w1);
NAND NAND2(w1, w1, out);

endmodule

module Testbench;
reg a,b;

wire out1, out2;
initial begin
      a=0; b=0;
      #1 a=1 ;
      #1 b=1 ;
      #1 a=0 ;
end

initial begin

$monitor( "Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2);
end

AND and_gate(a,b,out1);
NAND nand_gate(a,b,out2);
endmodule




ADUNARE

module Adder(A,B,Result);

  input [3:0] A;
  input [3:0] B;
  output [3:0] Result;
  reg [3:0] Result;

  always @(A or B)
  begin
    Result <= A+B;
  end

endmodule

module Testbench;

  reg [3:0] A_t;
  reg [3:0] B_t;
  wire [3:0] Result_t;

  Adder Adder_1(A_t, B_t, Result_t);

  initial
  begin
    //case 0
    A_t <= 0; B_t <=0;
    #1 $display("Result_t=%b", Result_t);

    //case 1

    A_t <= 0; B_t <= 1;
    #1 $display("Result_t=%b", Result_t);

    //case 2
    A_t <=  1; B_t <= 0;
    #1 $display("Result_t=%b", Result_t);

    //case 3

    A_t <= 10; B_t <= 10;
    #1 $display("Result_t=%b", Result_t);
    end

   endmodule


DECODER 2X4


module Decoder(A, B, D);

  input A, B;
  output [3:0] D;
  reg [3:0] D;

  always @(A or B)

  begin
    if( A == 0 && B == 0)
      D <= 4'b0001;

    else if ( A == 0 && B == 1 )
      D <= 4'b0010;

    else if ( A == 1 && B == 0 )
      D <= 4'b0100;

    else if ( A == 1 && B == 1)
      D <= 4'b1000;   //nr binar realizat pe 4 biti
    end
endmodule

module Testbench;

reg A_t;
  reg B_t;
  wire [3:0] D_t;

  Decoder Decoder_1(A_t, B_t, D_t);

  initial
  begin
    //case 0
    A_t <= 0; B_t <=0;
    #1 $display("D_t=%b", D_t);

    //case 1

    A_t <= 0; B_t <= 1;
    #1 $display("D_t=%b", D_t);

    //case 2
    A_t <=  1; B_t <= 0;
    #1 $display("D_t=%b", D_t);

    //case 3

    A_t <= 1; B_t <= 1;
    #1 $display("D_t=%b", D_t);
    end

   endmodule



HALF ADDER


module XOR(A,B,S);
    input A, B;
    output reg S;

    always @(A or B)
    begin
      S = A^B;
    end
    endmodule

    module AND(A,B,S);
    input A,B;
    output reg S;

    always @(A or B)
    begin
        S = A&B;
    end
endmodule

module half_adder;

      reg A,B;
      output S,C;

      XOR myXOR(A,B,S);
      AND myAND(A,B,C);

      initial
      begin
    A = 0;
    B = 0;
    #1 $display("S=%b, C=%b\n", S, C);

    A = 0;
    B = 1;
    #1 $display("S=%b, C=%b\n", S, C);

    A=1;
    B=0;
    #1 $display("S=%b, C=%b\n", S, C);

    A=1;
    B=1;
    #1 $display("S=%b, C=%b\n", S, C);

end
endmodule