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Sep 23rd, 2017
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  1. diff --git a/rtl/tf530ram/tf530_ram.v b/rtl/tf530ram/tf530_ram.v
  2. index ce97d79..4e27cfd 100644
  3. --- a/rtl/tf530ram/tf530_ram.v
  4. +++ b/rtl/tf530ram/tf530_ram.v
  5. @@ -64,7 +64,7 @@ reg STERM_D = 1'b1;
  6.  
  7.  wire BUS_CYCLE = (~DS20_D | DS20);
  8.  
  9. -reg configured = 'b0;
  10. +reg configured = 'b1;
  11.  reg shutup = 'b0;
  12.  reg [7:0] data_out = 'h00;
  13.  reg [7:0] base = 'h40;
  14. @@ -102,7 +102,7 @@ wire Z2_ACCESS = ({A[23:16]} != {8'hE8}) | AS20 | DS20 | shutup | configured;
  15.  wire Z2_READ =  (Z2_ACCESS | ~RW20);
  16.  wire Z2_WRITE = (Z2_ACCESS | RW20);
  17.  
  18. -wire RAM_ACCESS = ({A[23:21]} != {base[7:5]}) | AS20 | DS20 | ~configured;
  19. +wire RAM_ACCESS = ({A[23:21]} != {3'b110} | AS20 | DS20 | ~configured;
  20.  wire [6:0] zaddr = {AB[7:2],A1};
  21.  
  22.  always @(posedge CLKCPU) begin
  23. @@ -112,7 +112,7 @@ always @(posedge CLKCPU) begin
  24.      STERM_D <=  INTCYCLE | ~STERM_D;
  25.  
  26.      if (RESET == 1'b0) begin
  27. -        configured <= 1'b0;
  28. +        configured <= 1'b1;
  29.          shutup <= 1'b0;
  30.          STERM_D <= 1'b1;
  31.      end else begin
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