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  1. diff --git a/./mt7986a.dtsi b/./mt7986a_upstream.dtsi
  2. index e292c4f..a03d57d 100755
  3. --- a/./mt7986a.dtsi
  4. +++ b/./mt7986a_upstream.dtsi
  5. @@ -4,19 +4,19 @@
  6. * Author: Sam.Shih <[email protected]>
  7. */
  8.  
  9. -#include <dt-bindings/clock/mt7986-clk.h>
  10. #include <dt-bindings/interrupt-controller/irq.h>
  11. #include <dt-bindings/interrupt-controller/arm-gic.h>
  12. -#include <dt-bindings/phy/phy.h>
  13. +#include <dt-bindings/clock/mt7986-clk.h>
  14. #include <dt-bindings/reset/mt7986-resets.h>
  15. -#include <dt-bindings/thermal/thermal.h>
  16. +#include <dt-bindings/phy/phy.h>
  17.  
  18. / {
  19. + compatible = "mediatek,mt7986a";
  20. interrupt-parent = <&gic>;
  21. #address-cells = <2>;
  22. #size-cells = <2>;
  23.  
  24. - clk40m: oscillator@0 {
  25. + clk40m: oscillator-40m {
  26. compatible = "fixed-clock";
  27. clock-frequency = <40000000>;
  28. #clock-cells = <0>;
  29. @@ -60,22 +60,14 @@
  30. };
  31.  
  32. psci {
  33. - compatible = "arm,psci-0.2";
  34. - method = "smc";
  35. + compatible = "arm,psci-0.2";
  36. + method = "smc";
  37. };
  38.  
  39. reserved-memory {
  40. #address-cells = <2>;
  41. #size-cells = <2>;
  42. ranges;
  43. -
  44. - /* 64 KiB reserved for ramoops/pstore */
  45. - ramoops@42ff0000 {
  46. - compatible = "ramoops";
  47. - reg = <0 0x42ff0000 0 0x10000>;
  48. - record-size = <0x1000>;
  49. - };
  50. -
  51. /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
  52. secmon_reserved: secmon@43000000 {
  53. reg = <0 0x43000000 0 0x30000>;
  54. @@ -86,6 +78,47 @@
  55. no-map;
  56. reg = <0 0x4fc00000 0 0x00100000>;
  57. };
  58. +
  59. + wo_emi0: wo-emi@4fd00000 {
  60. + reg = <0 0x4fd00000 0 0x40000>;
  61. + no-map;
  62. + };
  63. +
  64. + wo_emi1: wo-emi@4fd40000 {
  65. + reg = <0 0x4fd40000 0 0x40000>;
  66. + no-map;
  67. + };
  68. +
  69. + wo_ilm0: wo-ilm@151e0000 {
  70. + reg = <0 0x151e0000 0 0x8000>;
  71. + no-map;
  72. + };
  73. +
  74. + wo_ilm1: wo-ilm@151f0000 {
  75. + reg = <0 0x151f0000 0 0x8000>;
  76. + no-map;
  77. + };
  78. +
  79. + wo_data: wo-data@4fd80000 {
  80. + reg = <0 0x4fd80000 0 0x240000>;
  81. + no-map;
  82. + };
  83. +
  84. + wo_dlm0: wo-dlm@151e8000 {
  85. + reg = <0 0x151e8000 0 0x2000>;
  86. + no-map;
  87. + };
  88. +
  89. + wo_dlm1: wo-dlm@151f8000 {
  90. + reg = <0 0x151f8000 0 0x2000>;
  91. + no-map;
  92. + };
  93. +
  94. + wo_boot: wo-boot@15194000 {
  95. + reg = <0 0x15194000 0 0x1000>;
  96. + no-map;
  97. + };
  98. +
  99. };
  100.  
  101. timer {
  102. @@ -122,6 +155,12 @@
  103. #clock-cells = <1>;
  104. };
  105.  
  106. + wed_pcie: wed-pcie@10003000 {
  107. + compatible = "mediatek,mt7986-wed-pcie",
  108. + "syscon";
  109. + reg = <0 0x10003000 0 0x10>;
  110. + };
  111. +
  112. topckgen: topckgen@1001b000 {
  113. compatible = "mediatek,mt7986-topckgen", "syscon";
  114. reg = <0 0x1001B000 0 0x1000>;
  115. @@ -129,11 +168,17 @@
  116. };
  117.  
  118. watchdog: watchdog@1001c000 {
  119. - compatible = "mediatek,mt7986-wdt",
  120. - "mediatek,mt6589-wdt";
  121. + compatible = "mediatek,mt7986-wdt";
  122. reg = <0 0x1001c000 0 0x1000>;
  123. interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
  124. #reset-cells = <1>;
  125. + status = "disabled";
  126. + };
  127. +
  128. + apmixedsys: apmixedsys@1001e000 {
  129. + compatible = "mediatek,mt7986-apmixedsys";
  130. + reg = <0 0x1001E000 0 0x1000>;
  131. + #clock-cells = <1>;
  132. };
  133.  
  134. pio: pinctrl@1001f000 {
  135. @@ -157,12 +202,6 @@
  136. #interrupt-cells = <2>;
  137. };
  138.  
  139. - apmixedsys: apmixedsys@1001e000 {
  140. - compatible = "mediatek,mt7986-apmixedsys";
  141. - reg = <0 0x1001E000 0 0x1000>;
  142. - #clock-cells = <1>;
  143. - };
  144. -
  145. sgmiisys0: syscon@10060000 {
  146. compatible = "mediatek,mt7986-sgmiisys_0",
  147. "syscon";
  148. @@ -177,12 +216,13 @@
  149. #clock-cells = <1>;
  150. };
  151.  
  152. - trng: trng@1020f000 {
  153. - compatible = "mediatek,mt7986-rng";
  154. + trng: rng@1020f000 {
  155. + compatible = "mediatek,mt7986-rng",
  156. + "mediatek,mt7623-rng";
  157. reg = <0 0x1020f000 0 0x100>;
  158. clocks = <&infracfg CLK_INFRA_TRNG_CK>;
  159. clock-names = "rng";
  160. - status = "okay";
  161. + status = "disabled";
  162. };
  163.  
  164. crypto: crypto@10320000 {
  165. @@ -197,7 +237,7 @@
  166. clock-names = "infra_eip97_ck";
  167. assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
  168. assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
  169. - status = "okay";
  170. + status = "disabled";
  171. };
  172.  
  173. pwm: pwm@10048000 {
  174. @@ -206,7 +246,7 @@
  175. #clock-cells = <1>;
  176. #pwm-cells = <2>;
  177. interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
  178. - clocks = <&infracfg CLK_INFRA_PWM_HCK>,
  179. + clocks = <&topckgen CLK_TOP_PWM_SEL>,
  180. <&infracfg CLK_INFRA_PWM_STA>,
  181. <&infracfg CLK_INFRA_PWM1_CK>,
  182. <&infracfg CLK_INFRA_PWM2_CK>;
  183. @@ -271,6 +311,8 @@
  184.  
  185. spi0: spi@1100a000 {
  186. compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
  187. + #address-cells = <1>;
  188. + #size-cells = <0>;
  189. reg = <0 0x1100a000 0 0x100>;
  190. interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
  191. clocks = <&topckgen CLK_TOP_MPLL_D2>,
  192. @@ -283,6 +325,8 @@
  193.  
  194. spi1: spi@1100b000 {
  195. compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
  196. + #address-cells = <1>;
  197. + #size-cells = <0>;
  198. reg = <0 0x1100b000 0 0x100>;
  199. interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
  200. clocks = <&topckgen CLK_TOP_MPLL_D2>,
  201. @@ -294,13 +338,12 @@
  202. };
  203.  
  204. auxadc: adc@1100d000 {
  205. - compatible = "mediatek,mt7986-auxadc",
  206. - "mediatek,mt7622-auxadc";
  207. + compatible = "mediatek,mt7986-auxadc";
  208. reg = <0 0x1100d000 0 0x1000>;
  209. - clocks = <&infracfg CLK_INFRA_ADC_26M_CK>,
  210. - <&infracfg CLK_INFRA_ADC_FRC_CK>;
  211. - clock-names = "main", "32k";
  212. + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
  213. + clock-names = "main";
  214. #io-channel-cells = <1>;
  215. + status = "disabled";
  216. };
  217.  
  218. ssusb: usb@11200000 {
  219. @@ -311,15 +354,15 @@
  220. reg-names = "mac", "ippc";
  221. interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
  222. clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
  223. - <&topckgen CLK_TOP_U2U3_XHCI_SEL>,
  224. <&infracfg CLK_INFRA_IUSB_CK>,
  225. <&infracfg CLK_INFRA_IUSB_133_CK>,
  226. - <&infracfg CLK_INFRA_IUSB_66M_CK>;
  227. + <&infracfg CLK_INFRA_IUSB_66M_CK>,
  228. + <&topckgen CLK_TOP_U2U3_XHCI_SEL>;
  229. clock-names = "sys_ck",
  230. - "xhci_ck",
  231. "ref_ck",
  232. "mcu_ck",
  233. - "dma_ck";
  234. + "dma_ck",
  235. + "xhci_ck";
  236. phys = <&u2port0 PHY_TYPE_USB2>,
  237. <&u3port0 PHY_TYPE_USB3>,
  238. <&u2port1 PHY_TYPE_USB2>;
  239. @@ -331,15 +374,13 @@
  240. reg = <0 0x11230000 0 0x1000>,
  241. <0 0x11c20000 0 0x1000>;
  242. interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  243. - clocks = <&infracfg CLK_INFRA_MSDC_CK>,
  244. + clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
  245. <&infracfg CLK_INFRA_MSDC_HCK_CK>,
  246. - <&infracfg CLK_INFRA_MSDC_66M_CK>,
  247. - <&infracfg CLK_INFRA_MSDC_133M_CK>;
  248. - clock-names = "source", "hclk", "axi_cg", "ahb_cg";
  249. - assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
  250. - <&topckgen CLK_TOP_EMMC_250M_SEL>;
  251. - assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
  252. - <&topckgen CLK_TOP_NET1PLL_D5_D2>;
  253. + <&infracfg CLK_INFRA_MSDC_CK>,
  254. + <&infracfg CLK_INFRA_MSDC_133M_CK>,
  255. + <&infracfg CLK_INFRA_MSDC_66M_CK>;
  256. + clock-names = "source", "hclk", "source_cg", "bus_clk",
  257. + "sys_cg";
  258. status = "disabled";
  259. };
  260.  
  261. @@ -370,11 +411,11 @@
  262. bus-range = <0x00 0xff>;
  263. ranges = <0x82000000 0x00 0x20000000 0x00
  264. 0x20000000 0x00 0x10000000>;
  265. - clocks = <&infracfg CLK_INFRA_PCIE_SEL>,
  266. + clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
  267. <&infracfg CLK_INFRA_IPCIE_CK>,
  268. - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
  269. <&infracfg CLK_INFRA_IPCIER_CK>,
  270. <&infracfg CLK_INFRA_IPCIEB_CK>;
  271. + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
  272. status = "disabled";
  273.  
  274. phys = <&pcie_port PHY_TYPE_PCIE>;
  275. @@ -395,7 +436,7 @@
  276.  
  277. pcie_phy: t-phy@11c00000 {
  278. compatible = "mediatek,mt7986-tphy",
  279. - "mediatek,generic-tphy-v4";
  280. + "mediatek,generic-tphy-v2";
  281. #address-cells = <2>;
  282. #size-cells = <2>;
  283. ranges;
  284. @@ -406,30 +447,11 @@
  285. clocks = <&clk40m>;
  286. clock-names = "ref";
  287. #phy-cells = <1>;
  288. - auto_load_valid;
  289. - auto_load_valid_ln1;
  290. - nvmem-cells = <&pcie_intr_ln0>,
  291. - <&pcie_rx_imp_ln0>,
  292. - <&pcie_tx_imp_ln0>,
  293. - <&pcie_auto_load_valid_ln0>,
  294. - <&pcie_intr_ln1>,
  295. - <&pcie_rx_imp_ln1>,
  296. - <&pcie_tx_imp_ln1>,
  297. - <&pcie_auto_load_valid_ln1>;
  298. - nvmem-cell-names = "intr",
  299. - "rx_imp",
  300. - "tx_imp",
  301. - "auto_load_valid",
  302. - "intr_ln1",
  303. - "rx_imp_ln1",
  304. - "tx_imp_ln1",
  305. - "auto_load_valid_ln1";
  306. };
  307. };
  308.  
  309. efuse: efuse@11d00000 {
  310. - compatible = "mediatek,mt7986-efuse",
  311. - "mediatek,efuse";
  312. + compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
  313. reg = <0 0x11d00000 0 0x1000>;
  314. #address-cells = <1>;
  315. #size-cells = <1>;
  316. @@ -437,154 +459,61 @@
  317. thermal_calibration: calib@274 {
  318. reg = <0x274 0xc>;
  319. };
  320. -
  321. - comb_auto_load_valid: usb3-alv-imp@8da {
  322. - reg = <0x8da 1>;
  323. - bits = <0 1>;
  324. - };
  325. -
  326. - comb_rx_imp_p0: usb3-rx-imp@8d8 {
  327. - reg = <0x8d8 1>;
  328. - bits = <0 5>;
  329. - };
  330. -
  331. - comb_tx_imp_p0: usb3-tx-imp@8d8 {
  332. - reg = <0x8d8 2>;
  333. - bits = <5 5>;
  334. - };
  335. -
  336. - comb_intr_p0: usb3-intr@8d9 {
  337. - reg = <0x8d9 1>;
  338. - bits = <2 6>;
  339. - };
  340. -
  341. - u2_auto_load_valid_p0: usb2-alv-p0@8e0 {
  342. - reg = <0x8e0 1>;
  343. - bits = <0 1>;
  344. - };
  345. -
  346. - u2_intr_p0: usb2-intr-p0@8e0 {
  347. - reg = <0x8e0 1>;
  348. - bits = <1 5>;
  349. - };
  350. -
  351. - u2_auto_load_valid_p1: usb2-alv-p1@8e0 {
  352. - reg = <0x8e0 2>;
  353. - bits = <6 1>;
  354. - };
  355. -
  356. - u2_intr_p1: usb2-intr-p1@8e0 {
  357. - reg = <0x8e0 2>;
  358. - bits = <7 5>;
  359. - };
  360. -
  361. - pcie_rx_imp_ln0: pcie-rx-imp@8d0 {
  362. - reg = <0x8d0 1>;
  363. - bits = <0 5>;
  364. - };
  365. -
  366. - pcie_tx_imp_ln0: pcie-tx-imp@8d0 {
  367. - reg = <0x8d0 2>;
  368. - bits = <5 5>;
  369. - };
  370. -
  371. - pcie_intr_ln0: pcie-intr@8d1 {
  372. - reg = <0x8d1 1>;
  373. - bits = <2 6>;
  374. - };
  375. -
  376. - pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 {
  377. - reg = <0x8d4 1>;
  378. - bits = <0 1>;
  379. - };
  380. -
  381. - pcie_rx_imp_ln1: pcie-rx-imp@8d2 {
  382. - reg = <0x8d2 1>;
  383. - bits = <0 5>;
  384. - };
  385. -
  386. - pcie_tx_imp_ln1: pcie-tx-imp@8d2 {
  387. - reg = <0x8d2 2>;
  388. - bits = <5 5>;
  389. - };
  390. -
  391. - pcie_intr_ln1: pcie-intr@8d3 {
  392. - reg = <0x8d3 1>;
  393. - bits = <2 6>;
  394. - };
  395. -
  396. - pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 {
  397. - reg = <0x8d4 1>;
  398. - bits = <1 1>;
  399. - };
  400. };
  401.  
  402. usb_phy: t-phy@11e10000 {
  403. compatible = "mediatek,mt7986-tphy",
  404. "mediatek,generic-tphy-v2";
  405. - #address-cells = <2>;
  406. - #size-cells = <2>;
  407. - ranges;
  408. + #address-cells = <1>;
  409. + #size-cells = <1>;
  410. + ranges = <0 0 0x11e10000 0x1700>;
  411. status = "disabled";
  412.  
  413. - u2port0: usb-phy@11e10000 {
  414. - reg = <0 0x11e10000 0 0x700>;
  415. + u2port0: usb-phy@0 {
  416. + reg = <0x0 0x700>;
  417. clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
  418. <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
  419. clock-names = "ref", "da_ref";
  420. #phy-cells = <1>;
  421. - auto_load_valid;
  422. - nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>;
  423. - nvmem-cell-names = "intr", "auto_load_valid";
  424. };
  425.  
  426. - u3port0: usb-phy@11e10700 {
  427. - reg = <0 0x11e10700 0 0x900>;
  428. + u3port0: usb-phy@700 {
  429. + reg = <0x700 0x900>;
  430. clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
  431. clock-names = "ref";
  432. #phy-cells = <1>;
  433. - auto_load_valid;
  434. - nvmem-cells = <&comb_intr_p0>,
  435. - <&comb_rx_imp_p0>,
  436. - <&comb_tx_imp_p0>,
  437. - <&comb_auto_load_valid>;
  438. - nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid";
  439. };
  440.  
  441. - u2port1: usb-phy@11e11000 {
  442. - reg = <0 0x11e11000 0 0x700>;
  443. + u2port1: usb-phy@1000 {
  444. + reg = <0x1000 0x700>;
  445. clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
  446. <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
  447. clock-names = "ref", "da_ref";
  448. #phy-cells = <1>;
  449. - auto_load_valid;
  450. - nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>;
  451. - nvmem-cell-names = "intr", "auto_load_valid";
  452. };
  453. };
  454.  
  455. ethsys: syscon@15000000 {
  456. #address-cells = <1>;
  457. #size-cells = <1>;
  458. - compatible = "mediatek,mt7986-ethsys_ck",
  459. + compatible = "mediatek,mt7986-ethsys",
  460. "syscon";
  461. reg = <0 0x15000000 0 0x1000>;
  462. #clock-cells = <1>;
  463. #reset-cells = <1>;
  464. };
  465.  
  466. - wed_pcie: wed-pcie@10003000 {
  467. - compatible = "mediatek,mt7986-wed-pcie",
  468. - "syscon";
  469. - reg = <0 0x10003000 0 0x10>;
  470. - };
  471. -
  472. wed0: wed@15010000 {
  473. compatible = "mediatek,mt7986-wed",
  474. "syscon";
  475. reg = <0 0x15010000 0 0x1000>;
  476. interrupt-parent = <&gic>;
  477. interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
  478. + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
  479. + <&wo_data>, <&wo_boot>;
  480. + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
  481. + "wo-data", "wo-boot";
  482. + mediatek,wo-ccif = <&wo_ccif0>;
  483. };
  484.  
  485. wed1: wed@15011000 {
  486. @@ -593,6 +522,25 @@
  487. reg = <0 0x15011000 0 0x1000>;
  488. interrupt-parent = <&gic>;
  489. interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
  490. + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
  491. + <&wo_data>, <&wo_boot>;
  492. + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
  493. + "wo-data", "wo-boot";
  494. + mediatek,wo-ccif = <&wo_ccif1>;
  495. + };
  496. +
  497. + wo_ccif0: syscon@151a5000 {
  498. + compatible = "mediatek,mt7986-wo-ccif", "syscon";
  499. + reg = <0 0x151a5000 0 0x1000>;
  500. + interrupt-parent = <&gic>;
  501. + interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
  502. + };
  503. +
  504. + wo_ccif1: syscon@151ad000 {
  505. + compatible = "mediatek,mt7986-wo-ccif", "syscon";
  506. + reg = <0 0x151ad000 0 0x1000>;
  507. + interrupt-parent = <&gic>;
  508. + interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
  509. };
  510.  
  511. eth: ethernet@15100000 {
  512. @@ -637,95 +585,49 @@
  513. status = "disabled";
  514. };
  515.  
  516. - consys: consys@10000000 {
  517. - compatible = "mediatek,mt7986-consys";
  518. - reg = <0 0x10000000 0 0x8600000>;
  519. - memory-region = <&wmcpu_emi>;
  520. - };
  521. -
  522. - wmac: wmac@18000000 {
  523. - compatible = "mediatek,mt7986-wmac", "mediatek,wbsys";
  524. - resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
  525. + wifi: wifi@18000000 {
  526. + compatible = "mediatek,mt7986-wmac";
  527. + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
  528. reset-names = "consys";
  529. + clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
  530. + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
  531. + clock-names = "mcu", "ap2conn";
  532. reg = <0 0x18000000 0 0x1000000>,
  533. <0 0x10003000 0 0x1000>,
  534. <0 0x11d10000 0 0x1000>;
  535. interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
  536. <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
  537. <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
  538. - <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
  539. - clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
  540. - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
  541. - clock-names = "mcu", "ap2conn";
  542. + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
  543. memory-region = <&wmcpu_emi>;
  544. - status = "disabled";
  545. };
  546. };
  547.  
  548. - fan: pwm-fan {
  549. - compatible = "pwm-fan";
  550. - /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */
  551. - cooling-levels = <0 86 172 255>;
  552. - #cooling-cells = <2>;
  553. - status = "disabled";
  554. - };
  555. -
  556. thermal-zones {
  557. cpu_thermal: cpu-thermal {
  558. polling-delay-passive = <1000>;
  559. polling-delay = <1000>;
  560. thermal-sensors = <&thermal 0>;
  561. - trips {
  562. - cpu_trip_crit: crit {
  563. - temperature = <125000>;
  564. - hysteresis = <2000>;
  565. - type = "critical";
  566. - };
  567. -
  568. - cpu_trip_hot: hot {
  569. - temperature = <120000>;
  570. - hysteresis = <2000>;
  571. - type = "hot";
  572. - };
  573.  
  574. + trips {
  575. cpu_trip_active_high: active-high {
  576. temperature = <115000>;
  577. hysteresis = <2000>;
  578. type = "active";
  579. };
  580.  
  581. - cpu_trip_active_med: active-med {
  582. + cpu_trip_active_low: active-low {
  583. temperature = <85000>;
  584. hysteresis = <2000>;
  585. type = "active";
  586. };
  587.  
  588. - cpu_trip_active_low: active-low {
  589. - temperature = <60000>;
  590. + cpu_trip_passive: passive {
  591. + temperature = <40000>;
  592. hysteresis = <2000>;
  593. type = "passive";
  594. };
  595. };
  596. -
  597. - cooling-maps {
  598. - cpu-active-high {
  599. - /* active: set fan to cooling level 3 */
  600. - cooling-device = <&fan 3 3>;
  601. - trip = <&cpu_trip_active_high>;
  602. - };
  603. -
  604. - cpu-active-med {
  605. - /* active: set fan to cooling level 2 */
  606. - cooling-device = <&fan 2 2>;
  607. - trip = <&cpu_trip_active_med>;
  608. - };
  609. -
  610. - cpu-active-low {
  611. - /* passive: set fan to cooling level 1 */
  612. - cooling-device = <&fan 1 1>;
  613. - trip = <&cpu_trip_active_low>;
  614. - };
  615. - };
  616. };
  617. };
  618. };
  619. \ No newline at end of file
  620.  
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