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exynos9810.dtsi

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Aug 26th, 2018
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  1. /*
  2. * SAMSUNG EXYNOS9810 SoC device tree source
  3. *
  4. * Copyright (c) 2017 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com
  6. *
  7. * SAMSUNG EXYNOS9810 SoC device nodes are listed in this file.
  8. * EXYNOS9810 based board files can include this file and provide
  9. * values for board specfic bindings.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15.  
  16. #include <dt-bindings/clock/exynos9810.h>
  17. #include <dt-bindings/interrupt-controller/exynos9810.h>
  18. #include <dt-bindings/sysmmu/sysmmu.h>
  19. #include <dt-bindings/soc/samsung/exynos9810.h>
  20. #include <dt-bindings/thermal/thermal.h>
  21. #include <dt-bindings/camera/fimc_is.h>
  22. #include <dt-bindings/pci/pci.h>
  23. #include "exynos9810-pinctrl.dtsi"
  24. #include <dt-bindings/ufs/ufs.h>
  25. #include "exynos9810-pm-domains.dtsi"
  26. #include "exynos9810-etm.dtsi"
  27. #include "exynos9810-inputbooster.dtsi"
  28. #include "exynos9810-ess.dtsi"
  29.  
  30. / {
  31. compatible = "samsung,armv8", "samsung,exynos9810";
  32. interrupt-parent = <&gic>;
  33. #address-cells = <2>;
  34. #size-cells = <1>;
  35.  
  36. aliases {
  37. pinctrl0 = &pinctrl_0;
  38. pinctrl1 = &pinctrl_1;
  39. pinctrl2 = &pinctrl_2;
  40. pinctrl3 = &pinctrl_3;
  41. pinctrl4 = &pinctrl_4;
  42. pinctrl5 = &pinctrl_5;
  43. pinctrl6 = &pinctrl_6;
  44. pinctrl7 = &pinctrl_7;
  45. pinctrl8 = &pinctrl_8;
  46. mshc2 = &dwmmc_2;
  47. usi0 = &usi_0;
  48. usi1 = &usi_0_i2c;
  49. usi2 = &usi_1;
  50. usi3 = &usi_1_i2c;
  51. usi4 = &usi_2;
  52. usi5 = &usi_2_i2c;
  53. usi6 = &usi_3;
  54. usi7 = &usi_3_i2c;
  55. usi8 = &usi_4;
  56. usi9 = &usi_4_i2c;
  57. usi10 = &usi_5;
  58. usi11 = &usi_5_i2c;
  59. usi12 = &usi_6;
  60. usi13 = &usi_6_i2c;
  61. usi14 = &usi_7;
  62. usi15 = &usi_7_i2c;
  63. usi16 = &usi_8;
  64. usi17 = &usi_8_i2c;
  65. usi18 = &usi_9;
  66. usi19 = &usi_9_i2c;
  67. usi20 = &usi_10;
  68. usi21 = &usi_10_i2c;
  69. usi22 = &usi_11;
  70. usi23 = &usi_11_i2c;
  71. usi24 = &usi_12;
  72. usi25 = &usi_12_i2c;
  73. usi26 = &usi_13;
  74. usi27 = &usi_13_i2c;
  75. usi28 = &usi_14;
  76. usi29 = &usi_14_i2c;
  77. usi30 = &usi_00_cmgp;
  78. usi31 = &usi_00_cmgp_i2c;
  79. usi32 = &usi_01_cmgp;
  80. usi33 = &usi_01_cmgp_i2c;
  81. usi34 = &usi_02_cmgp;
  82. usi35 = &usi_02_cmgp_i2c;
  83. usi36 = &usi_03_cmgp;
  84. usi37 = &usi_03_cmgp_i2c;
  85. usi38 = &usi_00_chub;
  86. usi39 = &usi_00_chub_i2c;
  87. usi40 = &usi_01_chub;
  88. usi41 = &usi_01_chub_i2c;
  89. hsi2c0 = &hsi2c_0;
  90. hsi2c1 = &hsi2c_1;
  91. hsi2c2 = &hsi2c_2;
  92. hsi2c3 = &hsi2c_3;
  93. hsi2c4 = &hsi2c_4;
  94. hsi2c5 = &hsi2c_5;
  95. hsi2c6 = &hsi2c_6;
  96. hsi2c7 = &hsi2c_7;
  97. hsi2c8 = &hsi2c_8;
  98. hsi2c9 = &hsi2c_9;
  99. hsi2c10 = &hsi2c_10;
  100. hsi2c11 = &hsi2c_11;
  101. hsi2c12 = &hsi2c_12;
  102. hsi2c13 = &hsi2c_13;
  103. hsi2c14 = &hsi2c_14;
  104. hsi2c15 = &hsi2c_15;
  105. hsi2c16 = &hsi2c_16;
  106. hsi2c17 = &hsi2c_17;
  107. hsi2c18 = &hsi2c_18;
  108. hsi2c19 = &hsi2c_19;
  109. hsi2c20 = &hsi2c_20;
  110. hsi2c21 = &hsi2c_21;
  111. hsi2c22 = &hsi2c_22;
  112. hsi2c23 = &hsi2c_23;
  113. hsi2c24 = &hsi2c_24;
  114. hsi2c25 = &hsi2c_25;
  115. hsi2c26 = &hsi2c_26;
  116. hsi2c27 = &hsi2c_27;
  117. hsi2c28 = &hsi2c_28;
  118. hsi2c29 = &hsi2c_29;
  119. hsi2c30 = &hsi2c_30;
  120. hsi2c31 = &hsi2c_31;
  121. hsi2c32 = &hsi2c_32;
  122. hsi2c33 = &hsi2c_33;
  123. hsi2c34 = &hsi2c_34;
  124. hsi2c35 = &hsi2c_35;
  125. hsi2c36 = &hsi2c_36;
  126. hsi2c37 = &hsi2c_37;
  127. hsi2c38 = &hsi2c_38;
  128. hsi2c39 = &hsi2c_39;
  129. hsi2c40 = &hsi2c_40;
  130. hsi2c41 = &hsi2c_41;
  131. hsi2c42 = &hsi2c_42;
  132. hsi2c43 = &hsi2c_43;
  133. hsi2c44 = &hsi2c_44;
  134. hsi2c45 = &hsi2c_45;
  135. spi0 = &spi_0;
  136. spi1 = &spi_1;
  137. spi2 = &spi_2;
  138. spi3 = &spi_3;
  139. spi4 = &spi_4;
  140. spi5 = &spi_5;
  141. spi6 = &spi_6;
  142. spi7 = &spi_7;
  143. spi8 = &spi_8;
  144. spi9 = &spi_9;
  145. spi10 = &spi_10;
  146. spi11 = &spi_11;
  147. spi12 = &spi_12;
  148. spi13 = &spi_13;
  149. spi14 = &spi_14;
  150. spi15 = &spi_15;
  151. spi16 = &spi_16;
  152. spi17 = &spi_17;
  153. spi18 = &spi_18;
  154. spi19 = &spi_19;
  155. spi20 = &spi_20;
  156. spi21 = &spi_21;
  157. ecduart = &serial_0;
  158. uart0 = &serial_0;
  159. dpp0 = &idma_g0;
  160. dpp1 = &idma_g1;
  161. dpp2 = &idma_vg0;
  162. dpp3 = &idma_vg1;
  163. dpp4 = &idma_vgf0;
  164. dpp5 = &idma_vgf1;
  165. dsim0 = &dsim_0;
  166. displayport = &displayport;
  167. decon0 = &decon_f;
  168. decon2 = &decon_t;
  169. uart1 = &serial_1;
  170. uart2 = &serial_2;
  171. uart3 = &serial_3;
  172. uart4 = &serial_4;
  173. uart5 = &serial_5;
  174. uart6 = &serial_6;
  175. uart7 = &serial_7;
  176. uart8 = &serial_8;
  177. uart9 = &serial_9;
  178. uart10 = &serial_10;
  179. uart11 = &serial_11;
  180. uart12 = &serial_12;
  181. uart13 = &serial_13;
  182. uart14 = &serial_14;
  183. uart15 = &serial_15;
  184. uart16 = &serial_16;
  185. uart17 = &serial_17;
  186. uart18 = &serial_18;
  187. uart19 = &serial_19;
  188. uart20 = &serial_20;
  189. uart21 = &serial_21;
  190. uart22 = &serial_22;
  191.  
  192. mfc0 = &mfc_0;
  193. scaler0 = &scaler_0;
  194. };
  195.  
  196. chipid@10000000 {
  197. compatible = "samsung,exynos9810-chipid";
  198. reg = <0x0 0x10000000 0x100>;
  199. };
  200.  
  201. arm-pmu {
  202. compatible = "arm,armv8-pmuv3";
  203. interrupts = <0 INTREQ__CPUCL1_PMUIRQ_0 4>,
  204. <0 INTREQ__CPUCL1_PMUIRQ_1 4>,
  205. <0 INTREQ__CPUCL1_PMUIRQ_2 4>,
  206. <0 INTREQ__CPUCL1_PMUIRQ_3 4>,
  207. <0 INTREQ__CPUCL0_PMUIRQ_0 4>,
  208. <0 INTREQ__CPUCL0_PMUIRQ_1 4>,
  209. <0 INTREQ__CPUCL0_PMUIRQ_2 4>,
  210. <0 INTREQ__CPUCL0_PMUIRQ_3 4>;
  211. };
  212.  
  213. cpus {
  214. #address-cells = <2>;
  215. #size-cells = <0>;
  216.  
  217. ehmp {
  218. /* lb trigger */
  219. #define DISABLED 0xFFFFFFFF
  220. top-overutil = <DISABLED
  221. DISABLED
  222. DISABLED
  223. DISABLED
  224. DISABLED
  225. DISABLED
  226. DISABLED
  227. DISABLED>;
  228. bot-overutil = <35
  229. 35
  230. 35
  231. 35
  232. DISABLED
  233. DISABLED
  234. DISABLED
  235. DISABLED>;
  236.  
  237. /* ontime migration */
  238. up-threshold = <79>;
  239. down-threshold = <128>;
  240. min-residency-us = <8192>;
  241. };
  242.  
  243. cpu0: cpu@0000 {
  244. device_type = "cpu";
  245. compatible = "arm,ananke", "arm,armv8";
  246. reg = <0x0 0x0000>;
  247. enable-method = "psci";
  248. cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
  249. sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
  250. };
  251. cpu1: cpu@0001 {
  252. device_type = "cpu";
  253. compatible = "arm,ananke", "arm,armv8";
  254. reg = <0x0 0x0001>;
  255. enable-method = "psci";
  256. cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
  257. sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
  258. };
  259. cpu2: cpu@0002 {
  260. device_type = "cpu";
  261. compatible = "arm,ananke", "arm,armv8";
  262. reg = <0x0 0x0002>;
  263. enable-method = "psci";
  264. cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
  265. sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
  266. };
  267. cpu3: cpu@0003 {
  268. device_type = "cpu";
  269. compatible = "arm,ananke", "arm,armv8";
  270. reg = <0x0 0x0003>;
  271. enable-method = "psci";
  272. cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
  273. sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
  274. };
  275. cpu4: cpu@0100 {
  276. device_type = "cpu";
  277. compatible = "arm,meerkat", "arm,armv8";
  278. reg = <0x0 0x100>;
  279. enable-method = "psci";
  280. cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
  281. sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
  282. };
  283. cpu5: cpu@0101 {
  284. device_type = "cpu";
  285. compatible = "arm,meerkat", "arm,armv8";
  286. reg = <0x0 0x101>;
  287. enable-method = "psci";
  288. cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
  289. sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
  290. };
  291. cpu6: cpu@0102 {
  292. device_type = "cpu";
  293. compatible = "arm,meerkat", "arm,armv8";
  294. reg = <0x0 0x102>;
  295. enable-method = "psci";
  296. cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
  297. sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
  298. };
  299. cpu7: cpu@0103 {
  300. device_type = "cpu";
  301. compatible = "arm,meerkat", "arm,armv8";
  302. reg = <0x0 0x103>;
  303. enable-method = "psci";
  304. cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
  305. sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
  306. };
  307. idle-states {
  308. entry-method = "arm,psci";
  309.  
  310. BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
  311. idle-state-name = "c2";
  312. compatible = "exynos,idle-state";
  313. arm,psci-suspend-param = <0x0010000>;
  314. entry-latency-us = <70>;
  315. exit-latency-us = <160>;
  316. min-residency-us = <2000>;
  317. status = "okay";
  318. };
  319.  
  320. NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
  321. idle-state-name = "c2";
  322. compatible = "exynos,idle-state";
  323. arm,psci-suspend-param = <0x0010000>;
  324. entry-latency-us = <235>;
  325. exit-latency-us = <220>;
  326. min-residency-us = <3500>;
  327. status = "okay";
  328. };
  329. };
  330. energy-costs {
  331. CPU_COST_0: core-core0{
  332. busy-cost-data = <
  333. 212 215
  334. 230 225
  335. 263 250
  336. 304 289
  337. 341 341
  338. 378 431
  339. 415 517
  340. 447 605
  341. 521 866
  342. 563 1037
  343. 600 1242
  344. 637 1452
  345. 683 1798
  346. 717 2025
  347. 747 2680
  348. 821 3180
  349. 886 3970
  350. 941 4861
  351. 959 5623
  352. 1015 6412
  353. 1024 7533
  354. >;
  355. idle-cost-data = <
  356. 10
  357. 0
  358. 0
  359. >;
  360. };
  361. CPU_COST_1: core-core1{
  362. busy-cost-data = <
  363. 46 22
  364. 61 31
  365. 72 39
  366. 84 51
  367. 96 63
  368. 107 77
  369. 127 105
  370. 148 149
  371. 171 231
  372. 182 240
  373. 198 250
  374. >;
  375. idle-cost-data = <
  376. 1
  377. 0
  378. 0
  379. >;
  380. };
  381. CLUSTER_COST_0: cluster-core0{
  382. busy-cost-data = <
  383. 212 61
  384. 230 64
  385. 263 70
  386. 304 76
  387. 341 93
  388. 378 123
  389. 415 151
  390. 447 181
  391. 521 268
  392. 563 325
  393. 600 393
  394. 637 463
  395. 683 579
  396. 717 654
  397. 747 873
  398. 821 1039
  399. 886 1302
  400. 941 1600
  401. 959 1854
  402. 1015 2117
  403. 1024 2490
  404. >;
  405. idle-cost-data = <
  406. 268
  407. 268
  408. 0
  409. >;
  410. };
  411. CLUSTER_COST_1: cluster-core1{
  412. busy-cost-data = <
  413. 46 1
  414. 61 3
  415. 72 4
  416. 84 7
  417. 96 9
  418. 107 12
  419. 127 18
  420. 148 26
  421. 171 43
  422. 182 53
  423. 198 58
  424. >;
  425. idle-cost-data = <
  426. 5
  427. 5
  428. 0
  429. >;
  430. };
  431. };
  432. };
  433.  
  434. exynos-pm {
  435. compatible = "samsung,exynos-pm";
  436. reg = <0x0 0x14050000 0x1000>,
  437. <0x0 0x10101200 0x100>;
  438. reg-names = "gpio_alive_base",
  439. "gicd_ispendrn_base";
  440. num-eint = <34>;
  441. num-gic = <16>;
  442. suspend_mode_idx = <8>; /* SYS_SLEEP */
  443. suspend_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
  444. cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
  445. cp_call_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
  446.  
  447. usbl2_suspend_available = <1>; /* SYS_SLEEP_AUD_ON */
  448. usbl2_suspend_mode_idx = <12>; /* SYS_SLEEP_AUD_ON */
  449. extra_wakeup_stat = <0x640>;
  450.  
  451. wakeup_stat_irqno = <0>, /* [0] EINT */
  452. <INTREQ__RTC_ALARM_INT>, <INTREQ__RTC_TIC_INT_0>,
  453. <INTREQ__TOP_RTC_ALARM_INT>, <INTREQ__TOP_RTC_TIC_INT_0>,
  454. <INTREQ__PCIE_WIFI0>, <INTREQ__PCIE_WIFI1>,
  455. <0>, <0>, /* [7:8] EXT_PCIE_GEN2,3 */
  456. <0>, <0>, /* [9:10] RSVD */
  457. <INTREQ__MMC_CARD>,
  458. <0>, <0>, /* [12:13] RSVD */
  459. <INTREQ__MCT_G0>,
  460. <0>, /* [15] CEC */
  461. <INTREQ__USB3_REMOTE_WAKEUP>, <INTREQ__USB2_REMOTE_WAKEUP>,
  462. <0>, /* [18] RSVD */
  463. <INTREQ__MAILBOX_APM2AP>, <INTREQ__CP2AP_WAKEUP>,
  464. <INTREQ__GNSS2AP_WAKEUP>, <INTREQ__GNSS2AP_WDOG_RESET>,
  465. <INTREQ__ALIVE_GNSS_ACTIVE>, <INTREQ__MAILBOX_CP2AP>,
  466. <INTREQ__ALIVE_CP_ACTIVE>, <INTREQ__MAILBOX_GNSS2AP>,
  467. <0>, <0>, /* [27] CORTEXM23_APM [28] RSVD */
  468. <INTREQ__S_MAILBOX_CP2AP>,
  469. <0>, <0>; /* [30] RSVD [31] WAKEUP */
  470.  
  471. extra_wakeup_stat_irqno {
  472. wakeup_stat4 {
  473. irqno = <INTREQ__MAILBOX_VTS2CHUB>, <INTREQ__WDT_VTS>,
  474. <INTREQ__SPEEDY_APM>, <INTREQ__UART_BT>,
  475. <INTREQ__UART_BT>, <INTREQ__WDT_CHUB>;
  476. /* [6:31] RSVD */
  477. };
  478. };
  479. };
  480.  
  481. exynos-powermode {
  482. cpd_residency = <10000>;
  483. sicd_residency = <10000>;
  484. cpd_enabled = <1>;
  485. sicd_enabled = <1>;
  486.  
  487. idle-ip = "10510000.pwm", /* [ 0] pwm */
  488. "14230000.adc", /* [ 1] adc */
  489. "10860000.hsi2c", /* [ 2] hsi2c_0 */
  490. "10870000.hsi2c", /* [ 3] hsi2c_1 */
  491. "10880000.hsi2c", /* [ 4] hsi2c_2 */
  492. "10890000.hsi2c", /* [ 5] hsi2c_3 */
  493. "10450000.hsi2c", /* [ 6] hsi2c_4 */
  494. "10460000.hsi2c", /* [ 7] hsi2c_5 */
  495. "10470000.hsi2c", /* [ 8] hsi2c_6 */
  496. "10480000.hsi2c", /* [ 9] hsi2c_7 */
  497. "10490000.hsi2c", /* [10] hsi2c_8 */
  498. "104a0000.hsi2c", /* [11] hsi2c_9 */
  499. "104b0000.hsi2c", /* [12] hsi2c_10 */
  500. "104c0000.hsi2c", /* [13] hsi2c_11 */
  501. "104d0000.hsi2c", /* [14] hsi2c_12 */
  502. "104e0000.hsi2c", /* [15] hsi2c_13 */
  503. "104f0000.hsi2c", /* [16] hsi2c_14 */
  504. "10500000.hsi2c", /* [17] hsi2c_15 */
  505. "108a0000.hsi2c", /* [18] hsi2c_16 */
  506. "108b0000.hsi2c", /* [19] hsi2c_17 */
  507. "108c0000.hsi2c", /* [20] hsi2c_18 */
  508. "108d0000.hsi2c", /* [21] hsi2c_19 */
  509. "108e0000.hsi2c", /* [22] hsi2c_20 */
  510. "108f0000.hsi2c", /* [23] hsi2c_21 */
  511. "10900000.hsi2c", /* [24] hsi2c_22 */
  512. "10910000.hsi2c", /* [25] hsi2c_23 */
  513. "10920000.hsi2c", /* [26] hsi2c_24 */
  514. "10930000.hsi2c", /* [27] hsi2c_25 */
  515. "10940000.hsi2c", /* [28] hsi2c_26 */
  516. "10950000.hsi2c", /* [29] hsi2c_27 */
  517. "10520000.hsi2c", /* [30] hsi2c_28 */
  518. "10530000.hsi2c", /* [31] hsi2c_29 */
  519. "10540000.hsi2c", /* [32] hsi2c_30 */
  520. "10550000.hsi2c", /* [33] hsi2c_31 */
  521. "10560000.hsi2c", /* [34] hsi2c_32 */
  522. "10570000.hsi2c", /* [35] hsi2c_33 */
  523. "14300000.hsi2c", /* [36] hsi2c_34 */
  524. "14310000.hsi2c", /* [37] hsi2c_35 */
  525. "14320000.hsi2c", /* [38] hsi2c_36 */
  526. "14330000.hsi2c", /* [39] hsi2c_37 */
  527. "14340000.hsi2c", /* [40] hsi2c_38 */
  528. "14350000.hsi2c", /* [41] hsi2c_39 */
  529. "14360000.hsi2c", /* [42] hsi2c_40 */
  530. "14370000.hsi2c", /* [43] hsi2c_41 */
  531. "10850000.spi", /* [44] spi_0 */
  532. "10450000.spi", /* [45] spi_1 */
  533. "10470000.spi", /* [46] spi_2 */
  534. "10490000.spi", /* [47] spi_3 */
  535. "104b0000.spi", /* [48] spi_4 */
  536. "104d0000.spi", /* [49] spi_5 */
  537. "104f0000.spi", /* [50] spi_6 */
  538. "108a0000.spi", /* [51] spi_7 */
  539. "108c0000.spi", /* [52] spi_8 */
  540. "108e0000.spi", /* [53] spi_9 */
  541. "10900000.spi", /* [54] spi_10 */
  542. "10920000.spi", /* [55] spi_11 */
  543. "10940000.spi", /* [56] spi_12 */
  544. "10520000.spi", /* [57] spi_13 */
  545. "10540000.spi", /* [58] spi_14 */
  546. "10560000.spi", /* [59] spi_15 */
  547. "14300000.spi", /* [60] spi_16 */
  548. "14320000.spi", /* [61] spi_17 */
  549. "14340000.spi", /* [62] spi_18 */
  550. "14360000.spi", /* [63] spi_19 */
  551. "11120000.ufs", /* [64] ufs */
  552. "11500000.dwmmc2", /* [65] dwmmc2 */
  553. "10c00000.usb", /* [66] usb */
  554. "141a0000.mailbox", /* [67] mailbox */
  555. "116a0000.pcie0", /* [68] pcie0 */
  556. "116b0000.pcie1", /* [69] pcie1 */
  557. "pd-aud", /* [70] pd-aud */
  558. "pd-dcf", /* [71] pd-dcf */
  559. "pd-dcpost", /* [72] pd-dcpost*/
  560. "pd-dcrd", /* [73] pd-dcrd */
  561. "pd-dpu", /* [74] pd-dpu */
  562. "pd-dspm", /* [75] pd-dspm */
  563. "pd-dsps", /* [76] pd-dsps */
  564. "pd-g2d", /* [77] pd-g2d */
  565. "pd-embedded_g3d", /* [78] pd-embedded_g3d */
  566. "pd-isppre", /* [79] pd-isppre */
  567. "pd-isphq", /* [80] pd-isphq */
  568. "pd-isplp", /* [81] pd-isplp */
  569. "pd-iva", /* [82] pd-iva */
  570. "pd-mfc", /* [83] pd-mfc */
  571. "pd-vts", /* [84] pd-vts */
  572. "11090000.displayport", /* [85] displayport */
  573. "bluetooth"; /* [86] bluetooth */
  574. fix-idle-ip = "acpm_dvfs";
  575. fix-idle-ip-index = <96>;
  576.  
  577. idle_ip_mask {
  578. sicd: SYS_SICD {
  579. mode-index = <0>;
  580. ref-idle-ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
  581. <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
  582. <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
  583. <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
  584. <40>, <41>, <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>,
  585. <50>, <51>, <52>, <53>, <54>, <55>, <56>, <57>, <58>, <59>,
  586. <60>, <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>,
  587. <74>, <75>, <76>, <77>, <78>, <79>,
  588. <80>, <81>, <82>, <83>, <85>, <86>, <96>;
  589. };
  590. };
  591.  
  592. wakeup-masks {
  593. /*
  594. * wakeup_mask configuration
  595. * SICD SICD_CPD AFTR STOP
  596. * LPD LPA ALPA DSTOP
  597. * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO USB_L2
  598. */
  599. wakeup-mask {
  600. mask = <0x400001E0>, <0x0>, <0x0>, <0x0>,
  601. <0x0>, <0x0>, <0x0>, <0x0>,
  602. <0xD00F7E7E>, <0x500F7E7E>, <0x500F7E7E>, <0x0>, <0xD00D7E7E>;
  603. reg-offset = <0x610>;
  604. };
  605. wakeup-mask2 {
  606. mask = <0x0>, <0x0>, <0x0>, <0x0>,
  607. <0x0>, <0x0>, <0x0>, <0x0>,
  608. <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>, <0xFFFF00FF>;
  609. reg-offset = <0x614>;
  610. };
  611. wakeup-mask3 {
  612. mask = <0x0>, <0x0>, <0x0>, <0x0>,
  613. <0x0>, <0x0>, <0x0>, <0x0>,
  614. <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>, <0xFFFF00FF>;
  615. reg-offset = <0x618>;
  616. };
  617. wakeup-mask4 {
  618. mask = <0x0>, <0x0>, <0x0>, <0x0>,
  619. <0x0>, <0x0>, <0x0>, <0x0>,
  620. <0x0>, <0x0>, <0x0>, <0x0>, <0x0>;
  621. reg-offset = <0x644>;
  622. };
  623. };
  624. };
  625.  
  626. psci {
  627. compatible = "arm,psci";
  628. method = "smc";
  629. cpu_suspend = <0xC4000001>;
  630. cpu_off = <0x84000002>;
  631. cpu_on = <0xC4000003>;
  632. };
  633.  
  634. exynos-ocp {
  635. compatible = "samsung,exynos-ocp";
  636.  
  637. interrupts = <0 INTREQ__CPUCL1_GCUIRQ 0>;
  638. sibling-cpus = "4-7";
  639. down-step = <1>;
  640.  
  641. max-freq-wo-ocp = <1794000>;
  642.  
  643. release-mode = <1>; /* 0 : current meter, 1 : cpu utilization */
  644. release-threshold = <50>; /* @current meter : current(A), @cpu load : capacity ratio(%) */
  645. release-duration = <15>; /* msec */
  646. };
  647.  
  648. exynos-pmu {
  649. compatible = "samsung,exynos-pmu";
  650. samsung,syscon-phandle = <&pmu_system_controller>;
  651. };
  652.  
  653. pmu_system_controller: system-controller@14060000 {
  654. compatible = "samsung,exynos9810-pmu", "syscon";
  655. reg = <0x0 0x14060000 0x10000>;
  656. };
  657.  
  658. gic:interrupt-controller@10100000 {
  659. compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
  660. #interrupt-cells = <3>;
  661. #address-cells = <0>;
  662. interrupt-controller;
  663. reg = <0x0 0x10101000 0x1000>,
  664. <0x0 0x10102000 0x1000>,
  665. <0x0 0x10104000 0x2000>,
  666. <0x0 0x10106000 0x2000>;
  667. interrupts = <1 9 0xf04>;
  668. };
  669.  
  670. timer {
  671. compatible = "arm,armv8-timer";
  672. interrupts = <GIC_PPI 13
  673. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  674. <GIC_PPI 14
  675. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  676. <GIC_PPI 11
  677. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
  678. <GIC_PPI 10
  679. (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
  680. clock-frequency = <26000000>;
  681. use-clocksource-only;
  682. use-physical-timer;
  683. };
  684.  
  685. clock: clock-controller@0x15a80000 {
  686. compatible = "samsung,exynos9810-clock";
  687. reg = <0x0 0x15a80000 0x8000>;
  688. #clock-cells = <1>;
  689. };
  690.  
  691. mct@10040000 {
  692. compatible = "samsung,exynos4210-mct";
  693. reg = <0x0 0x10040000 0x800>;
  694. interrupt-controller;
  695. #interrupt-cells = <1>;
  696. interrupt-parent = <&mct_map>;
  697. interrupts = <0>, <1>, <2>, <3>,
  698. <4>, <5>, <6>, <7>,
  699. <8>, <9>, <10>, <11>;
  700. clocks = <&clock OSCCLK>, <&clock GATE_MCT>;
  701. clock-names = "fin_pll", "mct";
  702. use-clockevent-only;
  703.  
  704. mct_map: mct-map {
  705. #interrupt-cells = <1>;
  706. #address-cells = <0>;
  707. #size-cells = <0>;
  708. interrupt-map = <0 &gic 0 INTREQ__MCT_G0 0>,
  709. <1 &gic 0 INTREQ__MCT_G1 0>,
  710. <2 &gic 0 INTREQ__MCT_G2 0>,
  711. <3 &gic 0 INTREQ__MCT_G3 0>,
  712. <4 &gic 0 INTREQ__MCT_L0 0>,
  713. <5 &gic 0 INTREQ__MCT_L1 0>,
  714. <6 &gic 0 INTREQ__MCT_L2 0>,
  715. <7 &gic 0 INTREQ__MCT_L3 0>,
  716. <8 &gic 0 INTREQ__MCT_L4 0>,
  717. <9 &gic 0 INTREQ__MCT_L5 0>,
  718. <10 &gic 0 INTREQ__MCT_L6 0>,
  719. <11 &gic 0 INTREQ__MCT_L7 0>;
  720. };
  721. };
  722.  
  723. /* DMA */
  724. amba {
  725. #address-cells = <2>;
  726. #size-cells = <1>;
  727. compatible = "arm,amba-bus";
  728. interrupt-parent = <&gic>;
  729. ranges;
  730.  
  731. pdma0: pdma0@1A2E0000 {
  732. compatible = "arm,pl330", "arm,primecell";
  733. reg = <0x0 0x1A2E0000 0x1000>;
  734. interrupts = <0 INTREQ__PDMA0 0>;
  735. clocks = <&clock GATE_PDMA0>;
  736. clock-names = "apb_pclk";
  737. #dma-cells = <1>;
  738. #dma-channels = <8>;
  739. #dma-requests = <32>;
  740. #dma-multi-irq = <1>;
  741. dma-arwrapper = <0x1A2E4400>,
  742. <0x1A2E4420>,
  743. <0x1A2E4440>,
  744. <0x1A2E4460>,
  745. <0x1A2E4480>,
  746. <0x1A2E44A0>,
  747. <0x1A2E44C0>,
  748. <0x1A2E44E0>;
  749. dma-awwrapper = <0x1A2E4404>,
  750. <0x1A2E4424>,
  751. <0x1A2E4444>,
  752. <0x1A2E4464>,
  753. <0x1A2E4484>,
  754. <0x1A2E44A4>,
  755. <0x1A2E44C4>,
  756. <0x1A2E44E4>;
  757. dma-instwrapper = <0x1A2E4500>;
  758. dma-mask-bit = <36>;
  759. coherent-mask-bit = <36>;
  760. };
  761. };
  762.  
  763. mali: mali@17500000 {
  764. compatible = "arm,mali";
  765. reg = <0x0 0x17500000 0x5000>;
  766. interrupts = <0 INTREQ__G3D_IRQJOB 0>,
  767. <0 INTREQ__G3D_IRQMMU 0>,
  768. <0 INTREQ__G3D_IRQGPU 0>;
  769. interrupt-names = "JOB", "MMU", "GPU";
  770. g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
  771. samsung,power-domain = <&pd_embedded_g3d>;
  772. #cooling-cells = <2>; /* min followed by max */
  773. };
  774.  
  775. ITMON@0 {
  776. compatible = "samsung,exynos-itmon";
  777. interrupts = <0 INTREQ__TREX_DEBUG 0>, /* DATA_BUS_C */
  778. <0 INTREQ__TREX_D_CORE_debugInterrupt 0>, /* DATA_CORE */
  779. <0 INTREQ__TREX_P0_CORE_debugInterrupt 0>, /* PERI_CORE_0 */
  780. <0 INTREQ__TREX_P_DEBUG 0>, /* PERI_BUS_C */
  781. <0 INTREQ__TREX_P1_CORE_debugInterrupt 0>, /* PERI_CORE_1 */
  782. <0 INTREQ__TREX_P_BUS1_DEBUG 0>; /* PERI_BUS_1 */
  783. };
  784.  
  785. /* ALIVE */
  786. pinctrl_0: pinctrl@14050000 {
  787. compatible = "samsung,exynos9810-pinctrl";
  788. reg = <0x0 0x14050000 0x1000>;
  789. interrupts = <0 INTREQ__EINT0 0>, <0 INTREQ__EINT1 0>, <0 INTREQ__EINT2 0>,
  790. <0 INTREQ__EINT3 0>, <0 INTREQ__EINT4 0>, <0 INTREQ__EINT5 0>,
  791. <0 INTREQ__EINT6 0>, <0 INTREQ__EINT7 0>, <0 INTREQ__EINT8 0>,
  792. <0 INTREQ__EINT9 0>, <0 INTREQ__EINT10 0>, <0 INTREQ__EINT11 0>,
  793. <0 INTREQ__EINT12 0>, <0 INTREQ__EINT13 0>, <0 INTREQ__EINT14 0>,
  794. <0 INTREQ__EINT15 0>, <0 INTREQ__EINT16 0>, <0 INTREQ__EINT17 0>,
  795. <0 INTREQ__EINT18 0>, <0 INTREQ__EINT19 0>, <0 INTREQ__EINT20 0>,
  796. <0 INTREQ__EINT21 0>, <0 INTREQ__EINT22 0>, <0 INTREQ__EINT23 0>,
  797. <0 INTREQ__EINT24 0>, <0 INTREQ__EINT25 0>, <0 INTREQ__EINT26 0>,
  798. <0 INTREQ__EINT27 0>, <0 INTREQ__EINT28 0>, <0 INTREQ__EINT29 0>,
  799. <0 INTREQ__EINT30 0>, <0 INTREQ__EINT31 0>, <0 INTREQ__EINT32 0>,
  800. <0 INTREQ__EINT33 0>;
  801.  
  802. wakeup-interrupt-controller {
  803. compatible = "samsung,exynos7-wakeup-eint";
  804. };
  805. };
  806.  
  807. /* AUD */
  808. pinctrl_1: pinctrl@17C60000{
  809. compatible = "samsung,exynos9810-pinctrl";
  810. reg = <0x0 0x17C60000 0x1000>;
  811. };
  812.  
  813. /* CHUB */
  814. pinctrl_2: pinctrl@13A80000{
  815. compatible = "samsung,exynos9810-pinctrl";
  816. reg = <0x0 0x13A80000 0x1000>;
  817. interrupts = <0 INTREQ__GPIO_CHUB 0>;
  818. };
  819.  
  820. /* CMGP */
  821. pinctrl_3: pinctrl@14220000{
  822. compatible = "samsung,exynos9810-pinctrl";
  823. reg = <0x0 0x14220000 0x1000>;
  824. interrupts = <0 INTREQ__EXT_INTM0_0 0>, <0 INTREQ__EXT_INTM0_1 0>,
  825. <0 INTREQ__EXT_INTM0_2 0>, <0 INTREQ__EXT_INTM0_3 0>,
  826. <0 INTREQ__EXT_INTM0_4 0>, <0 INTREQ__EXT_INTM0_5 0>,
  827. <0 INTREQ__EXT_INTM0_6 0>, <0 INTREQ__EXT_INTM0_7 0>,
  828. <0 INTREQ__EXT_INTM1_0 0>, <0 INTREQ__EXT_INTM1_1 0>,
  829. <0 INTREQ__EXT_INTM1_2 0>, <0 INTREQ__EXT_INTM1_3 0>,
  830. <0 INTREQ__EXT_INTM1_4 0>, <0 INTREQ__EXT_INTM1_5 0>,
  831. <0 INTREQ__EXT_INTM1_6 0>, <0 INTREQ__EXT_INTM1_7 0>,
  832. <0 INTREQ__EXT_INTM4_0 0>, <0 INTREQ__EXT_INTM4_1 0>,
  833. <0 INTREQ__EXT_INTM4_2 0>, <0 INTREQ__EXT_INTM4_3 0>;
  834.  
  835. wakeup-interrupt-controller {
  836. compatible = "samsung,exynos7-wakeup-eint";
  837. };
  838. };
  839.  
  840. /* FSYS0 */
  841. pinctrl_4: pinctrl@11050000 {
  842. compatible = "samsung,exynos9810-pinctrl";
  843. reg = <0x0 0x11050000 0x1000>;
  844. interrupts = <0 INTREQ__GPIO_FSYS0 0>;
  845. };
  846.  
  847. /* FSYS1 */
  848. pinctrl_5: pinctrl@11430000 {
  849. compatible = "samsung,exynos9810-pinctrl";
  850. reg = <0x0 0x11430000 0x1000>;
  851. interrupts = <0 INTREQ__GPIO_FSYS1 0>;
  852. };
  853.  
  854. /* PERIC0 */
  855. pinctrl_6: pinctrl@10430000 {
  856. compatible = "samsung,exynos9810-pinctrl";
  857. reg = <0x0 0x10430000 0x1000>;
  858. interrupts = <0 INTREQ__GPIO_PERIC0 0>;
  859. };
  860.  
  861. /* PERIC1 */
  862. pinctrl_7: pinctrl@10830000 {
  863. compatible = "samsung,exynos9810-pinctrl";
  864. reg = <0x0 0x10830000 0x1000>;
  865. interrupts = <0 INTREQ__GPIO_PERIC1 0>;
  866. };
  867.  
  868. /* VTS */
  869. pinctrl_8: pinctrl@13880000 {
  870. compatible = "samsung,exynos9810-pinctrl";
  871. reg = <0x0 0x13880000 0x1000>;
  872. };
  873.  
  874. idma_g0: dpp@0x16021000 {
  875. compatible = "samsung,exynos9-dpp";
  876. #pb-id-cells = <3>;
  877. /* DPP, DPU_DMA, DPU_DMA_COMMON */
  878. reg = <0x0 0x16021000 0x1000>, <0x0 0x16071000 0x1000>, <0x0 0x16070000 0x110>;
  879. /* DPU_DMA IRQ, DPP IRQ */
  880. interrupts = <0 INTREQ__DPU_DMA_G0 0>, <0 INTREQ__DPU_DPP_G0 0>;
  881.  
  882. /* power domain */
  883. samsung,power-domain = <&pd_dpu>;
  884. };
  885.  
  886. idma_g1: dpp@0x16022000 {
  887. compatible = "samsung,exynos9-dpp";
  888. #pb-id-cells = <3>;
  889. reg = <0x0 0x16022000 0x1000>, <0x0 0x16072000 0x1000>;
  890. interrupts = <0 INTREQ__DPU_DMA_G1 0>, <0 INTREQ__DPU_DPP_G1 0>;
  891.  
  892. /* power domain */
  893. samsung,power-domain = <&pd_dpu>;
  894. };
  895.  
  896. idma_vg0: dpp@0x16023000 {
  897. compatible = "samsung,exynos9-dpp";
  898. #pb-id-cells = <3>;
  899. reg = <0x0 0x16023000 0x1000>, <0x0 0x16073000 0x1000>;
  900. interrupts = <0 INTREQ__DPU_DMA_VG0 0>, <0 INTREQ__DPU_DPP_VG0 0>;
  901.  
  902. /* power domain */
  903. samsung,power-domain = <&pd_dpu>;
  904. };
  905.  
  906. idma_vg1: dpp@0x16024000 {
  907. compatible = "samsung,exynos9-dpp";
  908. #pb-id-cells = <3>;
  909. reg = <0x0 0x16024000 0x1000>, <0x0 0x16074000 0x1000>;
  910. interrupts = <0 INTREQ__DPU_DMA_VG1 0>, <0 INTREQ__DPU_DPP_VG1 0>;
  911.  
  912. /* power domain */
  913. samsung,power-domain = <&pd_dpu>;
  914. };
  915.  
  916. idma_vgf0: dpp@0x16025000 {
  917. compatible = "samsung,exynos9-dpp";
  918. #pb-id-cells = <3>;
  919. reg = <0x0 0x16025000 0x1000>, <0x0 0x16075000 0x1000>;
  920. interrupts = <0 INTREQ__DPU_DMA_VGF 0>, <0 INTREQ__DPU_DPP_VGF0 0>;
  921.  
  922. /* power domain */
  923. samsung,power-domain = <&pd_dpu>;
  924. };
  925.  
  926. idma_vgf1: dpp@0x16026000 {
  927. compatible = "samsung,exynos9-dpp";
  928. #pb-id-cells = <3>;
  929. reg = <0x0 0x16026000 0x1000>, <0x0 0x16076000 0x1000>;
  930. interrupts = <0 INTREQ__DPU_DMA_VGRF 0>, <0 INTREQ__DPU_DPP_VGF1 0>;
  931.  
  932. /* power domain */
  933. samsung,power-domain = <&pd_dpu>;
  934. };
  935.  
  936. disp_ss: disp_ss@0x16010000 {
  937. compatible = "samsung,exynos9-disp_ss";
  938. reg = <0x0 0x16011000 0x10>;
  939. };
  940.  
  941. mipi_phy_dsim: phy_m4s4top_dsi0@0x16160000 {
  942. compatible = "samsung,mipi-phy-m4s4-top";
  943. samsung,pmu-syscon = <&pmu_system_controller>;
  944. isolation = <0x070C>;
  945. /* PHY reset be controlled from DSIM */
  946. /* reg = <0x0 0x12821008 0x4>; */
  947. /* reset = <0 1>; */
  948. /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
  949. owner = <0>; /* 0: DSI, 1: CSI */
  950. #phy-cells = <1>;
  951. };
  952.  
  953. dsim_0: dsim@0x16080000 {
  954. compatible = "samsung,exynos9-dsim";
  955. reg = <0x0 0x16080000 0x100>, <0x0 0x16160000 0x4000>;
  956. interrupts = <0 INTREQ__DPU_DSIM0 0>;
  957. iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>;
  958.  
  959. /* clock */
  960. clock-names = "aclk";
  961. clocks = <&clock GATE_DPU>;
  962.  
  963. phys = <&mipi_phy_dsim 0>;
  964. phy-names = "dsim_dphy";
  965.  
  966. /* power domain */
  967. samsung,power-domain = <&pd_dpu>;
  968. };
  969.  
  970. displayport_phy: displayport_phy@110A0000 {
  971. compatible = "samsung,displayport-phy";
  972. samsung,pmu-syscon = <&pmu_system_controller>;
  973. isolation = <0x0704>;
  974. #phy-cells = <1>;
  975. };
  976.  
  977. displayport: displayport@0x11090000 {
  978. compatible = "samsung,exynos-displayport";
  979. reg = <0x0 0x11090000 0xFFFF>;
  980. interrupts = <0 INTREQ__DP_LINK 0>;
  981. iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>;
  982.  
  983. /* clock */
  984. clock-names = "aclk";
  985. clocks = <&clock GATE_DPU>;
  986.  
  987. phys = <&displayport_phy 0>;
  988. phy-names = "displayport_phy";
  989.  
  990. /* power domain */
  991. samsung,power-domain = <&pd_dpu>;
  992. };
  993.  
  994. displayport_adma: dp_dma {
  995. compatible = "samsung,displayport-adma";
  996.  
  997. /* dma-mode; */
  998. dmas = <&pdma0 28>;
  999. dma-names = "tx";
  1000. };
  1001.  
  1002. decon_f: decon_f@0x16030000 {
  1003. compatible = "samsung,exynos9-decon"; /* exynos9810 */
  1004. #pb-id-cells = <4>;
  1005. reg = <0x0 0x16030000 0x10000>;
  1006.  
  1007. /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */
  1008. interrupts = <0 INTREQ__DPU_DECON0_FRAME_START 0>,
  1009. <0 INTREQ__DPU_DECON0_FRAME_DONE 0>,
  1010. <0 INTREQ__DPU_DECON0_EXTRA 0>,
  1011. <0 INTREQ__GPIO_PERIC1 0>;
  1012.  
  1013. /* pinctrl */
  1014. pinctrl-names = "hw_te_on", "hw_te_off";
  1015. pinctrl-0 = <&decon_f_te_on>;
  1016. pinctrl-1 = <&decon_f_te_off>;
  1017.  
  1018. /* power domain */
  1019. samsung,power-domain = <&pd_dpu>;
  1020.  
  1021. max_win = <6>;
  1022. default_win = <5>;
  1023. default_idma = <0>;
  1024. psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
  1025. trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
  1026. dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
  1027.  
  1028. /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
  1029. out_type = <0>;
  1030. /* 0: DSI0, 1: DSI1, 2: DSI2 */
  1031. out_idx = <0>;
  1032.  
  1033. #address-cells = <2>;
  1034. #size-cells = <1>;
  1035. ranges;
  1036.  
  1037. /* EINT for TE */
  1038. gpios = <&gpd0 0 0xf>;
  1039. /* sw te pending register */
  1040. te_eint {
  1041. /* NWEINT_GPD0_PEND */
  1042. reg = <0x0 0x10830a14 0x4>;
  1043. };
  1044.  
  1045. cam-stat {
  1046. /* ISPPRE_STATUS(0x1406404C), ISPHQ_STATUS(0x14064054), ISPLP_STATUS(0x1406405C) */
  1047. reg = <0x0 0x1406404C 0x4>;
  1048. };
  1049. };
  1050.  
  1051. decon_t: decon_t@0x16050000 {
  1052. compatible = "samsung,exynos9-decon"; /* exynos9810 */
  1053. #pb-id-cells = <4>;
  1054. reg = <0x0 0x16050000 0x10000>;
  1055.  
  1056. /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA */
  1057. interrupts = <0 INTREQ__DPU_DECON2_FRAME_START 0>,
  1058. <0 INTREQ__DPU_DECON2_FRAME_DONE 0>,
  1059. <0 INTREQ__DPU_DECON2_EXTRA 0>;
  1060.  
  1061. /* power domain */
  1062. samsung,power-domain = <&pd_dpu>;
  1063.  
  1064. max_win = <6>;
  1065. default_win = <4>;
  1066. default_idma = <1>;
  1067. psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
  1068. trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
  1069. dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
  1070.  
  1071. /* 0: DSI, 1: eDP, 2:DP */
  1072. out_type = <2>;
  1073. /* 0: DSI0, 1: DSI1, 2: DSI2 */
  1074. out_idx = <0>;
  1075.  
  1076. #address-cells = <2>;
  1077. #size-cells = <1>;
  1078. ranges;
  1079. };
  1080.  
  1081. udc: usb@10C00000 {
  1082. compatible = "samsung,exynos-dwusb";
  1083. clocks = <&clock GATE_USB30DRD_USB30DRD_LINK>, <&clock USB30DRD>;
  1084. clock-names = "aclk", "sclk";
  1085. reg = <0x0 0x10C00000 0x10000>;
  1086. #address-cells = <2>;
  1087. #size-cells = <1>;
  1088. ranges;
  1089. status = "disabled";
  1090.  
  1091. usbdrd_dwc3: dwc3 {
  1092. compatible = "synopsys,dwc3";
  1093. reg = <0x0 0x10C00000 0x10000>;
  1094. interrupts = <0 INTREQ__USB30DRD_Interrupt_00 0>;
  1095. tx-fifo-resize = <0>;
  1096. adj-sof-accuracy = <0>;
  1097. is_not_vbus_pad = <1>;
  1098. enable_sprs_transfer = <1>;
  1099. phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
  1100. phy-names = "usb2-phy", "usb3-phy";
  1101. /* check susphy support */
  1102. xhci_l2_support = <1>;
  1103. /* support usb audio offloading: 1, if not: 0 */
  1104. usb_audio_offloading = <1>;
  1105. abox = <&abox>;
  1106. /* support USB L2 sleep */
  1107. ldos = <6>;
  1108. ldo_number = <9 10 11 12 13 14>;
  1109. };
  1110. };
  1111.  
  1112. usbdrd_phy0: phy@11100000 {
  1113. compatible = "samsung,exynos-usbdrd-phy";
  1114. reg = <0x0 0x11100000 0x200>,
  1115. <0x0 0x110A0000 0x1000>,
  1116. <0x0 0x110B0000 0x800>;
  1117. interrupts = <0 INTREQ__USB2_REMOTE_WAKEUP 0>,
  1118. <0 INTREQ__USB2_REMOTE_CONNECT 0>;
  1119. clocks = <&clock OSCCLK>, <&clock GATE_USB30DRD_USB30DRD_LINK>;
  1120. clock-names = "ext_xtal", "aclk";
  1121. samsung,pmu-syscon = <&pmu_system_controller>;
  1122. pmu_mask = <0x0>;
  1123. pmu_offset = <0x72c>;
  1124. pmu_offset_dp = <0x704>;
  1125.  
  1126. /* USBDP combo phy version - 0x200 */
  1127. phy_version = <0x300>;
  1128. /* if it doesn't need phy user mux, */
  1129. /* you should write "none" */
  1130. /* but refclk shouldn't be omitted */
  1131. phyclk_mux = "none";
  1132. phy_refclk = "ext_xtal";
  1133.  
  1134. /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
  1135. has_other_phy = <0>;
  1136. /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
  1137. has_combo_phy = <1>;
  1138. sub_phy_version = <0x400>;
  1139.  
  1140. /* ip type */
  1141. /* USB3DRD = 0 */
  1142. /* USB3HOST = 1 */
  1143. /* USB2DRD = 2 */
  1144. /* USB2HOST = 3 */
  1145. ip_type = <0x0>;
  1146.  
  1147. /* for PHY CAL */
  1148. /* choice only one item */
  1149. phy_refsel_clockcore = <1>;
  1150. phy_refsel_ext_osc = <0>;
  1151. phy_refsel_xtal = <0>;
  1152. phy_refsel_diff_pad = <0>;
  1153. phy_refsel_diff_internal = <0>;
  1154. phy_refsel_diff_single = <0>;
  1155.  
  1156. /* true : 1 , false : 0 */
  1157. use_io_for_ovc = <0>;
  1158. common_block_disable = <1>;
  1159. is_not_vbus_pad = <1>;
  1160. used_phy_port = <0>;
  1161.  
  1162. status = "disabled";
  1163.  
  1164. #phy-cells = <1>;
  1165. ranges;
  1166. };
  1167.  
  1168. /* USI_00 */
  1169. usi_0: usi@10411004 {
  1170. compatible = "samsung,exynos-usi-v2";
  1171. reg = <0x0 0x10411004 0x4>;
  1172. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1173. status = "disabled";
  1174. };
  1175.  
  1176. /* USI_00_I2C */
  1177. usi_0_i2c: usi@10411008 {
  1178. compatible = "samsung,exynos-usi-v2";
  1179. reg = <0x0 0x10411008 0x4>;
  1180. /* usi_mode_v2 = "i2c" */
  1181. status = "disabled";
  1182. };
  1183.  
  1184. /* USI_01 */
  1185. usi_1: usi@1041100c {
  1186. compatible = "samsung,exynos-usi-v2";
  1187. reg = <0x0 0x1041100c 0x4>;
  1188. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1189. status = "disabled";
  1190. };
  1191.  
  1192. /* USI_01_I2C */
  1193. usi_1_i2c: usi@10411010 {
  1194. compatible = "samsung,exynos-usi-v2";
  1195. reg = <0x0 0x10411010 0x4>;
  1196. /* usi_mode_v2 = "i2c" */
  1197. status = "disabled";
  1198. };
  1199.  
  1200. /* USI_02 */
  1201. usi_2: usi@10411014 {
  1202. compatible = "samsung,exynos-usi-v2";
  1203. reg = <0x0 0x10411014 0x4>;
  1204. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1205. status = "disabled";
  1206. };
  1207.  
  1208. /* USI_02_I2C */
  1209. usi_2_i2c: usi@10411018 {
  1210. compatible = "samsung,exynos-usi-v2";
  1211. reg = <0x0 0x10411018 0x4>;
  1212. /* usi_mode_v2 = "i2c" */
  1213. status = "disabled";
  1214. };
  1215.  
  1216. /* USI_03 */
  1217. usi_3: usi@1041101C {
  1218. compatible = "samsung,exynos-usi-v2";
  1219. reg = <0x0 0x1041101c 0x4>;
  1220. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1221. status = "disabled";
  1222. };
  1223.  
  1224. /* USI_03_I2C */
  1225. usi_3_i2c: usi@10411020 {
  1226. compatible = "samsung,exynos-usi-v2";
  1227. reg = <0x0 0x10411020 0x4>;
  1228. /* usi_mode_v2 = "i2c" */
  1229. status = "disabled";
  1230. };
  1231.  
  1232. /* USI_04 */
  1233. usi_4: usi@10411024 {
  1234. compatible = "samsung,exynos-usi-v2";
  1235. reg = <0x0 0x10411024 0x4>;
  1236. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1237. status = "disabled";
  1238. };
  1239.  
  1240. /* USI_04_I2C */
  1241. usi_4_i2c: usi@10411028 {
  1242. compatible = "samsung,exynos-usi-v2";
  1243. reg = <0x0 0x10411028 0x4>;
  1244. /* usi_mode_v2 = "i2c" */
  1245. status = "disabled";
  1246. };
  1247.  
  1248. /* USI_05 */
  1249. usi_5: usi@1041102C {
  1250. compatible = "samsung,exynos-usi-v2";
  1251. reg = <0x0 0x1041102c 0x4>;
  1252. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1253. status = "disabled";
  1254. };
  1255.  
  1256. /* USI_05_I2C */
  1257. usi_5_i2c: usi@10411030 {
  1258. compatible = "samsung,exynos-usi-v2";
  1259. reg = <0x0 0x10411030 0x4>;
  1260. /* usi_mode_v2 = "i2c" */
  1261. status = "disabled";
  1262. };
  1263.  
  1264. /* USI_06 */
  1265. usi_6: usi@1081101C {
  1266. compatible = "samsung,exynos-usi-v2";
  1267. reg = <0x0 0x1081101c 0x4>;
  1268. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1269. status = "disabled";
  1270. };
  1271.  
  1272. /* USI_06_I2C */
  1273. usi_6_i2c: usi@10811020 {
  1274. compatible = "samsung,exynos-usi-v2";
  1275. reg = <0x0 0x10811020 0x4>;
  1276. /* usi_mode_v2 = "i2c" */
  1277. status = "disabled";
  1278. };
  1279.  
  1280. /* USI_07 */
  1281. usi_7: usi@10811024 {
  1282. compatible = "samsung,exynos-usi-v2";
  1283. reg = <0x0 0x10811024 0x4>;
  1284. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1285. status = "disabled";
  1286. };
  1287.  
  1288. /* USI_07_I2C */
  1289. usi_7_i2c: usi@10811028 {
  1290. compatible = "samsung,exynos-usi-v2";
  1291. reg = <0x0 0x10811028 0x4>;
  1292. /* usi_mode_v2 = "i2c" */
  1293. status = "disabled";
  1294. };
  1295.  
  1296. /* USI_08 */
  1297. usi_8: usi@1081102C {
  1298. compatible = "samsung,exynos-usi-v2";
  1299. reg = <0x0 0x1081102c 0x4>;
  1300. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1301. status = "disabled";
  1302. };
  1303.  
  1304. /* USI_08_I2C */
  1305. usi_8_i2c: usi@10811030 {
  1306. compatible = "samsung,exynos-usi-v2";
  1307. reg = <0x0 0x10811030 0x4>;
  1308. /* usi_mode_v2 = "i2c" */
  1309. status = "disabled";
  1310. };
  1311.  
  1312. /* USI_09 */
  1313. usi_9: usi@10811034 {
  1314. compatible = "samsung,exynos-usi-v2";
  1315. reg = <0x0 0x10811034 0x4>;
  1316. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1317. status = "disabled";
  1318. };
  1319.  
  1320. /* USI_09_I2C */
  1321. usi_9_i2c: usi@10811038 {
  1322. compatible = "samsung,exynos-usi-v2";
  1323. reg = <0x0 0x10811038 0x4>;
  1324. /* usi_mode_v2 = "i2c" */
  1325. status = "disabled";
  1326. };
  1327.  
  1328. /* USI_10 */
  1329. usi_10: usi@1081103C {
  1330. compatible = "samsung,exynos-usi-v2";
  1331. reg = <0x0 0x1081103c 0x4>;
  1332. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1333. status = "disabled";
  1334. };
  1335.  
  1336. /* USI_10_I2C */
  1337. usi_10_i2c: usi@10811040 {
  1338. compatible = "samsung,exynos-usi-v2";
  1339. reg = <0x0 0x10811040 0x4>;
  1340. /* usi_mode_v2 = "i2c" */
  1341. status = "disabled";
  1342. };
  1343.  
  1344. /* USI_11 */
  1345. usi_11: usi@10811044 {
  1346. compatible = "samsung,exynos-usi-v2";
  1347. reg = <0x0 0x10811044 0x4>;
  1348. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1349. status = "disabled";
  1350. };
  1351.  
  1352. /* USI_11_I2C */
  1353. usi_11_i2c: usi@10811048 {
  1354. compatible = "samsung,exynos-usi-v2";
  1355. reg = <0x0 0x10811048 0x4>;
  1356. /* usi_mode_v2 = "i2c" */
  1357. status = "disabled";
  1358. };
  1359.  
  1360. /* USI_12 */
  1361. usi_12: usi@10411034 {
  1362. compatible = "samsung,exynos-usi-v2";
  1363. reg = <0x0 0x10411034 0x4>;
  1364. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1365. status = "disabled";
  1366. };
  1367.  
  1368. /* USI_12_I2C */
  1369. usi_12_i2c: usi@10411038 {
  1370. compatible = "samsung,exynos-usi-v2";
  1371. reg = <0x0 0x10411038 0x4>;
  1372. /* usi_mode_v2 = "i2c" */
  1373. status = "disabled";
  1374. };
  1375.  
  1376. /* USI_13 */
  1377. usi_13: usi@1041103C {
  1378. compatible = "samsung,exynos-usi-v2";
  1379. reg = <0x0 0x1041103c 0x4>;
  1380. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1381. status = "disabled";
  1382. };
  1383.  
  1384. /* USI_13_I2C */
  1385. usi_13_i2c: usi@10411040 {
  1386. compatible = "samsung,exynos-usi-v2";
  1387. reg = <0x0 0x10411040 0x4>;
  1388. /* usi_mode_v2 = "i2c" */
  1389. status = "disabled";
  1390. };
  1391.  
  1392. /* USI_14 */
  1393. usi_14: usi@10411044 {
  1394. compatible = "samsung,exynos-usi-v2";
  1395. reg = <0x0 0x10411044 0x4>;
  1396. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1397. status = "disabled";
  1398. };
  1399.  
  1400. /* USI_14_I2C */
  1401. usi_14_i2c: usi@10411048 {
  1402. compatible = "samsung,exynos-usi-v2";
  1403. reg = <0x0 0x10411048 0x4>;
  1404. /* usi_mode_v2 = "i2c" */
  1405. status = "disabled";
  1406. };
  1407.  
  1408. /* USI_00_CMGP */
  1409. usi_00_cmgp: usi@14212000 {
  1410. compatible = "samsung,exynos-usi-v2";
  1411. reg = <0x0 0x14212000 0x4>;
  1412. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1413. status = "disabled";
  1414. };
  1415.  
  1416. /* USI_00_CMGP_I2C */
  1417. usi_00_cmgp_i2c: usi@14212004 {
  1418. compatible = "samsung,exynos-usi-v2";
  1419. reg = <0x0 0x14212004 0x4>;
  1420. /* usi_mode_v2 = "i2c" */
  1421. status = "disabled";
  1422. };
  1423.  
  1424. /* USI_01_CMGP */
  1425. usi_01_cmgp: usi@14212010 {
  1426. compatible = "samsung,exynos-usi-v2";
  1427. reg = <0x0 0x14212010 0x4>;
  1428. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1429. status = "disabled";
  1430. };
  1431.  
  1432. /* USI_01_CMGP_I2C */
  1433. usi_01_cmgp_i2c: usi@14212014 {
  1434. compatible = "samsung,exynos-usi-v2";
  1435. reg = <0x0 0x14212014 0x4>;
  1436. /* usi_mode_v2 = "i2c" */
  1437. status = "disabled";
  1438. };
  1439.  
  1440. /* USI_02_CMGP */
  1441. usi_02_cmgp: usi@14212020 {
  1442. compatible = "samsung,exynos-usi-v2";
  1443. reg = <0x0 0x14212020 0x4>;
  1444. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1445. status = "disabled";
  1446. };
  1447.  
  1448. /* USI_02_CMGP_I2C */
  1449. usi_02_cmgp_i2c: usi@14212024 {
  1450. compatible = "samsung,exynos-usi-v2";
  1451. reg = <0x0 0x14212024 0x4>;
  1452. /* usi_mode_v2 = "i2c" */
  1453. status = "disabled";
  1454. };
  1455.  
  1456. /* USI_03_CMGP */
  1457. usi_03_cmgp: usi@14212030 {
  1458. compatible = "samsung,exynos-usi-v2";
  1459. reg = <0x0 0x14212030 0x4>;
  1460. /* usi_mode_v2 = "i2c" or "spi" or "uart" */
  1461. status = "disabled";
  1462. };
  1463.  
  1464. /* USI_03_CMGP_I2C */
  1465. usi_03_cmgp_i2c: usi@14212034 {
  1466. compatible = "samsung,exynos-usi-v2";
  1467. reg = <0x0 0x14212034 0x4>;
  1468. /* usi_mode_v2 = "i2c" */
  1469. status = "disabled";
  1470. };
  1471.  
  1472. /* USI_00_CHUB */
  1473. usi_00_chub: usi@13A13000 {
  1474. compatible = "samsung,exynos-usi-v2";
  1475. reg = <0x0 0x13a13000 0x4>;
  1476. /* usi_mode_v2 = "i2c" */
  1477. status = "disabled";
  1478. };
  1479.  
  1480. /* USI_00_CHUB_I2C */
  1481. usi_00_chub_i2c: usi@13A13008 {
  1482. compatible = "samsung,exynos-usi-v2";
  1483. reg = <0x0 0x13a13008 0x4>;
  1484. /* usi_mode_v2 = "i2c" */
  1485. status = "disabled";
  1486. };
  1487.  
  1488. /* USI_01_CHUB */
  1489. usi_01_chub: usi@13A13004 {
  1490. compatible = "samsung,exynos-usi-v2";
  1491. reg = <0x0 0x13a13004 0x4>;
  1492. /* usi_mode_v2 = "i2c" */
  1493. status = "disabled";
  1494. };
  1495.  
  1496. /* USI_01_CHUB_I2C */
  1497. usi_01_chub_i2c: usi@13A1300C {
  1498. compatible = "samsung,exynos-usi-v2";
  1499. reg = <0x0 0x13a1300c 0x4>;
  1500. /* usi_mode_v2 = "i2c" */
  1501. status = "disabled";
  1502. };
  1503.  
  1504. /* PERIC1 CAM0 */
  1505. hsi2c_0: hsi2c@10860000 {
  1506. compatible = "samsung,exynos5-hsi2c";
  1507. samsung,check-transdone-int;
  1508. default-clk = <200000000>;
  1509. reg = <0x0 0x10860000 0x1000>;
  1510. interrupts = <0 INTREQ__I2C_CAM0 0>;
  1511. #address-cells = <1>;
  1512. #size-cells = <0>;
  1513. pinctrl-names = "default";
  1514. pinctrl-0 = <&hsi2c0_bus>;
  1515. clocks = <&clock I2C_CAM0>, <&clock GATE_I2C_CAM0>;
  1516. clock-names = "rate_hsi2c", "gate_hsi2c";
  1517. samsung,scl-clk-stretching;
  1518. samsung,usi-i2c-v2;
  1519. gpio_scl= <&gpc0 0 0x1>;
  1520. gpio_sda= <&gpc0 1 0x1>;
  1521. status = "disabled";
  1522. };
  1523.  
  1524. /* PERI1 CAM1 */
  1525. hsi2c_1: hsi2c@10870000 {
  1526. compatible = "samsung,exynos5-hsi2c";
  1527. samsung,check-transdone-int;
  1528. default-clk = <200000000>;
  1529. reg = <0x0 0x10870000 0x1000>;
  1530. interrupts = <0 INTREQ__I2C_CAM1 0>;
  1531. #address-cells = <1>;
  1532. #size-cells = <0>;
  1533. pinctrl-names = "default";
  1534. pinctrl-0 = <&hsi2c1_bus>;
  1535. clocks = <&clock I2C_CAM1>, <&clock GATE_I2C_CAM1>;
  1536. clock-names = "rate_hsi2c", "gate_hsi2c";
  1537. samsung,scl-clk-stretching;
  1538. samsung,usi-i2c-v2;
  1539. gpio_scl= <&gpc0 2 0x1>;
  1540. gpio_sda= <&gpc0 3 0x1>;
  1541. status = "disabled";
  1542. };
  1543.  
  1544. /* PERI1 CAM2 */
  1545. hsi2c_2: hsi2c@10880000 {
  1546. compatible = "samsung,exynos5-hsi2c";
  1547. samsung,check-transdone-int;
  1548. default-clk = <200000000>;
  1549. reg = <0x0 0x10880000 0x1000>;
  1550. interrupts = <0 INTREQ__I2C_CAM2 0>;
  1551. #address-cells = <1>;
  1552. #size-cells = <0>;
  1553. pinctrl-names = "default";
  1554. pinctrl-0 = <&hsi2c2_bus>;
  1555. clocks = <&clock I2C_CAM2>, <&clock GATE_I2C_CAM2>;
  1556. clock-names = "rate_hsi2c", "gate_hsi2c";
  1557. samsung,scl-clk-stretching;
  1558. samsung,usi-i2c-v2;
  1559. gpio_scl= <&gpc0 4 0x1>;
  1560. gpio_sda= <&gpc0 5 0x1>;
  1561. status = "disabled";
  1562. };
  1563.  
  1564. /* PERI1 CAM3 */
  1565. hsi2c_3: hsi2c@10890000 {
  1566. compatible = "samsung,exynos5-hsi2c";
  1567. samsung,check-transdone-int;
  1568. default-clk = <200000000>;
  1569. reg = <0x0 0x10890000 0x1000>;
  1570. interrupts = <0 INTREQ__I2C_CAM3 0>;
  1571. #address-cells = <1>;
  1572. #size-cells = <0>;
  1573. pinctrl-names = "default";
  1574. pinctrl-0 = <&hsi2c3_bus>;
  1575. clocks = <&clock I2C_CAM3>, <&clock GATE_I2C_CAM3>;
  1576. clock-names = "rate_hsi2c", "gate_hsi2c";
  1577. samsung,scl-clk-stretching;
  1578. samsung,usi-i2c-v2;
  1579. gpio_scl= <&gpc0 6 0x1>;
  1580. gpio_sda= <&gpc0 7 0x1>;
  1581. status = "disabled";
  1582. };
  1583.  
  1584. /* USI00_USI */
  1585. hsi2c_4: hsi2c@10450000 {
  1586. compatible = "samsung,exynos5-hsi2c";
  1587. samsung,check-transdone-int;
  1588. default-clk = <200000000>;
  1589. reg = <0x0 0x10450000 0x1000>;
  1590. interrupts = <0 INTREQ__USI00_USI 0>;
  1591. #address-cells = <1>;
  1592. #size-cells = <0>;
  1593. pinctrl-names = "default";
  1594. pinctrl-0 = <&hsi2c4_bus>;
  1595. clocks = <&clock USI00>, <&clock GATE_USI00>;
  1596. clock-names = "rate_hsi2c", "gate_hsi2c";
  1597. samsung,scl-clk-stretching;
  1598. samsung,usi-i2c-v2;
  1599. gpio_scl= <&gpp0 0 0x1>;
  1600. gpio_sda= <&gpp0 1 0x1>;
  1601. status = "disabled";
  1602. };
  1603.  
  1604. /* USI00_USI_I2C */
  1605. hsi2c_5: hsi2c@10460000 {
  1606. compatible = "samsung,exynos5-hsi2c";
  1607. samsung,check-transdone-int;
  1608. default-clk = <200000000>;
  1609. reg = <0x0 0x10460000 0x1000>;
  1610. interrupts = <0 INTREQ__USI00_I2C 0>;
  1611. #address-cells = <1>;
  1612. #size-cells = <0>;
  1613. pinctrl-names = "default";
  1614. pinctrl-0 = <&hsi2c5_bus>;
  1615. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI00_I2C>;
  1616. clock-names = "rate_hsi2c", "gate_hsi2c";
  1617. samsung,scl-clk-stretching;
  1618. samsung,usi-i2c-v2;
  1619. gpio_scl= <&gpp0 2 0x1>;
  1620. gpio_sda= <&gpp0 3 0x1>;
  1621. status = "disabled";
  1622. };
  1623.  
  1624. /* USI01_USI */
  1625. hsi2c_6: hsi2c@10470000 {
  1626. compatible = "samsung,exynos5-hsi2c";
  1627. samsung,check-transdone-int;
  1628. default-clk = <200000000>;
  1629. reg = <0x0 0x10470000 0x1000>;
  1630. interrupts = <0 INTREQ__USI01_USI 0>;
  1631. #address-cells = <1>;
  1632. #size-cells = <0>;
  1633. pinctrl-names = "default";
  1634. pinctrl-0 = <&hsi2c6_bus>;
  1635. clocks = <&clock USI01>, <&clock GATE_USI01>;
  1636. clock-names = "rate_hsi2c", "gate_hsi2c";
  1637. samsung,scl-clk-stretching;
  1638. samsung,usi-i2c-v2;
  1639. gpio_scl= <&gpp0 4 0x1>;
  1640. gpio_sda= <&gpp0 5 0x1>;
  1641. status = "disabled";
  1642. };
  1643.  
  1644. /* USI01_USI_I2C */
  1645. hsi2c_7: hsi2c@10480000 {
  1646. compatible = "samsung,exynos5-hsi2c";
  1647. samsung,check-transdone-int;
  1648. default-clk = <200000000>;
  1649. reg = <0x0 0x10480000 0x1000>;
  1650. interrupts = <0 INTREQ__USI01_I2C 0>;
  1651. #address-cells = <1>;
  1652. #size-cells = <0>;
  1653. pinctrl-names = "default";
  1654. pinctrl-0 = <&hsi2c7_bus>;
  1655. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI01_I2C>;
  1656. clock-names = "rate_hsi2c", "gate_hsi2c";
  1657. samsung,scl-clk-stretching;
  1658. samsung,usi-i2c-v2;
  1659. gpio_scl= <&gpp0 6 0x1>;
  1660. gpio_sda= <&gpp0 7 0x1>;
  1661. status = "disabled";
  1662. };
  1663.  
  1664. /* USI02_USI */
  1665. hsi2c_8: hsi2c@10490000 {
  1666. compatible = "samsung,exynos5-hsi2c";
  1667. samsung,check-transdone-int;
  1668. default-clk = <200000000>;
  1669. reg = <0x0 0x10490000 0x1000>;
  1670. interrupts = <0 INTREQ__USI02_USI 0>;
  1671. #address-cells = <1>;
  1672. #size-cells = <0>;
  1673. pinctrl-names = "default";
  1674. pinctrl-0 = <&hsi2c8_bus>;
  1675. clocks = <&clock USI02>, <&clock GATE_USI02>;
  1676. clock-names = "rate_hsi2c", "gate_hsi2c";
  1677. samsung,scl-clk-stretching;
  1678. samsung,usi-i2c-v2;
  1679. gpio_scl= <&gpp1 0 0x1>;
  1680. gpio_sda= <&gpp1 1 0x1>;
  1681. status = "disabled";
  1682. };
  1683.  
  1684. /* USI02_USI_I2C */
  1685. hsi2c_9: hsi2c@104A0000 {
  1686. compatible = "samsung,exynos5-hsi2c";
  1687. samsung,check-transdone-int;
  1688. default-clk = <200000000>;
  1689. reg = <0x0 0x104a0000 0x1000>;
  1690. interrupts = <0 INTREQ__USI02_I2C 0>;
  1691. #address-cells = <1>;
  1692. #size-cells = <0>;
  1693. pinctrl-names = "default";
  1694. pinctrl-0 = <&hsi2c9_bus>;
  1695. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI02_I2C>;
  1696. clock-names = "rate_hsi2c", "gate_hsi2c";
  1697. samsung,scl-clk-stretching;
  1698. samsung,usi-i2c-v2;
  1699. gpio_scl= <&gpp1 2 0x1>;
  1700. gpio_sda= <&gpp1 3 0x1>;
  1701. status = "disabled";
  1702. };
  1703.  
  1704. /* USI03_USI */
  1705. hsi2c_10: hsi2c@104B0000 {
  1706. compatible = "samsung,exynos5-hsi2c";
  1707. samsung,check-transdone-int;
  1708. default-clk = <200000000>;
  1709. reg = <0x0 0x104B0000 0x1000>;
  1710. interrupts = <0 INTREQ__USI03_USI 0>;
  1711. #address-cells = <1>;
  1712. #size-cells = <0>;
  1713. pinctrl-names = "default";
  1714. pinctrl-0 = <&hsi2c10_bus>;
  1715. clocks = <&clock USI03>, <&clock GATE_USI03>;
  1716. clock-names = "rate_hsi2c", "gate_hsi2c";
  1717. samsung,scl-clk-stretching;
  1718. samsung,usi-i2c-v2;
  1719. gpio_scl= <&gpp1 4 0x1>;
  1720. gpio_sda= <&gpp1 5 0x1>;
  1721. status = "disabled";
  1722. };
  1723.  
  1724. /* USI03_USI_I2C */
  1725. hsi2c_11: hsi2c@104C0000 {
  1726. compatible = "samsung,exynos5-hsi2c";
  1727. samsung,check-transdone-int;
  1728. default-clk = <200000000>;
  1729. reg = <0x0 0x104C0000 0x1000>;
  1730. interrupts = <0 INTREQ__USI03_I2C 0>;
  1731. #address-cells = <1>;
  1732. #size-cells = <0>;
  1733. pinctrl-names = "default";
  1734. pinctrl-0 = <&hsi2c11_bus>;
  1735. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI03_I2C>;
  1736. clock-names = "rate_hsi2c", "gate_hsi2c";
  1737. samsung,scl-clk-stretching;
  1738. samsung,usi-i2c-v2;
  1739. gpio_scl= <&gpp1 6 0x1>;
  1740. gpio_sda= <&gpp1 7 0x1>;
  1741. status = "disabled";
  1742. };
  1743.  
  1744. /* USI04_USI */
  1745. hsi2c_12: hsi2c@104D0000 {
  1746. compatible = "samsung,exynos5-hsi2c";
  1747. samsung,check-transdone-int;
  1748. default-clk = <200000000>;
  1749. reg = <0x0 0x104D0000 0x1000>;
  1750. interrupts = <0 INTREQ__USI04_USI 0>;
  1751. #address-cells = <1>;
  1752. #size-cells = <0>;
  1753. pinctrl-names = "default";
  1754. pinctrl-0 = <&hsi2c12_bus>;
  1755. clocks = <&clock USI04>, <&clock GATE_USI04>;
  1756. clock-names = "rate_hsi2c", "gate_hsi2c";
  1757. samsung,scl-clk-stretching;
  1758. samsung,usi-i2c-v2;
  1759. gpio_scl= <&gpp2 0 0x1>;
  1760. gpio_sda= <&gpp2 1 0x1>;
  1761. status = "disabled";
  1762. };
  1763.  
  1764. /* USI04_USI_I2C */
  1765. hsi2c_13: hsi2c@104E0000 {
  1766. compatible = "samsung,exynos5-hsi2c";
  1767. samsung,check-transdone-int;
  1768. default-clk = <200000000>;
  1769. reg = <0x0 0x104E0000 0x1000>;
  1770. interrupts = <0 INTREQ__USI04_I2C 0>;
  1771. #address-cells = <1>;
  1772. #size-cells = <0>;
  1773. pinctrl-names = "default";
  1774. pinctrl-0 = <&hsi2c13_bus>;
  1775. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI04_I2C>;
  1776. clock-names = "rate_hsi2c", "gate_hsi2c";
  1777. samsung,scl-clk-stretching;
  1778. samsung,usi-i2c-v2;
  1779. gpio_scl= <&gpp2 2 0x1>;
  1780. gpio_sda= <&gpp2 3 0x1>;
  1781. status = "disabled";
  1782. };
  1783.  
  1784. /* USI05_USI */
  1785. hsi2c_14: hsi2c@104F0000 {
  1786. compatible = "samsung,exynos5-hsi2c";
  1787. samsung,check-transdone-int;
  1788. default-clk = <200000000>;
  1789. reg = <0x0 0x104F0000 0x1000>;
  1790. interrupts = <0 INTREQ__USI05_USI 0>;
  1791. #address-cells = <1>;
  1792. #size-cells = <0>;
  1793. pinctrl-names = "default";
  1794. pinctrl-0 = <&hsi2c14_bus>;
  1795. clocks = <&clock USI05>, <&clock GATE_USI05>;
  1796. clock-names = "rate_hsi2c", "gate_hsi2c";
  1797. samsung,scl-clk-stretching;
  1798. samsung,usi-i2c-v2;
  1799. gpio_scl= <&gpp2 4 0x1>;
  1800. gpio_sda= <&gpp2 5 0x1>;
  1801. status = "disabled";
  1802. };
  1803.  
  1804. /* USI05_USI_I2C */
  1805. hsi2c_15: hsi2c@10500000 {
  1806. compatible = "samsung,exynos5-hsi2c";
  1807. samsung,check-transdone-int;
  1808. default-clk = <200000000>;
  1809. reg = <0x0 0x10500000 0x1000>;
  1810. interrupts = <0 INTREQ__USI05_I2C 0>;
  1811. #address-cells = <1>;
  1812. #size-cells = <0>;
  1813. pinctrl-names = "default";
  1814. pinctrl-0 = <&hsi2c15_bus>;
  1815. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI05_I2C>;
  1816. clock-names = "rate_hsi2c", "gate_hsi2c";
  1817. samsung,scl-clk-stretching;
  1818. samsung,usi-i2c-v2;
  1819. gpio_scl= <&gpp2 6 0x1>;
  1820. gpio_sda= <&gpp2 7 0x1>;
  1821. status = "disabled";
  1822. };
  1823.  
  1824. /* USI06_USI */
  1825. hsi2c_16: hsi2c@108A0000 {
  1826. compatible = "samsung,exynos5-hsi2c";
  1827. samsung,check-transdone-int;
  1828. default-clk = <200000000>;
  1829. reg = <0x0 0x108A0000 0x1000>;
  1830. interrupts = <0 INTREQ__USI06_USI 0>;
  1831. #address-cells = <1>;
  1832. #size-cells = <0>;
  1833. pinctrl-names = "default";
  1834. pinctrl-0 = <&hsi2c16_bus>;
  1835. clocks = <&clock USI06>, <&clock GATE_USI06>;
  1836. clock-names = "rate_hsi2c", "gate_hsi2c";
  1837. samsung,scl-clk-stretching;
  1838. samsung,usi-i2c-v2;
  1839. gpio_scl= <&gpp4 0 0x1>;
  1840. gpio_sda= <&gpp4 1 0x1>;
  1841. status = "disabled";
  1842. };
  1843.  
  1844. /* USI06_USI_I2C */
  1845. hsi2c_17: hsi2c@108B0000 {
  1846. compatible = "samsung,exynos5-hsi2c";
  1847. samsung,check-transdone-int;
  1848. default-clk = <200000000>;
  1849. reg = <0x0 0x108B0000 0x1000>;
  1850. interrupts = <0 INTREQ__USI06_I2C 0>;
  1851. #address-cells = <1>;
  1852. #size-cells = <0>;
  1853. pinctrl-names = "default";
  1854. pinctrl-0 = <&hsi2c17_bus>;
  1855. clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI06_I2C>;
  1856. clock-names = "rate_hsi2c", "gate_hsi2c";
  1857. samsung,scl-clk-stretching;
  1858. samsung,usi-i2c-v2;
  1859. gpio_scl= <&gpp4 2 0x1>;
  1860. gpio_sda= <&gpp4 3 0x1>;
  1861. status = "disabled";
  1862. };
  1863.  
  1864. /* USI07_USI */
  1865. hsi2c_18: hsi2c@108C0000 {
  1866. compatible = "samsung,exynos5-hsi2c";
  1867. samsung,check-transdone-int;
  1868. default-clk = <200000000>;
  1869. reg = <0x0 0x108C0000 0x1000>;
  1870. interrupts = <0 INTREQ__USI07_USI 0>;
  1871. #address-cells = <1>;
  1872. #size-cells = <0>;
  1873. pinctrl-names = "default";
  1874. pinctrl-0 = <&hsi2c18_bus>;
  1875. clocks = <&clock USI07>, <&clock GATE_USI07>;
  1876. clock-names = "rate_hsi2c", "gate_hsi2c";
  1877. samsung,scl-clk-stretching;
  1878. samsung,usi-i2c-v2;
  1879. gpio_scl= <&gpp4 4 0x1>;
  1880. gpio_sda= <&gpp4 5 0x1>;
  1881. status = "disabled";
  1882. };
  1883.  
  1884. /* USI07_USI_I2C */
  1885. hsi2c_19: hsi2c@108D0000 {
  1886. compatible = "samsung,exynos5-hsi2c";
  1887. samsung,check-transdone-int;
  1888. default-clk = <200000000>;
  1889. reg = <0x0 0x108D0000 0x1000>;
  1890. interrupts = <0 INTREQ__USI07_I2C 0>;
  1891. #address-cells = <1>;
  1892. #size-cells = <0>;
  1893. pinctrl-names = "default";
  1894. pinctrl-0 = <&hsi2c19_bus>;
  1895. clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI07_I2C>;
  1896. clock-names = "rate_hsi2c", "gate_hsi2c";
  1897. samsung,scl-clk-stretching;
  1898. samsung,usi-i2c-v2;
  1899. gpio_scl= <&gpp4 6 0x1>;
  1900. gpio_sda= <&gpp4 7 0x1>;
  1901. status = "disabled";
  1902. };
  1903.  
  1904. /* USI08_USI */
  1905. hsi2c_20: hsi2c@108E0000 {
  1906. compatible = "samsung,exynos5-hsi2c";
  1907. samsung,check-transdone-int;
  1908. default-clk = <200000000>;
  1909. reg = <0x0 0x108E0000 0x1000>;
  1910. interrupts = <0 INTREQ__USI08_USI 0>;
  1911. #address-cells = <1>;
  1912. #size-cells = <0>;
  1913. pinctrl-names = "default";
  1914. pinctrl-0 = <&hsi2c20_bus>;
  1915. clocks = <&clock USI08>, <&clock GATE_USI08>;
  1916. clock-names = "rate_hsi2c", "gate_hsi2c";
  1917. samsung,scl-clk-stretching;
  1918. samsung,usi-i2c-v2;
  1919. gpio_scl= <&gpp5 0 0x1>;
  1920. gpio_sda= <&gpp5 1 0x1>;
  1921. status = "disabled";
  1922. };
  1923.  
  1924. /* USI08_USI_I2C */
  1925. hsi2c_21: hsi2c@108F0000 {
  1926. compatible = "samsung,exynos5-hsi2c";
  1927. samsung,check-transdone-int;
  1928. default-clk = <200000000>;
  1929. reg = <0x0 0x108F0000 0x1000>;
  1930. interrupts = <0 INTREQ__USI08_I2C 0>;
  1931. #address-cells = <1>;
  1932. #size-cells = <0>;
  1933. pinctrl-names = "default";
  1934. pinctrl-0 = <&hsi2c21_bus>;
  1935. clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI08_I2C>;
  1936. clock-names = "rate_hsi2c", "gate_hsi2c";
  1937. samsung,scl-clk-stretching;
  1938. samsung,usi-i2c-v2;
  1939. gpio_scl= <&gpp5 2 0x1>;
  1940. gpio_sda= <&gpp5 3 0x1>;
  1941. status = "disabled";
  1942. };
  1943.  
  1944. /* USI09_USI */
  1945. hsi2c_22: hsi2c@10900000 {
  1946. compatible = "samsung,exynos5-hsi2c";
  1947. samsung,check-transdone-int;
  1948. default-clk = <200000000>;
  1949. reg = <0x0 0x10900000 0x1000>;
  1950. interrupts = <0 INTREQ__USI09_USI 0>;
  1951. #address-cells = <1>;
  1952. #size-cells = <0>;
  1953. pinctrl-names = "default";
  1954. pinctrl-0 = <&hsi2c22_bus>;
  1955. clocks = <&clock USI09>, <&clock GATE_USI09>;
  1956. clock-names = "rate_hsi2c", "gate_hsi2c";
  1957. samsung,scl-clk-stretching;
  1958. samsung,usi-i2c-v2;
  1959. gpio_scl= <&gpp5 4 0x1>;
  1960. gpio_sda= <&gpp5 5 0x1>;
  1961. status = "disabled";
  1962. };
  1963.  
  1964. /* USI09_USI_I2C */
  1965. hsi2c_23: hsi2c@10910000 {
  1966. compatible = "samsung,exynos5-hsi2c";
  1967. samsung,check-transdone-int;
  1968. default-clk = <200000000>;
  1969. reg = <0x0 0x10910000 0x1000>;
  1970. interrupts = <0 INTREQ__USI09_I2C 0>;
  1971. #address-cells = <1>;
  1972. #size-cells = <0>;
  1973. pinctrl-names = "default";
  1974. pinctrl-0 = <&hsi2c23_bus>;
  1975. clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI09_I2C>;
  1976. clock-names = "rate_hsi2c", "gate_hsi2c";
  1977. samsung,scl-clk-stretching;
  1978. samsung,usi-i2c-v2;
  1979. gpio_scl= <&gpp5 6 0x1>;
  1980. gpio_sda= <&gpp5 7 0x1>;
  1981. status = "disabled";
  1982. };
  1983.  
  1984. /* USI10_USI */
  1985. hsi2c_24: hsi2c@10920000 {
  1986. compatible = "samsung,exynos5-hsi2c";
  1987. samsung,check-transdone-int;
  1988. default-clk = <200000000>;
  1989. reg = <0x0 0x10920000 0x1000>;
  1990. interrupts = <0 INTREQ__USI10_USI 0>;
  1991. #address-cells = <1>;
  1992. #size-cells = <0>;
  1993. pinctrl-names = "default";
  1994. pinctrl-0 = <&hsi2c24_bus>;
  1995. clocks = <&clock USI10>, <&clock GATE_USI10>;
  1996. clock-names = "rate_hsi2c", "gate_hsi2c";
  1997. samsung,scl-clk-stretching;
  1998. samsung,usi-i2c-v2;
  1999. gpio_scl= <&gpp6 0 0x1>;
  2000. gpio_sda= <&gpp6 1 0x1>;
  2001. status = "disabled";
  2002. };
  2003.  
  2004. /* USI10_USI_I2C */
  2005. hsi2c_25: hsi2c@10930000 {
  2006. compatible = "samsung,exynos5-hsi2c";
  2007. samsung,check-transdone-int;
  2008. default-clk = <200000000>;
  2009. reg = <0x0 0x10930000 0x1000>;
  2010. interrupts = <0 INTREQ__USI10_I2C 0>;
  2011. #address-cells = <1>;
  2012. #size-cells = <0>;
  2013. pinctrl-names = "default";
  2014. pinctrl-0 = <&hsi2c25_bus>;
  2015. clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI10_I2C>;
  2016. clock-names = "rate_hsi2c", "gate_hsi2c";
  2017. samsung,scl-clk-stretching;
  2018. samsung,usi-i2c-v2;
  2019. gpio_scl= <&gpp6 2 0x1>;
  2020. gpio_sda= <&gpp6 3 0x1>;
  2021. status = "disabled";
  2022. };
  2023.  
  2024. /* USI11_USI */
  2025. hsi2c_26: hsi2c@10940000 {
  2026. compatible = "samsung,exynos5-hsi2c";
  2027. samsung,check-transdone-int;
  2028. default-clk = <200000000>;
  2029. reg = <0x0 0x10940000 0x1000>;
  2030. interrupts = <0 INTREQ__USI11_USI 0>;
  2031. #address-cells = <1>;
  2032. #size-cells = <0>;
  2033. pinctrl-names = "default";
  2034. pinctrl-0 = <&hsi2c26_bus>;
  2035. clocks = <&clock USI11>, <&clock GATE_USI11>;
  2036. clock-names = "rate_hsi2c", "gate_hsi2c";
  2037. samsung,scl-clk-stretching;
  2038. samsung,usi-i2c-v2;
  2039. gpio_scl= <&gpg3 3 0x1>;
  2040. gpio_sda= <&gpg3 4 0x1>;
  2041. status = "disabled";
  2042. };
  2043.  
  2044. /* USI11_USI_I2C */
  2045. hsi2c_27: hsi2c@10950000 {
  2046. compatible = "samsung,exynos5-hsi2c";
  2047. samsung,check-transdone-int;
  2048. default-clk = <200000000>;
  2049. reg = <0x0 0x10950000 0x1000>;
  2050. interrupts = <0 INTREQ__USI11_I2C 0>;
  2051. #address-cells = <1>;
  2052. #size-cells = <0>;
  2053. pinctrl-names = "default";
  2054. pinctrl-0 = <&hsi2c27_bus>;
  2055. clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI11_I2C>;
  2056. clock-names = "rate_hsi2c", "gate_hsi2c";
  2057. samsung,scl-clk-stretching;
  2058. samsung,usi-i2c-v2;
  2059. gpio_scl= <&gpg3 5 0x1>;
  2060. gpio_sda= <&gpg3 6 0x1>;
  2061. status = "disabled";
  2062. };
  2063.  
  2064. /* USI12_USI */
  2065. hsi2c_28: hsi2c@10520000 {
  2066. compatible = "samsung,exynos5-hsi2c";
  2067. samsung,check-transdone-int;
  2068. default-clk = <200000000>;
  2069. reg = <0x0 0x10520000 0x1000>;
  2070. interrupts = <0 INTREQ__USI12_USI 0>;
  2071. #address-cells = <1>;
  2072. #size-cells = <0>;
  2073. pinctrl-names = "default";
  2074. pinctrl-0 = <&hsi2c28_bus>;
  2075. clocks = <&clock USI12>, <&clock GATE_USI12>;
  2076. clock-names = "rate_hsi2c", "gate_hsi2c";
  2077. samsung,scl-clk-stretching;
  2078. samsung,usi-i2c-v2;
  2079. gpio_scl= <&gpg0 4 0x1>;
  2080. gpio_sda= <&gpg0 5 0x1>;
  2081. status = "disabled";
  2082. };
  2083.  
  2084. /* USI12_USI_I2C */
  2085. hsi2c_29: hsi2c@10530000 {
  2086. compatible = "samsung,exynos5-hsi2c";
  2087. samsung,check-transdone-int;
  2088. default-clk = <200000000>;
  2089. reg = <0x0 0x10530000 0x1000>;
  2090. interrupts = <0 INTREQ__USI12_I2C 0>;
  2091. #address-cells = <1>;
  2092. #size-cells = <0>;
  2093. pinctrl-names = "default";
  2094. pinctrl-0 = <&hsi2c29_bus>;
  2095. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI12_I2C>;
  2096. clock-names = "rate_hsi2c", "gate_hsi2c";
  2097. samsung,scl-clk-stretching;
  2098. samsung,usi-i2c-v2;
  2099. gpio_scl= <&gpg0 6 0x1>;
  2100. gpio_sda= <&gpg0 7 0x1>;
  2101. status = "disabled";
  2102. };
  2103.  
  2104. /* USI13_USI */
  2105. hsi2c_30: hsi2c@10540000 {
  2106. compatible = "samsung,exynos5-hsi2c";
  2107. samsung,check-transdone-int;
  2108. default-clk = <200000000>;
  2109. reg = <0x0 0x10540000 0x1000>;
  2110. interrupts = <0 INTREQ__USI13_USI 0>;
  2111. #address-cells = <1>;
  2112. #size-cells = <0>;
  2113. pinctrl-names = "default";
  2114. pinctrl-0 = <&hsi2c30_bus>;
  2115. clocks = <&clock USI13>, <&clock GATE_USI13>;
  2116. clock-names = "rate_hsi2c", "gate_hsi2c";
  2117. samsung,scl-clk-stretching;
  2118. samsung,usi-i2c-v2;
  2119. gpio_scl= <&gpg1 0 0x1>;
  2120. gpio_sda= <&gpg1 1 0x1>;
  2121. status = "disabled";
  2122. };
  2123.  
  2124. /* USI13_USI_I2C */
  2125. hsi2c_31: hsi2c@10550000 {
  2126. compatible = "samsung,exynos5-hsi2c";
  2127. samsung,check-transdone-int;
  2128. default-clk = <200000000>;
  2129. reg = <0x0 0x10550000 0x1000>;
  2130. interrupts = <0 INTREQ__USI13_I2C 0>;
  2131. #address-cells = <1>;
  2132. #size-cells = <0>;
  2133. pinctrl-names = "default";
  2134. pinctrl-0 = <&hsi2c31_bus>;
  2135. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI13_I2C>;
  2136. clock-names = "rate_hsi2c", "gate_hsi2c";
  2137. samsung,scl-clk-stretching;
  2138. samsung,usi-i2c-v2;
  2139. gpio_scl= <&gpg1 2 0x1>;
  2140. gpio_sda= <&gpg1 3 0x1>;
  2141. status = "disabled";
  2142. };
  2143.  
  2144. /* USI14_USI */
  2145. hsi2c_32: hsi2c@10560000 {
  2146. compatible = "samsung,exynos5-hsi2c";
  2147. samsung,check-transdone-int;
  2148. default-clk = <200000000>;
  2149. reg = <0x0 0x10560000 0x1000>;
  2150. interrupts = <0 INTREQ__USI14_USI 0>;
  2151. #address-cells = <1>;
  2152. #size-cells = <0>;
  2153. pinctrl-names = "default";
  2154. pinctrl-0 = <&hsi2c32_bus>;
  2155. clocks = <&clock USI14>, <&clock GATE_USI14>;
  2156. clock-names = "rate_hsi2c", "gate_hsi2c";
  2157. samsung,scl-clk-stretching;
  2158. samsung,usi-i2c-v2;
  2159. gpio_scl= <&gpg1 4 0x1>;
  2160. gpio_sda= <&gpg1 5 0x1>;
  2161. status = "disabled";
  2162. };
  2163.  
  2164. /* USI14_USI_I2C */
  2165. hsi2c_33: hsi2c@10570000 {
  2166. compatible = "samsung,exynos5-hsi2c";
  2167. samsung,check-transdone-int;
  2168. default-clk = <200000000>;
  2169. reg = <0x0 0x10570000 0x1000>;
  2170. interrupts = <0 INTREQ__USI14_I2C 0>;
  2171. #address-cells = <1>;
  2172. #size-cells = <0>;
  2173. pinctrl-names = "default";
  2174. pinctrl-0 = <&hsi2c33_bus>;
  2175. clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI14_I2C>;
  2176. clock-names = "rate_hsi2c", "gate_hsi2c";
  2177. samsung,scl-clk-stretching;
  2178. samsung,usi-i2c-v2;
  2179. gpio_scl= <&gpg1 6 0x1>;
  2180. gpio_sda= <&gpg1 7 0x1>;
  2181. status = "disabled";
  2182. };
  2183.  
  2184. /* USI_CMGP00 */
  2185. hsi2c_34: hsi2c@14300000 {
  2186. compatible = "samsung,exynos5-hsi2c";
  2187. samsung,check-transdone-int;
  2188. default-clk = <200000000>;
  2189. reg = <0x0 0x14300000 0x1000>;
  2190. interrupts = <0 INTREQ__USI_CMGP00 0>;
  2191. #address-cells = <1>;
  2192. #size-cells = <0>;
  2193. pinctrl-names = "default";
  2194. pinctrl-0 = <&hsi2c34_bus>;
  2195. clocks = <&clock USI_CMGP00>, <&clock GATE_USI_CMGP00>;
  2196. clock-names = "rate_hsi2c", "gate_hsi2c";
  2197. samsung,scl-clk-stretching;
  2198. samsung,usi-i2c-v2;
  2199. gpio_scl= <&gpm0 0 0x1>;
  2200. gpio_sda= <&gpm1 0 0x1>;
  2201. status = "disabled";
  2202. };
  2203.  
  2204. /* USI_CMGP00_I2C */
  2205. hsi2c_35: hsi2c@14310000 {
  2206. compatible = "samsung,exynos5-hsi2c";
  2207. samsung,check-transdone-int;
  2208. default-clk = <200000000>;
  2209. reg = <0x0 0x14310000 0x1000>;
  2210. interrupts = <0 INTREQ__I2C_CMGP00 0>;
  2211. #address-cells = <1>;
  2212. #size-cells = <0>;
  2213. pinctrl-names = "default";
  2214. pinctrl-0 = <&hsi2c35_bus>;
  2215. clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP00>;
  2216. clock-names = "rate_hsi2c", "gate_hsi2c";
  2217. samsung,scl-clk-stretching;
  2218. samsung,usi-i2c-v2;
  2219. gpio_scl= <&gpm2 0 0x1>;
  2220. gpio_sda= <&gpm3 0 0x1>;
  2221. status = "disabled";
  2222. };
  2223.  
  2224. /* USI_CMGP01 */
  2225. hsi2c_36: hsi2c@14320000 {
  2226. compatible = "samsung,exynos5-hsi2c";
  2227. samsung,check-transdone-int;
  2228. default-clk = <200000000>;
  2229. reg = <0x0 0x14320000 0x1000>;
  2230. interrupts = <0 INTREQ__USI_CMGP01 0>;
  2231. #address-cells = <1>;
  2232. #size-cells = <0>;
  2233. pinctrl-names = "default";
  2234. pinctrl-0 = <&hsi2c36_bus>;
  2235. clocks = <&clock USI_CMGP01>, <&clock GATE_USI_CMGP01>;
  2236. clock-names = "rate_hsi2c", "gate_hsi2c";
  2237. samsung,scl-clk-stretching;
  2238. samsung,usi-i2c-v2;
  2239. gpio_scl= <&gpm4 0 0x1>;
  2240. gpio_sda= <&gpm5 0 0x1>;
  2241. status = "disabled";
  2242. };
  2243.  
  2244. /* USI_CMGP01_I2C */
  2245. hsi2c_37: hsi2c@14330000 {
  2246. compatible = "samsung,exynos5-hsi2c";
  2247. samsung,check-transdone-int;
  2248. default-clk = <200000000>;
  2249. reg = <0x0 0x14330000 0x1000>;
  2250. interrupts = <0 INTREQ__I2C_CMGP01 0>;
  2251. #address-cells = <1>;
  2252. #size-cells = <0>;
  2253. pinctrl-names = "default";
  2254. pinctrl-0 = <&hsi2c37_bus>;
  2255. clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP01>;
  2256. clock-names = "rate_hsi2c", "gate_hsi2c";
  2257. samsung,scl-clk-stretching;
  2258. samsung,usi-i2c-v2;
  2259. gpio_scl= <&gpm6 0 0x1>;
  2260. gpio_sda= <&gpm7 0 0x1>;
  2261. status = "disabled";
  2262. };
  2263.  
  2264. /* USI_CMGP02 */
  2265. hsi2c_38: hsi2c@14340000 {
  2266. compatible = "samsung,exynos5-hsi2c";
  2267. samsung,check-transdone-int;
  2268. default-clk = <200000000>;
  2269. reg = <0x0 0x14340000 0x1000>;
  2270. interrupts = <0 INTREQ__USI_CMGP02 0>;
  2271. #address-cells = <1>;
  2272. #size-cells = <0>;
  2273. pinctrl-names = "default";
  2274. pinctrl-0 = <&hsi2c38_bus>;
  2275. clocks = <&clock USI_CMGP02>, <&clock GATE_USI_CMGP02>;
  2276. clock-names = "rate_hsi2c", "gate_hsi2c";
  2277. samsung,scl-clk-stretching;
  2278. samsung,usi-i2c-v2;
  2279. gpio_scl= <&gpm10 0 0x1>;
  2280. gpio_sda= <&gpm11 0 0x1>;
  2281. status = "disabled";
  2282. };
  2283.  
  2284. /* USI_CMGP02_I2C */
  2285. hsi2c_39: hsi2c@14350000 {
  2286. compatible = "samsung,exynos5-hsi2c";
  2287. samsung,check-transdone-int;
  2288. default-clk = <200000000>;
  2289. reg = <0x0 0x14350000 0x1000>;
  2290. interrupts = <0 INTREQ__I2C_CMGP02 0>;
  2291. #address-cells = <1>;
  2292. #size-cells = <0>;
  2293. pinctrl-names = "default";
  2294. pinctrl-0 = <&hsi2c39_bus>;
  2295. clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP02>;
  2296. clock-names = "rate_hsi2c", "gate_hsi2c";
  2297. samsung,scl-clk-stretching;
  2298. samsung,usi-i2c-v2;
  2299. gpio_scl= <&gpm12 0 0x1>;
  2300. gpio_sda= <&gpm13 0 0x1>;
  2301. status = "disabled";
  2302. };
  2303.  
  2304. /* USI_CMGP03 */
  2305. hsi2c_40: hsi2c@14360000 {
  2306. compatible = "samsung,exynos5-hsi2c";
  2307. samsung,check-transdone-int;
  2308. default-clk = <200000000>;
  2309. reg = <0x0 0x14360000 0x1000>;
  2310. interrupts = <0 INTREQ__USI_CMGP03 0>;
  2311. #address-cells = <1>;
  2312. #size-cells = <0>;
  2313. pinctrl-names = "default";
  2314. pinctrl-0 = <&hsi2c40_bus>;
  2315. clocks = <&clock USI_CMGP03>, <&clock GATE_USI_CMGP03>;
  2316. clock-names = "rate_hsi2c", "gate_hsi2c";
  2317. samsung,scl-clk-stretching;
  2318. samsung,usi-i2c-v2;
  2319. gpio_scl= <&gpm14 0 0x1>;
  2320. gpio_sda= <&gpm15 0 0x1>;
  2321. status = "disabled";
  2322. };
  2323.  
  2324. /* USI_CMGP03_I2C */
  2325. hsi2c_41: hsi2c@14370000 {
  2326. compatible = "samsung,exynos5-hsi2c";
  2327. samsung,check-transdone-int;
  2328. default-clk = <200000000>;
  2329. reg = <0x0 0x14370000 0x1000>;
  2330. interrupts = <0 INTREQ__I2C_CMGP03 0>;
  2331. #address-cells = <1>;
  2332. #size-cells = <0>;
  2333. pinctrl-names = "default";
  2334. pinctrl-0 = <&hsi2c41_bus>;
  2335. clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP03>;
  2336. clock-names = "rate_hsi2c", "gate_hsi2c";
  2337. samsung,scl-clk-stretching;
  2338. samsung,usi-i2c-v2;
  2339. gpio_scl= <&gpm16 0 0x1>;
  2340. gpio_sda= <&gpm17 0 0x1>;
  2341. status = "disabled";
  2342. };
  2343.  
  2344. /* USI_CHUB00 */
  2345. hsi2c_42: hsi2c@13AC0000 {
  2346. compatible = "samsung,exynos5-hsi2c";
  2347. samsung,check-transdone-int;
  2348. default-clk = <200000000>;
  2349. reg = <0x0 0x13ac0000 0x1000>;
  2350. interrupts = <0 INTREQ__USI_CHUB00 0>;
  2351. #address-cells = <1>;
  2352. #size-cells = <0>;
  2353. pinctrl-names = "default";
  2354. pinctrl-0 = <&hsi2c42_bus>;
  2355. clocks = <&clock CHUB_USI00>, <&clock GATE_USI_CHUB00>;
  2356. clock-names = "rate_hsi2c", "gate_hsi2c";
  2357. samsung,scl-clk-stretching;
  2358. samsung,usi-i2c-v2;
  2359. gpio_scl= <&gph0 0 0x1>;
  2360. gpio_sda= <&gph0 1 0x1>;
  2361. status = "disabled";
  2362. };
  2363.  
  2364. /* USI_CHUB00_I2C */
  2365. hsi2c_43: hsi2c@13AD0000 {
  2366. compatible = "samsung,exynos5-hsi2c";
  2367. samsung,check-transdone-int;
  2368. default-clk = <200000000>;
  2369. reg = <0x0 0x13ad0000 0x1000>;
  2370. interrupts = <0 INTREQ__I2C_CHUB00 0>;
  2371. #address-cells = <1>;
  2372. #size-cells = <0>;
  2373. pinctrl-names = "default";
  2374. pinctrl-0 = <&hsi2c43_bus>;
  2375. clocks = <&clock CHUB_USI_I2C>, <&clock GATE_I2C_CHUB00>;
  2376. clock-names = "rate_hsi2c", "gate_hsi2c";
  2377. samsung,scl-clk-stretching;
  2378. samsung,usi-i2c-v2;
  2379. gpio_scl= <&gph0 2 0x1>;
  2380. gpio_sda= <&gph0 3 0x1>;
  2381. status = "disabled";
  2382. };
  2383.  
  2384. /* USI_CHUB01 */
  2385. hsi2c_44: hsi2c@13AE0000 {
  2386. compatible = "samsung,exynos5-hsi2c";
  2387. samsung,check-transdone-int;
  2388. default-clk = <200000000>;
  2389. reg = <0x0 0x13ae0000 0x1000>;
  2390. interrupts = <0 INTREQ__USI_CHUB01 0>;
  2391. #address-cells = <1>;
  2392. #size-cells = <0>;
  2393. pinctrl-names = "default";
  2394. pinctrl-0 = <&hsi2c44_bus>;
  2395. clocks = <&clock CHUB_USI01>, <&clock GATE_USI_CHUB01>;
  2396. clock-names = "rate_hsi2c", "gate_hsi2c";
  2397. samsung,scl-clk-stretching;
  2398. samsung,usi-i2c-v2;
  2399. gpio_scl= <&gph0 4 0x1>;
  2400. gpio_sda= <&gph0 5 0x1>;
  2401. status = "disabled";
  2402. };
  2403.  
  2404. /* USI_CHUB01_I2C */
  2405. hsi2c_45: hsi2c@13AF0000 {
  2406. compatible = "samsung,exynos5-hsi2c";
  2407. samsung,check-transdone-int;
  2408. default-clk = <200000000>;
  2409. reg = <0x0 0x13af0000 0x1000>;
  2410. interrupts = <0 INTREQ__I2C_CHUB01 0>;
  2411. #address-cells = <1>;
  2412. #size-cells = <0>;
  2413. pinctrl-names = "default";
  2414. pinctrl-0 = <&hsi2c45_bus>;
  2415. clocks = <&clock CHUB_USI_I2C>, <&clock GATE_I2C_CHUB01>;
  2416. clock-names = "rate_hsi2c", "gate_hsi2c";
  2417. samsung,scl-clk-stretching;
  2418. samsung,usi-i2c-v2;
  2419. gpio_scl= <&gph0 6 0x1>;
  2420. gpio_sda= <&gph0 7 0x1>;
  2421. status = "disabled";
  2422. };
  2423.  
  2424. /* SPI USI_PERIC1_SPI_CAM0 */
  2425. spi_0: spi@10850000 {
  2426. compatible = "samsung,exynos-spi";
  2427. reg = <0x0 0x10850000 0x100>;
  2428. samsung,spi-fifosize = <256>;
  2429. interrupts = <0 INTREQ__SPI_CAM0 0>;
  2430. /*
  2431. dma-mode;
  2432. dmas = <&pdma0 25 &pdma0 24>;
  2433. */
  2434. dma-names = "tx", "rx";
  2435. swap-mode;
  2436. #address-cells = <1>;
  2437. #size-cells = <0>;
  2438. clocks = <&clock GATE_SPI_CAM0>, <&clock SPI_CAM0>;
  2439. clock-names = "spi", "spi_busclk0";
  2440. pinctrl-names = "default";
  2441. pinctrl-0 = <&spi0_bus>;
  2442. status = "disabled";
  2443. };
  2444.  
  2445. /* SPI USI_PERIC0_USI00_SPI */
  2446. spi_1: spi@10450000 {
  2447. compatible = "samsung,exynos-spi";
  2448. reg = <0x0 0x10450000 0x100>;
  2449. samsung,spi-fifosize = <64>;
  2450. interrupts = <0 INTREQ__USI00_USI 0>;
  2451. /*
  2452. dma-mode;
  2453. dmas = <&pdma0 1 &pdma0 0>;
  2454. */
  2455. dma-names = "tx", "rx";
  2456. swap-mode;
  2457. #address-cells = <1>;
  2458. #size-cells = <0>;
  2459. clocks = <&clock GATE_USI00>, <&clock USI00>;
  2460. clock-names = "spi", "spi_busclk0";
  2461. pinctrl-names = "default";
  2462. pinctrl-0 = <&spi1_bus>;
  2463. status = "disabled";
  2464. };
  2465.  
  2466. /* SPI USI_PERIC0_USI01_SPI */
  2467. spi_2: spi@10470000 {
  2468. compatible = "samsung,exynos-spi";
  2469. reg = <0x0 0x10470000 0x100>;
  2470. samsung,spi-fifosize = <64>;
  2471. interrupts = <0 INTREQ__USI01_USI 0>;
  2472. /*
  2473. dma-mode;
  2474. dmas = <&pdma0 3 &pdma0 2>;
  2475. */
  2476. dma-names = "tx", "rx";
  2477. swap-mode;
  2478. #address-cells = <1>;
  2479. #size-cells = <0>;
  2480. clocks = <&clock GATE_USI01>, <&clock USI01>;
  2481. clock-names = "spi", "spi_busclk0";
  2482. pinctrl-names = "default";
  2483. pinctrl-0 = <&spi2_bus>;
  2484. status = "disabled";
  2485. };
  2486.  
  2487. /* SPI USI_PERIC0_USI02_SPI */
  2488. spi_3: spi@10490000 {
  2489. compatible = "samsung,exynos-spi";
  2490. reg = <0x0 0x10490000 0x100>;
  2491. samsung,spi-fifosize = <64>;
  2492. interrupts = <0 INTREQ__USI02_USI 0>;
  2493. /*
  2494. dma-mode;
  2495. dmas = <&pdma0 5 &pdma0 4>;
  2496. */
  2497. dma-names = "tx", "rx";
  2498. swap-mode;
  2499. #address-cells = <1>;
  2500. #size-cells = <0>;
  2501. clocks = <&clock GATE_USI02>, <&clock USI02>;
  2502. clock-names = "spi", "spi_busclk0";
  2503. pinctrl-names = "default";
  2504. pinctrl-0 = <&spi3_bus>;
  2505. status = "disabled";
  2506. };
  2507.  
  2508. /* SPI USI_PERIC0_USI03_SPI */
  2509. spi_4: spi@104B0000 {
  2510. compatible = "samsung,exynos-spi";
  2511. reg = <0x0 0x104B0000 0x100>;
  2512. samsung,spi-fifosize = <64>;
  2513. interrupts = <0 INTREQ__USI03_USI 0>;
  2514. /*
  2515. dma-mode;
  2516. dmas = <&pdma0 7 &pdma0 6>;
  2517. */
  2518. dma-names = "tx", "rx";
  2519. swap-mode;
  2520. #address-cells = <1>;
  2521. #size-cells = <0>;
  2522. clocks = <&clock GATE_USI03>, <&clock USI03>;
  2523. clock-names = "spi", "spi_busclk0";
  2524. pinctrl-names = "default";
  2525. pinctrl-0 = <&spi4_bus>;
  2526. status = "disabled";
  2527. };
  2528.  
  2529. /* SPI USI_PERIC0_USI04_SPI */
  2530. spi_5: spi@104D0000 {
  2531. compatible = "samsung,exynos-spi";
  2532. reg = <0x0 0x104D0000 0x100>;
  2533. samsung,spi-fifosize = <64>;
  2534. interrupts = <0 INTREQ__USI04_USI 0>;
  2535. /*
  2536. dma-mode;
  2537. dmas = <&pdma0 9 &pdma0 8>;
  2538. */
  2539. dma-names = "tx", "rx";
  2540. swap-mode;
  2541. #address-cells = <1>;
  2542. #size-cells = <0>;
  2543. clocks = <&clock GATE_USI04>, <&clock USI04>;
  2544. clock-names = "spi", "spi_busclk0";
  2545. pinctrl-names = "default";
  2546. pinctrl-0 = <&spi5_bus>;
  2547. status = "disabled";
  2548. };
  2549.  
  2550. /* SPI USI_PERIC0_USI05_SPI */
  2551. spi_6: spi@104F0000 {
  2552. compatible = "samsung,exynos-spi";
  2553. reg = <0x0 0x104F0000 0x100>;
  2554. samsung,spi-fifosize = <64>;
  2555. interrupts = <0 INTREQ__USI05_USI 0>;
  2556. /*
  2557. dma-mode;
  2558. dmas = <&pdma0 11 &pdma0 10>;
  2559. */
  2560. dma-names = "tx", "rx";
  2561. swap-mode;
  2562. #address-cells = <1>;
  2563. #size-cells = <0>;
  2564. clocks = <&clock GATE_USI05>, <&clock USI05>;
  2565. clock-names = "spi", "spi_busclk0";
  2566. pinctrl-names = "default";
  2567. pinctrl-0 = <&spi6_bus>;
  2568. status = "disabled";
  2569. };
  2570.  
  2571. /* SPI USI_PERIC1_USI06_SPI */
  2572. spi_7: spi@108A0000 {
  2573. compatible = "samsung,exynos-spi";
  2574. reg = <0x0 0x108A0000 0x100>;
  2575. samsung,spi-fifosize = <64>;
  2576. interrupts = <0 INTREQ__USI06_USI 0>;
  2577. /*
  2578. dma-mode;
  2579. dmas = <&pdma0 15 &pdma0 14>;
  2580. */
  2581. dma-names = "tx", "rx";
  2582. swap-mode;
  2583. #address-cells = <1>;
  2584. #size-cells = <0>;
  2585. clocks = <&clock GATE_USI06>, <&clock USI06>;
  2586. clock-names = "spi", "spi_busclk0";
  2587. pinctrl-names = "default";
  2588. pinctrl-0 = <&spi7_bus>;
  2589. status = "disabled";
  2590. };
  2591.  
  2592. /* SPI USI_PERIC1_USI07_SPI */
  2593. spi_8: spi@108C0000 {
  2594. compatible = "samsung,exynos-spi";
  2595. reg = <0x0 0x108C0000 0x100>;
  2596. samsung,spi-fifosize = <64>;
  2597. interrupts = <0 INTREQ__USI07_USI 0>;
  2598. /*
  2599. dma-mode;
  2600. dmas = <&pdma0 17 &pdma0 16>;
  2601. */
  2602. dma-names = "tx", "rx";
  2603. swap-mode;
  2604. #address-cells = <1>;
  2605. #size-cells = <0>;
  2606. clocks = <&clock GATE_USI07>, <&clock USI07>;
  2607. clock-names = "spi", "spi_busclk0";
  2608. pinctrl-names = "default";
  2609. pinctrl-0 = <&spi8_bus>;
  2610. status = "disabled";
  2611. };
  2612.  
  2613. /* SPI USI_PERIC1_USI08_SPI */
  2614. spi_9: spi@108E0000 {
  2615. compatible = "samsung,exynos-spi";
  2616. reg = <0x0 0x108E0000 0x100>;
  2617. samsung,spi-fifosize = <256>;
  2618. interrupts = <0 INTREQ__USI08_USI 0>;
  2619. /*
  2620. dma-mode;
  2621. dmas = <&pdma0 19 &pdma0 18>;
  2622. */
  2623. dma-names = "tx", "rx";
  2624. swap-mode;
  2625. #address-cells = <1>;
  2626. #size-cells = <0>;
  2627. clocks = <&clock GATE_USI08>, <&clock USI08>;
  2628. clock-names = "spi", "spi_busclk0";
  2629. pinctrl-names = "default";
  2630. pinctrl-0 = <&spi9_bus>;
  2631. status = "disabled";
  2632. };
  2633.  
  2634. /* SPI USI_PERIC1_USI09_SPI */
  2635. spi_10: spi@10900000 {
  2636. compatible = "samsung,exynos-spi";
  2637. reg = <0x0 0x10900000 0x100>;
  2638. samsung,spi-fifosize = <256>;
  2639. interrupts = <0 INTREQ__USI09_USI 0>;
  2640. /*
  2641. dma-mode;
  2642. dmas = <&pdma0 21 &pdma0 20>;
  2643. */
  2644. dma-names = "tx", "rx";
  2645. swap-mode;
  2646. #address-cells = <1>;
  2647. #size-cells = <0>;
  2648. clocks = <&clock GATE_USI09>, <&clock USI09>;
  2649. clock-names = "spi", "spi_busclk0";
  2650. pinctrl-names = "default";
  2651. pinctrl-0 = <&spi10_bus>;
  2652. status = "disabled";
  2653. };
  2654.  
  2655. /* SPI USI_PERIC1_USI10_SPI */
  2656. spi_11: spi@10920000 {
  2657. compatible = "samsung,exynos-spi";
  2658. reg = <0x0 0x10920000 0x100>;
  2659. samsung,spi-fifosize = <256>;
  2660. interrupts = <0 INTREQ__USI10_USI 0>;
  2661. /*
  2662. dma-mode;
  2663. dmas = <&pdma0 23 &pdma0 22>;
  2664. */
  2665. dma-names = "tx", "rx";
  2666. swap-mode;
  2667. #address-cells = <1>;
  2668. #size-cells = <0>;
  2669. clocks = <&clock GATE_USI10>, <&clock USI10>;
  2670. clock-names = "spi", "spi_busclk0";
  2671. pinctrl-names = "default";
  2672. pinctrl-0 = <&spi11_bus>;
  2673. status = "disabled";
  2674. };
  2675.  
  2676. /* SPI USI_PERIC1_USI11_SPI */
  2677. spi_12: spi@10940000 {
  2678. compatible = "samsung,exynos-spi";
  2679. reg = <0x0 0x10940000 0x100>;
  2680. samsung,spi-fifosize = <64>;
  2681. interrupts = <0 INTREQ__USI11_USI 0>;
  2682. /*
  2683. dma-mode;
  2684. dmas = <&pdma0 31 &pdma0 30>;
  2685. */
  2686. dma-names = "tx", "rx";
  2687. swap-mode;
  2688. #address-cells = <1>;
  2689. #size-cells = <0>;
  2690. clocks = <&clock GATE_USI11>, <&clock USI11>;
  2691. clock-names = "spi", "spi_busclk0";
  2692. pinctrl-names = "default";
  2693. pinctrl-0 = <&spi12_bus>;
  2694. status = "disabled";
  2695. };
  2696.  
  2697. /* SPI USI_PERIC0_USI12_SPI */
  2698. spi_13: spi@10520000 {
  2699. compatible = "samsung,exynos-spi";
  2700. reg = <0x0 0x10520000 0x100>;
  2701. samsung,spi-fifosize = <64>;
  2702. interrupts = <0 INTREQ__USI12_USI 0>;
  2703. /*
  2704. dma-mode;
  2705. dmas = <&pdma0 31 &pdma0 30>;
  2706. */
  2707. dma-names = "tx", "rx";
  2708. swap-mode;
  2709. #address-cells = <1>;
  2710. #size-cells = <0>;
  2711. clocks = <&clock GATE_USI12>, <&clock USI12>;
  2712. clock-names = "spi", "spi_busclk0";
  2713. pinctrl-names = "default";
  2714. pinctrl-0 = <&spi13_bus>;
  2715. status = "disabled";
  2716. };
  2717.  
  2718. /* SPI USI_PERIC0_USI13_SPI */
  2719. spi_14: spi@10540000 {
  2720. compatible = "samsung,exynos-spi";
  2721. reg = <0x0 0x10540000 0x100>;
  2722. samsung,spi-fifosize = <64>;
  2723. interrupts = <0 INTREQ__USI13_USI 0>;
  2724. /*
  2725. dma-mode;
  2726. dmas = <&pdma0 31 &pdma0 30>;
  2727. */
  2728. dma-names = "tx", "rx";
  2729. swap-mode;
  2730. #address-cells = <1>;
  2731. #size-cells = <0>;
  2732. clocks = <&clock GATE_USI13>, <&clock USI13>;
  2733. clock-names = "spi", "spi_busclk0";
  2734. pinctrl-names = "default";
  2735. pinctrl-0 = <&spi14_bus>;
  2736. status = "disabled";
  2737. };
  2738.  
  2739. /* SPI USI_PERIC0_USI14_SPI */
  2740. spi_15: spi@10560000 {
  2741. compatible = "samsung,exynos-spi";
  2742. reg = <0x0 0x10560000 0x100>;
  2743. samsung,spi-fifosize = <64>;
  2744. interrupts = <0 INTREQ__USI14_USI 0>;
  2745. /*
  2746. dma-mode;
  2747. dmas = <&pdma0 31 &pdma0 30>;
  2748. */
  2749. dma-names = "tx", "rx";
  2750. swap-mode;
  2751. #address-cells = <1>;
  2752. #size-cells = <0>;
  2753. clocks = <&clock GATE_USI14>, <&clock USI14>;
  2754. clock-names = "spi", "spi_busclk0";
  2755. pinctrl-names = "default";
  2756. pinctrl-0 = <&spi15_bus>;
  2757. status = "disabled";
  2758. };
  2759.  
  2760. /* SPI USI_CMGP00 */
  2761. spi_16: spi@14300000 {
  2762. compatible = "samsung,exynos-spi";
  2763. reg = <0x0 0x14300000 0x100>;
  2764. samsung,spi-fifosize = <64>;
  2765. interrupts = <0 INTREQ__USI_CMGP00 0>;
  2766. /*
  2767. dma-mode;
  2768. dmas = <&pdma0 31 &pdma0 30>;
  2769. */
  2770. dma-names = "tx", "rx";
  2771. swap-mode;
  2772. #address-cells = <1>;
  2773. #size-cells = <0>;
  2774. clocks = <&clock GATE_USI_CMGP00>, <&clock USI_CMGP00>;
  2775. clock-names = "spi", "spi_busclk0";
  2776. pinctrl-names = "default";
  2777. pinctrl-0 = <&spi16_bus>;
  2778. status = "disabled";
  2779. };
  2780.  
  2781. /* SPI USI_CMGP01 */
  2782. spi_17: spi@14320000 {
  2783. compatible = "samsung,exynos-spi";
  2784. reg = <0x0 0x1432000 0x100>;
  2785. samsung,spi-fifosize = <64>;
  2786. interrupts = <0 INTREQ__USI_CMGP01 0>;
  2787. /*
  2788. dma-mode;
  2789. dmas = <&pdma0 31 &pdma0 30>;
  2790. */
  2791. dma-names = "tx", "rx";
  2792. swap-mode;
  2793. #address-cells = <1>;
  2794. #size-cells = <0>;
  2795. clocks = <&clock GATE_USI_CMGP01>, <&clock USI_CMGP01>;
  2796. clock-names = "spi", "spi_busclk0";
  2797. pinctrl-names = "default";
  2798. pinctrl-0 = <&spi17_bus>;
  2799. status = "disabled";
  2800. };
  2801.  
  2802. /* SPI USI_CMGP02 */
  2803. spi_18: spi@14340000 {
  2804. compatible = "samsung,exynos-spi";
  2805. reg = <0x0 0x14340000 0x100>;
  2806. samsung,spi-fifosize = <64>;
  2807. interrupts = <0 INTREQ__USI_CMGP02 0>;
  2808. /*
  2809. dma-mode;
  2810. dmas = <&pdma0 31 &pdma0 30>;
  2811. */
  2812. dma-names = "tx", "rx";
  2813. swap-mode;
  2814. #address-cells = <1>;
  2815. #size-cells = <0>;
  2816. clocks = <&clock GATE_USI_CMGP02>, <&clock USI_CMGP02>;
  2817. clock-names = "spi", "spi_busclk0";
  2818. pinctrl-names = "default";
  2819. pinctrl-0 = <&spi18_bus>;
  2820. status = "disabled";
  2821. };
  2822.  
  2823. /* SPI USI_CMGP03 */
  2824. spi_19: spi@14360000 {
  2825. compatible = "samsung,exynos-spi";
  2826. reg = <0x0 0x14360000 0x100>;
  2827. samsung,spi-fifosize = <64>;
  2828. interrupts = <0 INTREQ__USI_CMGP03 0>;
  2829. /*
  2830. dma-mode;
  2831. dmas = <&pdma0 31 &pdma0 30>;
  2832. */
  2833. dma-names = "tx", "rx";
  2834. swap-mode;
  2835. #address-cells = <1>;
  2836. #size-cells = <0>;
  2837. clocks = <&clock GATE_USI_CMGP03>, <&clock USI_CMGP03>;
  2838. clock-names = "spi", "spi_busclk0";
  2839. pinctrl-names = "default";
  2840. pinctrl-0 = <&spi19_bus>;
  2841. status = "disabled";
  2842. };
  2843.  
  2844. /* SPI USI_CHUB00 */
  2845. spi_20: spi@13AC0000 {
  2846. compatible = "samsung,exynos-spi";
  2847. reg = <0x0 0x13ac0000 0x100>;
  2848. samsung,spi-fifosize = <64>;
  2849. interrupts = <0 INTREQ__USI_CHUB00 0>;
  2850. /*
  2851. dma-mode;
  2852. dmas = <&pdma0 31 &pdma0 30>;
  2853. */
  2854. dma-names = "tx", "rx";
  2855. swap-mode;
  2856. #address-cells = <1>;
  2857. #size-cells = <0>;
  2858. clocks = <&clock GATE_USI_CHUB00>, <&clock CHUB_USI00>;
  2859. clock-names = "spi", "spi_busclk0";
  2860. pinctrl-names = "default";
  2861. pinctrl-0 = <&spi20_bus>;
  2862. status = "disabled";
  2863. };
  2864.  
  2865. /* SPI USI_CHUB01 */
  2866. spi_21: spi@13AE0000 {
  2867. compatible = "samsung,exynos-spi";
  2868. reg = <0x0 0x13AE0000 0x100>;
  2869. samsung,spi-fifosize = <64>;
  2870. interrupts = <0 INTREQ__USI_CHUB01 0>;
  2871. /*
  2872. dma-mode;
  2873. dmas = <&pdma0 31 &pdma0 30>;
  2874. */
  2875. dma-names = "tx", "rx";
  2876. swap-mode;
  2877. #address-cells = <1>;
  2878. #size-cells = <0>;
  2879. clocks = <&clock GATE_USI_CHUB01>, <&clock CHUB_USI01>;
  2880. clock-names = "spi", "spi_busclk0";
  2881. pinctrl-names = "default";
  2882. pinctrl-0 = <&spi21_bus>;
  2883. status = "disabled";
  2884. };
  2885.  
  2886. /* USI_PERIC0_UART_DBG */
  2887. serial_0: uart@10440000 {
  2888. compatible = "samsung,exynos-uart";
  2889. samsung,separate-uart-clk;
  2890. reg = <0x0 0x10440000 0x100>;
  2891. samsung,fifo-size = <256>;
  2892. interrupts = <0 INTREQ__UART_DBG 0>;
  2893. pinctrl-names = "default";
  2894. pinctrl-0 = <&uart0_bus>;
  2895. samsung,usi-serial-v2;
  2896. clocks = <&clock GATE_UART_DBG>, <&clock UART_DBG>;
  2897. clock-names = "gate_pclk0", "gate_uart0";
  2898. status = "disabled";
  2899. };
  2900.  
  2901. smu: smu {
  2902. compatible = "samsung,exynos-smu";
  2903. };
  2904.  
  2905. fmp: fmp {
  2906. compatible = "samsung,exynos-fmp";
  2907. exynos,host-type = "ufs";
  2908. exynos-host = <&ufs>;
  2909. exynos,block-type = "sda";
  2910. exynos,fips-block_offset = <5>;
  2911. };
  2912.  
  2913. ufs: ufs@0x11120000 {
  2914. /* ----------------------- */
  2915. /* 1. SYSTEM CONFIGURATION */
  2916. /* ----------------------- */
  2917. compatible ="samsung,exynos-ufs";
  2918. #address-cells = <2>;
  2919. #size-cells = <1>;
  2920. ranges;
  2921.  
  2922. reg =
  2923. <0x0 0x11120000 0x200>, /* 0: HCI standard */
  2924. <0x0 0x11121100 0x200>, /* 1: Vendor specificed */
  2925. <0x0 0x11110000 0x8000>, /* 2: UNIPRO */
  2926. <0x0 0x11130000 0x100>; /* 3: UFS protector */
  2927. interrupts = <0 INTREQ__UFS_EMBD 0>;
  2928. pinctrl-names = "default";
  2929. pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
  2930. clocks =
  2931. /* aclk clock */
  2932. <&clock GATE_UFS_EMBD>,
  2933. /* unipro clocks */
  2934. <&clock UFS_EMBD>;
  2935.  
  2936. clock-names =
  2937. /* aclk clocks */
  2938. "GATE_UFS_EMBD",
  2939. /* unipro clocks */
  2940. "UFS_EMBD";
  2941.  
  2942. /* PM QoS for INT power domain */
  2943. /* ufs-pm-qos-int = <400000>;*/
  2944.  
  2945. /* PM QoS for FSYS0 power domain */
  2946. ufs-pm-qos-fsys0 = <200000>;
  2947.  
  2948. /* DMA coherent callback, should be coupled with 'ufs-sys' */
  2949. dma-coherent;
  2950.  
  2951. /* ----------------------- */
  2952. /* 2. UFS COMMON */
  2953. /* ----------------------- */
  2954. freq-table-hz = <0 0>, <0 0>;
  2955.  
  2956. vcc-supply = <&ufs_fixed_vcc>;
  2957. vcc-fixed-regulator;
  2958.  
  2959.  
  2960. /* ----------------------- */
  2961. /* 3. UFS EXYNOS */
  2962. /* ----------------------- */
  2963. hw-rev = <UFS_VER_0005>;
  2964.  
  2965. /* power mode change */
  2966. ufs,pmd-attr-lane = /bits/ 8 <2>;
  2967. ufs,pmd-attr-gear = /bits/ 8 <3>;
  2968.  
  2969. /* hiberantion */
  2970. ufs-rx-min-activate-time-cap = <3>;
  2971. ufs-rx-hibern8-time-cap = <2>;
  2972. ufs-tx-hibern8-time-cap = <2>;
  2973.  
  2974. /* board type for UFS CAL */
  2975. brd-for-cal = <0>;
  2976.  
  2977. /* smu */
  2978. ufs-exynos-smu = <&smu>;
  2979.  
  2980. /* ----------------------- */
  2981. /* 4. ADDITIONAL NODES */
  2982. /* ----------------------- */
  2983. /* PHY isolation */
  2984. ufs-phy {
  2985. #address-cells = <2>;
  2986. #size-cells = <1>;
  2987. ranges;
  2988. reg = <0x0 0x11124000 0x800>;
  2989.  
  2990. ufs-phy-sys {
  2991. reg = <0x0 0x14060724 0x4>;
  2992. };
  2993. };
  2994.  
  2995. /* SYSREG */
  2996. ufs-io-coherency {
  2997. #address-cells = <2>;
  2998. #size-cells = <1>;
  2999. ranges;
  3000.  
  3001. reg =
  3002. <0x0 0x11010700 0x4>;
  3003.  
  3004. mask = <(BIT_8 | BIT_9)>;
  3005. bits = <(BIT_8 | BIT_9)>;
  3006. };
  3007.  
  3008. };
  3009.  
  3010. ufs_fixed_vcc: fixedregulator@0 {
  3011. compatible = "regulator-fixed";
  3012. regulator-name = "ufs-vcc";
  3013. gpio = <&gpd0 2 0>;
  3014. regulator-boot-on;
  3015. enable-active-high;
  3016. };
  3017.  
  3018. reboot {
  3019. compatible = "exynos,reboot";
  3020. pmu_base = <0x14060000>;
  3021. };
  3022.  
  3023. handler {
  3024. compatible = "exynos,handler";
  3025. interrupts = <0 INTREQ__CPUCL0_ERRIRQ_0 0>, /* CPUCL0 L3 ECC */
  3026. <0 INTREQ__CPUCL0_ERRIRQ_1 0>, /* CPUCL0_0 L1 ECC */
  3027. <0 INTREQ__CPUCL0_ERRIRQ_2 0>, /* CPUCL0_1 L1 ECC */
  3028. <0 INTREQ__CPUCL0_ERRIRQ_3 0>, /* CPUCL0_2 L1 ECC */
  3029. <0 INTREQ__CPUCL0_ERRIRQ_4 0>, /* CPUCL0_3 L1 ECC */
  3030. <0 INTREQ__CPUCL1_INTERRIRQ 0>; /* CPUCL1 L2, L3 ECC */
  3031. };
  3032.  
  3033. sysmmu_dpu0: sysmmu@160A0000 {
  3034. compatible = "samsung,exynos-sysmmu";
  3035. reg = <0x0 0x160A0000 0x9000>;
  3036. interrupts = <0 INTREQ__SYSMMU_DPUD0_NONSECURE 0>,
  3037. <0 INTREQ__SYSMMU_DPUD0_SECURE 0>;
  3038. qos = <15>;
  3039. clock-names = "aclk";
  3040. clocks = <&clock GATE_SYSMMU_DPUD0>;
  3041. port-name = "VGRF, VGF";
  3042. sysmmu,secure-irq;
  3043. sysmmu,secure_base = <0x160D0000>;
  3044. sysmmu,tlb_property =
  3045. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL4) SYSMMU_NOID>,
  3046. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x5, 0xF)>,
  3047. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x6, 0xF)>,
  3048. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x7, 0xF)>,
  3049. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0xC, 0xF)>,
  3050. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0xD, 0xF)>,
  3051. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x0, 0xF)>,
  3052. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x1, 0xF)>,
  3053. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x2, 0xF)>,
  3054. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x3, 0xF)>,
  3055. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x8, 0xF)>,
  3056. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x9, 0xF)>;
  3057. #iommu-cells = <0>;
  3058. };
  3059. sysmmu_dpu1: sysmmu@160B0000 {
  3060. compatible = "samsung,exynos-sysmmu";
  3061. reg = <0x0 0x160B0000 0x9000>;
  3062. interrupts = <0 INTREQ__SYSMMU_DPUD1_NONSECURE 0>,
  3063. <0 INTREQ__SYSMMU_DPUD1_SECURE 0>;
  3064. qos = <15>;
  3065. clock-names = "aclk";
  3066. clocks = <&clock GATE_SYSMMU_DPUD1>;
  3067. port-name = "G0, VG0";
  3068. sysmmu,secure-irq;
  3069. sysmmu,secure_base = <0x160E0000>;
  3070. sysmmu,tlb_property =
  3071. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
  3072. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0xF)>,
  3073. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0xF)>,
  3074. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0xF)>,
  3075. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0xF)>;
  3076. #iommu-cells = <0>;
  3077. };
  3078. sysmmu_dpu2: sysmmu@160C0000 {
  3079. compatible = "samsung,exynos-sysmmu";
  3080. reg = <0x0 0x160C0000 0x9000>;
  3081. interrupts = <0 INTREQ__SYSMMU_DPUD2_NONSECURE 0>,
  3082. <0 INTREQ__SYSMMU_DPUD2_SECURE 0>;
  3083. qos = <15>;
  3084. clock-names = "aclk";
  3085. clocks = <&clock GATE_SYSMMU_DPUD2>;
  3086. port-name = "G1, VG1, WB";
  3087. sysmmu,secure-irq;
  3088. sysmmu,secure_base = <0x160F0000>;
  3089. sysmmu,tlb_property =
  3090. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
  3091. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0xF)>,
  3092. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0xF)>,
  3093. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0xF)>,
  3094. <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0xF)>,
  3095. <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x18)>,
  3096. <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x18)>,
  3097. <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x18)>,
  3098. <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x18)>;
  3099. #iommu-cells = <0>;
  3100. };
  3101.  
  3102. iommu-domain_disp {
  3103. compatible = "samsung,exynos-iommu-bus";
  3104. #address-cells = <2>;
  3105. #size-cells = <1>;
  3106. ranges;
  3107.  
  3108. domain-clients = <&dsim_0>, <&displayport>;
  3109. };
  3110.  
  3111. iva: iva@0x17200000 {
  3112. compatible = "samsung,iva";
  3113. reg = <0x0 0x17200000 0x200000>;
  3114.  
  3115. iommus = <&sysmmu_iva>;
  3116.  
  3117. interrupt-names = "iva_mbox_irq";
  3118. interrupts = <0 INTREQ__BLK_IVA_IVA_iva_ap_irq_aq_0 0>;
  3119.  
  3120. clocks = <&clock GATE_IVA>;
  3121. clock-names = "clk_iva";
  3122. samsung,power-domain = <&pd_iva>;
  3123. dvfs-dev = <&devfreq_6>;
  3124. qos_rate = <534000>;
  3125.  
  3126. mcu-info {
  3127. mem_size = <0x20000>;
  3128. shmem_size = <0x1000>;
  3129. print_delay = <0>; /* us */
  3130. };
  3131. };
  3132.  
  3133. sysmmu_iva: sysmmu@17020000 {
  3134. compatible = "samsung,exynos-sysmmu";
  3135. reg = <0x0 0x17020000 0x9000>;
  3136. interrupts = <0 INTREQ__BLK_IVA_SYSMMU_IVA_O_INTERRUPT_NONSECURE 0>;
  3137. clock-names = "aclk";
  3138. clocks = <&clock GATE_SMMU_IVA>;
  3139. #iommu-cells = <0>;
  3140. };
  3141.  
  3142. iommu-domain_iva_score {
  3143. compatible = "samsung,exynos-iommu-bus";
  3144.  
  3145. /* #address-cells = <2>; */
  3146. /* #size-cells = <1>; */
  3147. /* ranges; */
  3148.  
  3149. #dma-address-cells = <1>;
  3150. #dma-size-cells = <1>;
  3151. /* start address, size */
  3152. dma-window = <0x80000000 0x70000000>;
  3153.  
  3154. domain-clients = <&iva>;
  3155. };
  3156.  
  3157. score: score@16D00000 {
  3158. compatible = "samsung,score";
  3159. dma-coherent;
  3160. reg = <0x0 0x16D00000 0x100000>;
  3161. interrupts = <0 222 0>;
  3162.  
  3163. clocks = <&clock GATE_SCORE_MASTER>, <&clock GATE_SCORE_KNIGHT>;
  3164. clock-names = "dspm", "dsps";
  3165. samsung,power-domain = <&pd_dsps>;
  3166.  
  3167. iommus = <&sysmmu_score0>, <&sysmmu_score1>;
  3168. qos_table = <534000 467000 336000 168000 34000>;
  3169. default_qos = <534000>;
  3170. };
  3171.  
  3172. iommu-domain_score {
  3173. compatible = "samsung,exynos-iommu-bus";
  3174. #address-cells = <2>;
  3175. #size-cells = <1>;
  3176. ranges;
  3177.  
  3178. /* #dma-address-cells = <1>; */
  3179. /* #dma-size-cells = <1>; */
  3180. /* start address, size */
  3181. /* dma-window = <0x80000000 0x20000000>; */
  3182.  
  3183. domain-clients = <&score>;
  3184. };
  3185.  
  3186. sysmmu_score0: sysmmu@16C20000 {
  3187. compatible = "samsung,exynos-sysmmu";
  3188. reg = <0x0 0x16C20000 0x9000>;
  3189. interrupts = <0 INTREQ__BLK_DSPM_SYSMMU_DSPM0_O_INTERRUPT_NONSECURE 0>,
  3190. <0 INTREQ__BLK_DSPM_SYSMMU_DSPM0_O_INTERRUPT_SECURE 0>;
  3191. qos = <15>;
  3192. clock-names = "aclk";
  3193. clocks = <&clock GATE_SMMU_DSPM0>;
  3194. port-name = "SCore0";
  3195. sysmmu,secure-irq;
  3196. sysmmu,secure_base = <0x16C50000>;
  3197. sysmmu,tlb_property =
  3198. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
  3199. #iommu-cells = <0>;
  3200. };
  3201.  
  3202. sysmmu_score1: sysmmu@16C30000 {
  3203. compatible = "samsung,exynos-sysmmu";
  3204. reg = <0x0 0x16C30000 0x9000>;
  3205. interrupts = <0 INTREQ__BLK_DSPM_SYSMMU_DSPM1_O_INTERRUPT_NONSECURE 0>,
  3206. <0 INTREQ__BLK_DSPM_SYSMMU_DSPM1_O_INTERRUPT_SECURE 0>;
  3207. qos = <15>;
  3208. clock-names = "aclk";
  3209. clocks = <&clock GATE_SMMU_DSPM1>;
  3210. port-name = "SCore1";
  3211. sysmmu,secure-irq;
  3212. sysmmu,secure_base = <0x16C60000>;
  3213. sysmmu,tlb_property =
  3214. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
  3215. #iommu-cells = <0>;
  3216. };
  3217.  
  3218. sysmmu_g2d0: sysmmu@17660000 {
  3219. compatible = "samsung,exynos-sysmmu";
  3220. reg = <0x0 0x17660000 0x9000>;
  3221. interrupts = <0 INTREQ__SYSMMU_G2DD0_interrupt_nonsecure 0>,
  3222. <0 INTREQ__SYSMMU_G2DD0_interrupt_secure 0>;
  3223. qos = <15>;
  3224. clock-names = "aclk";
  3225. clocks = <&clock GATE_SMMU_G2DD0>;
  3226. port-name = "G2D port0";
  3227. sysmmu,secure-irq;
  3228. sysmmu,secure_base = <0x17670000>;
  3229. sysmmu,tlb_property =
  3230. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL32) SYSMMU_NOID>;
  3231. #iommu-cells = <0>;
  3232. };
  3233. sysmmu_g2d1: sysmmu@17680000 {
  3234. compatible = "samsung,exynos-sysmmu";
  3235. reg = <0x0 0x17680000 0x9000>;
  3236. interrupts = <0 INTREQ__SYSMMU_G2DD1_interrupt_nonsecure 0>,
  3237. <0 INTREQ__SYSMMU_G2DD1_interrupt_secure 0>;
  3238. qos = <15>;
  3239. clock-names = "aclk";
  3240. clocks = <&clock GATE_SMMU_G2DD1>;
  3241. port-name = "G2D port1";
  3242. sysmmu,secure-irq;
  3243. sysmmu,secure_base = <0x17690000>;
  3244. sysmmu,tlb_property =
  3245. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL32) SYSMMU_NOID>;
  3246. #iommu-cells = <0>;
  3247. };
  3248.  
  3249. iommu-domain_g2d {
  3250. compatible = "samsung,exynos-iommu-bus";
  3251. #address-cells = <2>;
  3252. #size-cells = <1>;
  3253. ranges;
  3254.  
  3255. domain-clients = <&fimg2d>;
  3256.  
  3257. #dma-address-cells = <1>;
  3258. #dma-size-cells = <1>;
  3259. dma-ranges;
  3260. dma-window = <0x10000000 0x70000000>;
  3261. };
  3262.  
  3263. fimg2d: g2d@17620000 {
  3264. compatible = "samsung,exynos9810-g2d";
  3265. reg = <0x0 0x17620000 0x9000>;
  3266. interrupts = <0 INTREQ__G2D 0>;
  3267. clock-names = "gate";
  3268. clocks = <&clock GATE_G2D>;
  3269. samsung,power-domain = <&pd_g2d>;
  3270. iommus = <&sysmmu_g2d0>, <&sysmmu_g2d1>;
  3271. hw_ppc =
  3272. /* sc_up none x1 x1/4 x1/9 x1/16 */
  3273. <3400 3100 2200 3600 5100 7000 /* rgb32 non-rotated */
  3274. 3300 2700 2000 3000 5200 6500 /* rgb32 rotated */
  3275. 3000 2900 2600 3400 5100 11900 /* yuv2p non-rotated */
  3276. 3200 2000 1900 3300 5200 7000 /* yuv2p rotated */
  3277. 2400 1900 1900 2700 3100 4100 /* 8+2 non-rotated */
  3278. 2500 900 900 2200 2900 3700 /* 8+2 rotated */
  3279. 3800>; /* colorfill */
  3280.  
  3281. g2d_dvfs_table = <534000 711000
  3282. 400000 534000
  3283. 336000 400000
  3284. 267000 356000
  3285. 178000 200000
  3286. 107000 134000
  3287. >;
  3288. dma-coherent;
  3289. };
  3290.  
  3291. sysmmu_g2d2: sysmmu@17780000 {
  3292. compatible = "samsung,exynos-sysmmu";
  3293. reg = <0x0 0x17780000 0x9000>;
  3294. interrupts = <0 INTREQ__SYSMMU_G2DD2_interrupt_nonsecure 0>,
  3295. <0 INTREQ__SYSMMU_G2DD2_interrupt_secure 0>;
  3296. qos = <15>;
  3297. clock-names = "aclk";
  3298. clocks = <&clock GATE_SMMU_G2DD2>;
  3299. port-name = "MSCL, SMFC";
  3300. sysmmu,secure-irq;
  3301. sysmmu,secure_base = <0x17790000>;
  3302. sysmmu,tlb_property =
  3303. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL32) SYSMMU_NOID>,
  3304. <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
  3305. <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
  3306. <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
  3307. <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
  3308. <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL2) SYSMMU_ID_MASK(0x2, 0x3)>;
  3309. #iommu-cells = <0>;
  3310. };
  3311.  
  3312. iommu-domain_mscl_smfc {
  3313. compatible = "samsung,exynos-iommu-bus";
  3314. #address-cells = <2>;
  3315. #size-cells = <1>;
  3316. ranges;
  3317.  
  3318. domain-clients = <&astc>, <&smfc>, <&scaler_0>;
  3319. };
  3320.  
  3321. smfc: smfc@17700000 {
  3322. compatible = "samsung,exynos8890-jpeg";
  3323. dma-coherent;
  3324. reg = <0x0 0x17700000 0x1000>;
  3325. interrupts = <0 INTREQ__JPEG 0>;
  3326. clocks = <&clock GATE_JPEG>;
  3327. clock-names = "gate";
  3328. iommus = <&sysmmu_g2d2>;
  3329. smfc,int_qos_minlock = <534000>;
  3330. samsung,power-domain = <&pd_g2d>;
  3331. };
  3332.  
  3333. astc: astc@17720000 {
  3334. compatible = "samsung,exynos-astc";
  3335. dma-coherent;
  3336. reg = <0x0 0x17720000 0x1000>;
  3337. interrupts = <0 INTREQ__ASTC 0>;
  3338. clocks = <&clock GATE_ASTC>;
  3339. clock-names = "gate";
  3340. iommus = <&sysmmu_g2d2>;
  3341. /* ASTC IP uses 533000, not 534000 */
  3342. astc,int_qos_minlock = <533000>;
  3343. samsung,power-domain = <&pd_g2d>;
  3344. };
  3345.  
  3346. scaler_0: scaler@17710000 {
  3347. compatible = "samsung,exynos5-scaler";
  3348. reg = <0x0 0x17710000 0x3000>;
  3349. interrupts = <0 INTREQ__MSCL 0>;
  3350. clocks = <&clock GATE_MSCL>;
  3351. clock-names = "gate";
  3352. iommus = <&sysmmu_g2d2>;
  3353. dma-coherent;
  3354.  
  3355. /* MIF / INT */
  3356. mscl_qos_table = <
  3357. 1794000 534000 2143260
  3358. 1352000 400000 1610280
  3359. 1014000 400000 1458000
  3360. 845000 336000 648000
  3361. 676000 267000 367200
  3362. >;
  3363.  
  3364. /* power domain */
  3365. samsung,power-domain = <&pd_g2d>;
  3366. };
  3367.  
  3368. sysmmu_mfc0: sysmmu@17880000 {
  3369. compatible = "samsung,exynos-sysmmu";
  3370. reg = <0x0 0x17880000 0x9000>;
  3371. interrupts = <0 INTREQ__SYSMMU_MFCD0_interrupt_nonsecure 0>,
  3372. <0 INTREQ__SYSMMU_MFCD0_interrupt_secure 0>;
  3373. qos = <15>;
  3374. clock-names = "aclk";
  3375. clocks = <&clock GATE_SMMU_MFCD0>;
  3376. port-name = "MFC port0";
  3377. sysmmu,secure-irq;
  3378. sysmmu,secure_base = <0x17890000>;
  3379. sysmmu,tlb_property =
  3380. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
  3381. #iommu-cells = <0>;
  3382. };
  3383. sysmmu_mfc1: sysmmu@178A0000 {
  3384. compatible = "samsung,exynos-sysmmu";
  3385. reg = <0x0 0x178A0000 0x9000>;
  3386. interrupts = <0 INTREQ__SYSMMU_MFCD1_interrupt_nonsecure 0>,
  3387. <0 INTREQ__SYSMMU_MFCD1_interrupt_secure 0>;
  3388. qos = <15>;
  3389. clock-names = "aclk";
  3390. clocks = <&clock GATE_SMMU_MFCD1>;
  3391. port-name = "MFC port1, WFD";
  3392. sysmmu,secure-irq;
  3393. sysmmu,secure_base = <0x178B0000>;
  3394. sysmmu,tlb_property =
  3395. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>,
  3396. <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x0) | SYSMMU_BL2) SYSMMU_ID_MASK(0x1, 0x1)>;
  3397. #iommu-cells = <0>;
  3398. };
  3399.  
  3400. iommu-domain_mfc {
  3401. compatible = "samsung,exynos-iommu-bus";
  3402. #address-cells = <2>;
  3403. #size-cells = <1>;
  3404. ranges;
  3405.  
  3406. domain-clients = <&mfc_0>, <&tsmux>;
  3407. };
  3408.  
  3409. mfc_0: mfc0@178D0000 {
  3410. compatible = "samsung,mfc-v6";
  3411. reg = <0x0 0x178D0000 0x10000>;
  3412. interrupts = <0 INTREQ__MFC 0>;
  3413. clock-names = "aclk_mfc";
  3414. clocks = <&clock GATE_MFC>;
  3415. iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>;
  3416. samsung,power-domain = <&pd_mfc>;
  3417. status = "ok";
  3418. ip_ver = <17>;
  3419. clock_rate = <400000000>;
  3420. min_rate = <100000>;
  3421. num_qos_steps = <8>;
  3422. max_qos_steps = <9>;
  3423. max_mb = <4757298>;
  3424. mfc_qos_table {
  3425. mfc_qos_variant_0 {
  3426. thrd_mb = <0>;
  3427. freq_mfc = <200000>;
  3428. freq_int = <178000>;
  3429. freq_mif = <421000>;
  3430. freq_cpu = <0>;
  3431. freq_kfc = <0>;
  3432. mo_value = <0>;
  3433. mo_10bit_value = <0>;
  3434. mo_uhd_enc60_value = <0>;
  3435. time_fw = <607>;
  3436. };
  3437. mfc_qos_variant_1 {
  3438. thrd_mb = <253209>;
  3439. freq_mfc = <336000>;
  3440. freq_int = <267000>;
  3441. freq_mif = <546000>;
  3442. freq_cpu = <0>;
  3443. freq_kfc = <0>;
  3444. mo_value = <0>;
  3445. mo_10bit_value = <0>;
  3446. mo_uhd_enc60_value = <0>;
  3447. time_fw = <432>;
  3448. };
  3449. mfc_qos_variant_2 {
  3450. thrd_mb = <518600>;
  3451. freq_mfc = <400000>;
  3452. freq_int = <336000>;
  3453. freq_mif = <845000>;
  3454. freq_cpu = <0>;
  3455. freq_kfc = <0>;
  3456. mo_value = <0>;
  3457. mo_10bit_value = <0>;
  3458. mo_uhd_enc60_value = <0>;
  3459. time_fw = <323>;
  3460. };
  3461. mfc_qos_variant_3 {
  3462. thrd_mb = <1086358>;
  3463. freq_mfc = <534000>;
  3464. freq_int = <400000>;
  3465. freq_mif = <1352000>;
  3466. freq_cpu = <0>;
  3467. freq_kfc = <0>;
  3468. mo_value = <0>;
  3469. mo_10bit_value = <0>;
  3470. mo_uhd_enc60_value = <0>;
  3471. time_fw = <241>;
  3472. };
  3473. mfc_qos_variant_4 {
  3474. thrd_mb = <1694860>;
  3475. freq_mfc = <672000>;
  3476. freq_int = <534000>;
  3477. freq_mif = <1794000>;
  3478. freq_cpu = <0>;
  3479. freq_kfc = <0>;
  3480. mo_value = <0>;
  3481. mo_10bit_value = <0>;
  3482. mo_uhd_enc60_value = <0>;
  3483. time_fw = <191>;
  3484. };
  3485. mfc_qos_variant_5 {
  3486. thrd_mb = <2347751>;
  3487. freq_mfc = <672000>;
  3488. freq_int = <534000>;
  3489. freq_mif = <1014000>;
  3490. freq_cpu = <0>;
  3491. freq_kfc = <0>;
  3492. mo_value = <1>;
  3493. mo_10bit_value = <0>;
  3494. mo_uhd_enc60_value = <0>;
  3495. time_fw = <236>;
  3496. };
  3497. mfc_qos_variant_6 {
  3498. thrd_mb = <3122858>;
  3499. freq_mfc = <672000>;
  3500. freq_int = <534000>;
  3501. freq_mif = <1794000>;
  3502. freq_cpu = <0>;
  3503. freq_kfc = <0>;
  3504. mo_value = <1>;
  3505. mo_10bit_value = <0>;
  3506. mo_uhd_enc60_value = <0>;
  3507. time_fw = <191>;
  3508. };
  3509. mfc_qos_variant_7 {
  3510. thrd_mb = <4230819>;
  3511. freq_mfc = <672000>;
  3512. freq_int = <534000>;
  3513. freq_mif = <1794000>;
  3514. freq_cpu = <0>;
  3515. freq_kfc = <0>;
  3516. mo_value = <0>;
  3517. mo_10bit_value = <1>;
  3518. mo_uhd_enc60_value = <0>;
  3519. time_fw = <191>;
  3520. };
  3521. /* special level for uhd 60fps enc */
  3522. mfc_qos_variant_8 {
  3523. thrd_mb = <1694860>;
  3524. freq_mfc = <672000>;
  3525. freq_int = <534000>;
  3526. freq_mif = <1794000>;
  3527. freq_cpu = <0>;
  3528. freq_kfc = <0>;
  3529. mo_value = <0>;
  3530. mo_10bit_value = <0>;
  3531. mo_uhd_enc60_value = <1>;
  3532. time_fw = <191>;
  3533. };
  3534. };
  3535. };
  3536.  
  3537. tsmux: tsmux@178E0000 {
  3538. compatible = "samsung,exynos-tsmux";
  3539. reg = <0x0 0x178E0000 0x1000>;
  3540. interrupts = <0 INTREQ__WFD 0>;
  3541. iommus = <&sysmmu_mfc1>;
  3542. /* power domain */
  3543. samsung,power-domain = <&pd_mfc>;
  3544. };
  3545.  
  3546. sysmmu_aud: sysmmu@17E00000 {
  3547. compatible = "samsung,exynos-sysmmu";
  3548. reg = <0x0 0x17E00000 0x9000>;
  3549. interrupts = <0 INTREQ__AUD_SMMU 0>;
  3550. qos = <15>;
  3551. clock-names = "aclk";
  3552. clocks = <&clock GATE_SMMU_ABOX>;
  3553. port-name = "Abox";
  3554. sysmmu,no-suspend;
  3555. sysmmu,tlb_property =
  3556. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>;
  3557. #iommu-cells = <0>;
  3558. };
  3559.  
  3560. iommu-domain_aud {
  3561. compatible = "samsung,exynos-iommu-bus";
  3562. #address-cells = <2>;
  3563. #size-cells = <1>;
  3564. ranges;
  3565.  
  3566. domain-clients = <&abox>;
  3567. };
  3568.  
  3569. repeater: repeater@15100000 {
  3570. compatible = "samsung,exynos-repeater";
  3571. /* power domain */
  3572. samsung,power-domain = <&pd_g2d>;
  3573. };
  3574.  
  3575. sysmmu_isphq: sysmmu@16650000 {
  3576. compatible = "samsung,exynos-sysmmu";
  3577. reg = <0x0 0x16650000 0x9000>;
  3578. interrupts = <0 INTREQ__BLK_ISPHQ_SYSMMU_ISPHQ_O_INTERRUPT_NONSECURE 0>,
  3579. <0 INTREQ__BLK_ISPHQ_SYSMMU_ISPHQ_O_INTERRUPT_SECURE 0>;
  3580. qos = <15>;
  3581. clock-names = "aclk";
  3582. clocks = <&clock GATE_IS_ISPHQ_SYSMMU>;
  3583. port-name = "ISPHQ";
  3584. sysmmu,secure-irq;
  3585. sysmmu,secure_base = <0x16660000>;
  3586. sysmmu,tlb_property =
  3587. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL16) SYSMMU_NOID>,
  3588. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x1, 0xF)>,
  3589. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x2, 0xF)>,
  3590. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x0, 0xF)>,
  3591. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x1, 0xF)>;
  3592. #iommu-cells = <0>;
  3593. };
  3594.  
  3595. sysmmu_isplp0: sysmmu@16450000 {
  3596. compatible = "samsung,exynos-sysmmu";
  3597. reg = <0x0 0x16450000 0x9000>;
  3598. interrupts = <0 INTREQ__SYSMMU_ISPLP0_NONSECURE 0>,
  3599. <0 INTREQ__SYSMMU_ISPLP0_SECURE 0>;
  3600. qos = <15>;
  3601. clock-names = "aclk";
  3602. clocks = <&clock GATE_IS_SYSMMU_ISPLP0>;
  3603. port-name = "GDC, ISPLP, VRA";
  3604. sysmmu,secure-irq;
  3605. sysmmu,secure_base = <0x16460000>;
  3606. sysmmu,tlb_property =
  3607. /* GDC */
  3608. <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL16) SYSMMU_NOID>,
  3609. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x1, 0xF)>,
  3610. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x5, 0xF)>,
  3611. /* ISPLP */
  3612. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
  3613. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
  3614. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
  3615. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
  3616. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
  3617. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
  3618. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
  3619. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
  3620. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
  3621. /* VRA */
  3622. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3)>,
  3623. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3)>;
  3624. #iommu-cells = <0>;
  3625. };
  3626. sysmmu_isplp1: sysmmu@16470000 {
  3627. compatible = "samsung,exynos-sysmmu";
  3628. reg = <0x0 0x16470000 0x9000>;
  3629. interrupts = <0 INTREQ__SYSMMU_ISPLP1_NONSECURE 0>,
  3630. <0 INTREQ__SYSMMU_ISPLP1_SECURE 0>;
  3631. qos = <15>;
  3632. clock-names = "aclk";
  3633. clocks = <&clock GATE_IS_SYSMMU_ISPLP1>;
  3634. port-name = "MC_SCALER";
  3635. sysmmu,secure-irq;
  3636. sysmmu,secure_base = <0x16480000>;
  3637. sysmmu,tlb_property =
  3638. /* RDMA0 */
  3639. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
  3640. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
  3641. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
  3642. /* RDMA0 (2bit) */
  3643. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
  3644. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
  3645. /* WDMA0 */
  3646. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
  3647. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
  3648. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
  3649. /* WDMA1 */
  3650. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
  3651. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
  3652. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0x3F)>,
  3653. /* WDMA2 */
  3654. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
  3655. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
  3656. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
  3657. /* WDMA3 */
  3658. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x9, 0x3F)>,
  3659. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xA, 0x3F)>,
  3660. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xB, 0x3F)>,
  3661. /* WDMA4 */
  3662. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
  3663. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xD, 0x3F)>,
  3664. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xE, 0x3F)>,
  3665. /* WDMA5 */
  3666. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
  3667. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
  3668. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x11, 0x3F)>,
  3669. /* WDMA0 (2bit) */
  3670. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x15, 0x3F)>,
  3671. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x16, 0x3F)>,
  3672. /* WDMA1 (2bit) */
  3673. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x17, 0x3F)>,
  3674. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x3F)>,
  3675. /* WDMA2 (2bit) */
  3676. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x19, 0x3F)>,
  3677. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1A, 0x3F)>,
  3678. /* WDMA3 (2bit) */
  3679. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1B, 0x3F)>,
  3680. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1C, 0x3F)>,
  3681. /* WDMA4 (2bit) */
  3682. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1D, 0x3F)>,
  3683. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1E, 0x3F)>,
  3684. /* WDMA5 (2bit) */
  3685. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1F, 0x3F)>,
  3686. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x20, 0x3F)>;
  3687. #iommu-cells = <0>;
  3688. };
  3689.  
  3690. sysmmu_isppre: sysmmu@16310000 {
  3691. compatible = "samsung,exynos-sysmmu";
  3692. reg = <0x0 0x16310000 0x9000>;
  3693. interrupts = <0 INTREQ__SYSMMU_ISPPRE_NONSECURE 0>,
  3694. <0 INTREQ__SYSMMU_ISPPRE_SECURE 0>;
  3695. qos = <15>;
  3696. clock-names = "aclk";
  3697. clocks = <&clock GATE_IS_ISPPRE_SYSMMU>;
  3698. port-name = "3AAM, 3AA, PDP";
  3699. sysmmu,secure-irq;
  3700. sysmmu,secure_base = <0x16300000>;
  3701. sysmmu,tlb_property =
  3702. /* 3AA0 */
  3703. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
  3704. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
  3705. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xA, 0x3F)>,
  3706. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xE, 0x3F)>,
  3707. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x12, 0x3F)>,
  3708. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
  3709. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
  3710. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xA, 0x3F)>,
  3711. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xE, 0x3F)>,
  3712. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x12, 0x3F)>,
  3713. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x16, 0x3F)>,
  3714. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1A, 0x3F)>,
  3715. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1E, 0x3F)>,
  3716. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x22, 0x3F)>,
  3717. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x26, 0x3F)>,
  3718. /* 3AA1 */
  3719. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
  3720. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
  3721. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xB, 0x3F)>,
  3722. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
  3723. <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x13, 0x3F)>,
  3724. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
  3725. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
  3726. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xB, 0x3F)>,
  3727. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
  3728. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x13, 0x3F)>,
  3729. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x17, 0x3F)>,
  3730. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1B, 0x3F)>,
  3731. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1F, 0x3F)>,
  3732. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x23, 0x3F)>,
  3733. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x27, 0x3F)>,
  3734. /* PDP */
  3735. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
  3736. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
  3737. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
  3738. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
  3739. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
  3740. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x14, 0x3F)>,
  3741. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x3F)>,
  3742. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1C, 0x3F)>,
  3743. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x20, 0x3F)>,
  3744. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x24, 0x3F)>,
  3745. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x28, 0x3F)>,
  3746. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2C, 0x3F)>,
  3747. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x30, 0x3F)>,
  3748. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x34, 0x3F)>,
  3749. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x38, 0x3F)>,
  3750. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3C, 0x3F)>,
  3751. /* PDP stat */
  3752. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
  3753. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0x3F)>,
  3754. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x21, 0x3F)>,
  3755. <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x25, 0x3F)>;
  3756. #iommu-cells = <0>;
  3757. };
  3758.  
  3759. iommu-domain_isp {
  3760. compatible = "samsung,exynos-iommu-bus";
  3761. #address-cells = <2>;
  3762. #size-cells = <1>;
  3763. ranges;
  3764.  
  3765. domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
  3766. <&fimc_is_sensor2>, <&fimc_is_sensor3>, <&camerapp_gdc>;
  3767. };
  3768.  
  3769. speedy@141C0000 {
  3770. compatible = "samsung,exynos-speedy";
  3771. reg = <0x0 0x141C0000 0x2000>;
  3772. interrupts = <0 INTREQ__SPEEDY_APM 0>;
  3773. #address-cells = <1>;
  3774. #size-cells = <0>;
  3775. pinctrl-names = "default";
  3776. pinctrl-0 = <&speedy_bus>;
  3777. #if 0
  3778. clocks = <&clock GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP>;
  3779. clock-names = "gate_speedy";
  3780. #endif
  3781. status = "disabled";
  3782. };
  3783.  
  3784. acpm {
  3785. compatible = "samsung,exynos-acpm";
  3786. #address-cells = <2>;
  3787. #size-cells = <1>;
  3788. acpm-ipc-channel = <4>;
  3789. fvmap_offset = <0x6700>;
  3790. reg = <0x0 0x14020000 0x1000>; /* TIMER_APM */
  3791. reg-names = "timer_apm";
  3792. peritimer-cnt = <0xFFFF>;
  3793. };
  3794.  
  3795. acpm_ipc {
  3796. compatible = "samsung,exynos-acpm-ipc";
  3797. #address-cells = <2>;
  3798. #size-cells = <1>;
  3799. interrupts = <0 INTREQ__MAILBOX_APM2AP 0>; /* AP2APM MAILBOX SPI NUM*/
  3800. reg = <0x0 0x14100000 0x1000>, /* AP2APM MAILBOX */
  3801. <0x0 0x2039000 0x30000>; /* APM SRAM */
  3802. initdata-base = <0x7F00>;
  3803. num-timestamps = <32>;
  3804. debug-log-level = <0>;
  3805. logging-period = <500>;
  3806. dump-base = <0x203C000>;
  3807. dump-size = <0x1D000>; /* 116KB */
  3808. };
  3809.  
  3810. exynos_flexpmu_dbg {
  3811. compatible = "samsung,exynos-flexpmu-dbg";
  3812. #address-cells = <2>;
  3813. #size-cells = <1>;
  3814. data-base = <0x204F800>;
  3815. data-size = <0x400>;
  3816. };
  3817.  
  3818. acpm_dvfs {
  3819. compatible = "samsung,exynos-acpm-dvfs";
  3820. acpm-ipc-channel = <5>;
  3821. };
  3822.  
  3823. acpm_s2d {
  3824. compatible = "samsung,exynos-acpm-s2d";
  3825. acpm-ipc-channel = <11>;
  3826. };
  3827.  
  3828. devfreq_0: devfreq_mif@17000010 {
  3829. compatible = "samsung,exynos-devfreq";
  3830. reg = <0x0 0x17000010 0x0>;
  3831. devfreq_type = "mif";
  3832. devfreq_domain_name = "dvfs_mif";
  3833.  
  3834. /* Delay time */
  3835. use_delay_time = "true";
  3836. delay_time_list = "20";
  3837.  
  3838. freq_info = <2093000 208000 1014000 208000 2093000 2093000>;
  3839. /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
  3840.  
  3841. /* Booting value */
  3842. boot_info = <40 1794000>;
  3843. /* boot_qos_timeout, boot_freq */
  3844.  
  3845. use_get_dev = "false";
  3846. polling_ms = <0>;
  3847.  
  3848. /* governor data */
  3849. gov_name = "interactive";
  3850. use_reg = "false";
  3851.  
  3852. use_tmu = "true";
  3853. use_cl_dvfs = "false";
  3854. use_sw_clk = "false";
  3855. dfs_id = <ACPM_DVFS_MIF>;
  3856. acpm-ipc-channel = <1>;
  3857. use_acpm = "true";
  3858. };
  3859.  
  3860. devfreq_1: devfreq_int@17000020 {
  3861. compatible = "samsung,exynos-devfreq";
  3862. reg = <0x0 0x17000020 0x0>;
  3863. devfreq_type = "int";
  3864. devfreq_domain_name = "dvfs_int";
  3865.  
  3866. /* Delay time */
  3867. use_delay_time = "false";
  3868.  
  3869. freq_info = <667000 178000 107000 107000 667000 667000>;
  3870. /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
  3871.  
  3872. /* Booting value */
  3873. boot_info = <40 667000>;
  3874. /* boot_qos_timeout, boot_freq */
  3875.  
  3876. /* default_dev_profile */
  3877. use_get_dev = "false";
  3878. polling_ms = <0>;
  3879.  
  3880. /* governor data */
  3881. gov_name = "interactive";
  3882. use_reg = "false";
  3883.  
  3884. use_tmu = "true";
  3885. use_cl_dvfs = "false";
  3886. use_sw_clk = "false";
  3887. dfs_id = <ACPM_DVFS_INT>;
  3888. acpm-ipc-channel = <1>;
  3889. use_acpm = "true";
  3890. };
  3891.  
  3892. devfreq_2: devfreq_intcam@17000030 {
  3893. compatible = "samsung,exynos-devfreq";
  3894. reg = <0x0 0x17000030 0x0>;
  3895. devfreq_type = "intcam";
  3896. devfreq_domain_name = "dvfs_intcam";
  3897.  
  3898. /* Delay time */
  3899. use_delay_time = "false";
  3900.  
  3901. freq_info = <690000 630000 690000 630000 690000 690000>;
  3902. /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
  3903.  
  3904. /* Booting value */
  3905. boot_info = <40 640000>;
  3906. /* boot_qos_timeout, boot_freq */
  3907.  
  3908. /* default_dev_profile */
  3909. use_get_dev = "false";
  3910. polling_ms = <0>;
  3911.  
  3912. /* governor data */
  3913. gov_name = "interactive";
  3914. use_reg = "false";
  3915.  
  3916. use_tmu = "true";
  3917. use_cl_dvfs = "false";
  3918. use_sw_clk = "false";
  3919. dfs_id = <ACPM_DVFS_INTCAM>;
  3920. };
  3921.  
  3922. devfreq_3: devfreq_disp@17000040 {
  3923. compatible = "samsung,exynos-devfreq";
  3924. reg = <0x0 0x17000040 0x0>;
  3925. devfreq_type = "disp";
  3926. devfreq_domain_name = "dvfs_disp";
  3927.  
  3928. /* Delay time */
  3929. use_delay_time = "false";
  3930.  
  3931. freq_info = <640000 200000 640000 200000 640000 640000>;
  3932. /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
  3933.  
  3934. /* Booting value */
  3935. boot_info = <40 640000>;
  3936. /* boot_qos_timeout, boot_freq */
  3937.  
  3938. /* default dev profile */
  3939. use_get_dev = "false";
  3940. polling_ms = <0>;
  3941.  
  3942. /* governor data */
  3943. gov_name = "interactive";
  3944. use_reg = "false";
  3945.  
  3946. use_tmu = "true";
  3947. use_cl_dvfs = "false";
  3948. use_sw_clk = "false";
  3949. dfs_id = <ACPM_DVFS_DISP>;
  3950. };
  3951.  
  3952. devfreq_4: devfreq_cam@17000050 {
  3953. compatible = "samsung,exynos-devfreq";
  3954. reg = <0x0 0x17000050 0x0>;
  3955. devfreq_type = "cam";
  3956. devfreq_domain_name = "dvfs_cam";
  3957.  
  3958. /* Delay time */
  3959. use_delay_time = "false";
  3960.  
  3961. freq_info = <690000 590000 690000 590000 690000 690000>;
  3962. /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
  3963.  
  3964. /* Booting value */
  3965. boot_info = <40 630000>;
  3966. /* boot_qos_timeout, boot_freq */
  3967.  
  3968. /* default dev profile */
  3969. use_get_dev = "false";
  3970. polling_ms = <0>;
  3971.  
  3972. /* governor data */
  3973. gov_name = "interactive";
  3974. use_reg = "false";
  3975.  
  3976. use_tmu = "true";
  3977. use_cl_dvfs = "false";
  3978. use_sw_clk = "false";
  3979. dfs_id = <ACPM_DVFS_CAM>;
  3980. };
  3981.  
  3982. devfreq_5: devfreq_aud@17000060 {
  3983. compatible = "samsung,exynos-devfreq";
  3984. reg = <0x0 0x17000060 0x0>;
  3985. devfreq_type = "aud";
  3986. devfreq_domain_name = "dvfs_aud";
  3987.  
  3988. /* Delay time */
  3989. use_delay_time = "false";
  3990.  
  3991. freq_info = <295000 295000 295000 295000 1180000 295000>;
  3992. /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
  3993.  
  3994. /* Booting value */
  3995. boot_info = <40 295000>;
  3996. /* boot_qos_timeout, boot_freq */
  3997.  
  3998. /* default dev profile */
  3999. use_get_dev = "false";
  4000. polling_ms = <0>;
  4001.  
  4002. /* governor data */
  4003. gov_name = "interactive";
  4004. use_reg = "false";
  4005.  
  4006. use_tmu = "true";
  4007. use_cl_dvfs = "false";
  4008. use_sw_clk = "false";
  4009. dfs_id = <ACPM_DVFS_AUD>;
  4010. };
  4011.  
  4012. devfreq_6: devfreq_iva@17000070 {
  4013. compatible = "samsung,exynos-devfreq";
  4014. reg = <0x0 0x17000070 0x0>;
  4015. devfreq_type = "iva";
  4016. devfreq_domain_name = "dvfs_iva";
  4017.  
  4018. /* Delay time */
  4019. use_delay_time = "false";
  4020.  
  4021. freq_info = <34000 34000 34000 34000 534000 34000>;
  4022. /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
  4023.  
  4024. /* Booting value */
  4025. boot_info = <40 34000>;
  4026. /* boot_qos_timeout, boot_freq */
  4027.  
  4028. /* default dev profile */
  4029. use_get_dev = "false";
  4030. polling_ms = <0>;
  4031.  
  4032. /* governor data */
  4033. gov_name = "interactive";
  4034. use_reg = "false";
  4035.  
  4036. use_tmu = "true";
  4037. use_cl_dvfs = "false";
  4038. use_sw_clk = "false";
  4039. dfs_id = <ACPM_DVFS_IVA>;
  4040. };
  4041.  
  4042. devfreq_7: devfreq_score@17000080 {
  4043. compatible = "samsung,exynos-devfreq";
  4044. reg = <0x0 0x17000080 0x0>;
  4045. devfreq_type = "score";
  4046. devfreq_domain_name = "dvfs_score";
  4047.  
  4048. /* Delay time */
  4049. use_delay_time = "false";
  4050.  
  4051. freq_info = <34000 34000 34000 34000 534000 34000>;
  4052. /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
  4053.  
  4054. /* Booting value */
  4055. boot_info = <40 34000>;
  4056. /* boot_qos_timeout, boot_freq */
  4057.  
  4058. /* default dev profile */
  4059. use_get_dev = "false";
  4060. polling_ms = <0>;
  4061.  
  4062. /* governor data */
  4063. gov_name = "interactive";
  4064. use_reg = "false";
  4065.  
  4066. use_tmu = "true";
  4067. use_cl_dvfs = "false";
  4068. use_sw_clk = "false";
  4069. dfs_id = <ACPM_DVFS_SCORE>;
  4070. };
  4071.  
  4072. devfreq_8: devfreq_fsys0@17000090 {
  4073. compatible = "samsung,exynos-devfreq";
  4074. reg = <0x0 0x17000090 0x0>;
  4075. devfreq_type = "fsys0";
  4076. devfreq_domain_name = "dvfs_fsys0";
  4077.  
  4078. /* Delay time */
  4079. use_delay_time = "false";
  4080.  
  4081. freq_info = <336000 73000 336000 73000 336000 336000>;
  4082. /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
  4083.  
  4084. /* Booting value */
  4085. boot_info = <40 336000>;
  4086. /* boot_qos_timeout, boot_freq */
  4087.  
  4088. /* default dev profile */
  4089. use_get_dev = "false";
  4090. polling_ms = <0>;
  4091.  
  4092. /* governor data */
  4093. gov_name = "interactive";
  4094. use_reg = "false";
  4095.  
  4096. use_tmu = "true";
  4097. use_cl_dvfs = "false";
  4098. use_sw_clk = "false";
  4099. dfs_id = <ACPM_DVFS_FSYS0>;
  4100. };
  4101.  
  4102. exynos_adc: adc@14230000 {
  4103. compatible = "samsung,exynos-adc-v3";
  4104. reg = <0x0 0x14230000 0x100>;
  4105. interrupts = <0 INTREQ__ADC_CMGP_S0 0>;
  4106. #io-channel-cells = <1>;
  4107. io-channel-ranges;
  4108. clocks = <&clock GATE_ADC_CMGP>;
  4109. clock-names = "gate_adcif";
  4110. };
  4111.  
  4112. rtc@141E0000 {
  4113. compatible = "samsung,exynos8-rtc";
  4114. reg = <0x0 0x141E0000 0x100>;
  4115. interrupts = <0 INTREQ__RTC_ALARM_INT 0>, <0 INTREQ__RTC_TIC_INT_0 0>;
  4116. };
  4117.  
  4118. watchdog_cl0@10050000 {
  4119. compatible = "samsung,exynos8-wdt";
  4120. reg = <0x0 0x10050000 0x100>;
  4121. interrupts = <0 INTREQ__WDT_CLUSTER0 0>;
  4122. clocks = <&clock OSCCLK>, <&clock UMUX_CLKCMU_PERIS_BUS>;
  4123. clock-names = "rate_watchdog", "gate_watchdog";
  4124. timeout-sec = <30>;
  4125. samsung,syscon-phandle = <&pmu_system_controller>;
  4126. index = <0>; /* if little cluster then index is 0 */
  4127. };
  4128.  
  4129. watchdog_cl1@10060000 {
  4130. compatible = "samsung,exynos7-wdt";
  4131. reg = <0x0 0x10060000 0x100>;
  4132. interrupts = <0 INTREQ__WDT_CLUSTER1 0>;
  4133. clocks = <&clock OSCCLK>, <&clock UMUX_CLKCMU_PERIS_BUS>;
  4134. clock-names = "rate_watchdog", "gate_watchdog";
  4135. timeout-sec = <20>;
  4136. samsung,syscon-phandle = <&pmu_system_controller>;
  4137. index = <1>; /* if big cluster then index is 1*/
  4138. use_multistage_wdt; /* Use FIQ debug watchdog */
  4139. };
  4140.  
  4141. /* USI_PERIC1_UART_BT */
  4142. serial_1: uart@10840000 {
  4143. compatible = "samsung,exynos-uart";
  4144. samsung,separate-uart-clk;
  4145. reg = <0x0 0x10840000 0x100>;
  4146. samsung,fifo-size = <256>;
  4147. interrupts = <0 INTREQ__UART_BT 0>;
  4148. pinctrl-names = "default", "rts";
  4149. pinctrl-0 = <&uart1_bus_single &uart1_rxd_pull>; /* or _bus_dual */
  4150. pinctrl-1 = <&uart1_bus_rts>;
  4151. samsung,usi-serial-v2;
  4152. clocks = <&clock GATE_UART_BT>, <&clock UART_BT>;
  4153. clock-names = "gate_pclk1", "gate_uart1";
  4154. status = "disabled";
  4155. };
  4156.  
  4157. /* USI_PERIC0_USI00_UART */
  4158. serial_2: uart@10450000 {
  4159. compatible = "samsung,exynos-uart";
  4160. samsung,separate-uart-clk;
  4161. reg = <0x0 0x10450000 0x100>;
  4162. samsung,fifo-size = <64>;
  4163. interrupts = <0 INTREQ__USI00_USI 0>;
  4164. pinctrl-names = "default";
  4165. pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */
  4166. samsung,usi-serial-v2;
  4167. clocks = <&clock GATE_USI00>, <&clock USI00>;
  4168. clock-names = "gate_pclk2", "gate_uart2";
  4169. status = "disabled";
  4170. };
  4171.  
  4172. /* USI_PERIC0_USI01_UART */
  4173. serial_3: uart@10470000 {
  4174. compatible = "samsung,exynos-uart";
  4175. samsung,separate-uart-clk;
  4176. reg = <0x0 0x10470000 0x100>;
  4177. samsung,fifo-size = <64>;
  4178. interrupts = <0 INTREQ__USI01_USI 0>;
  4179. pinctrl-names = "default";
  4180. pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */
  4181. samsung,usi-serial-v2;
  4182. clocks = <&clock GATE_USI01>, <&clock USI01>;
  4183. clock-names = "gate_pclk3", "gate_uart3";
  4184. status = "disabled";
  4185. };
  4186.  
  4187. /* USI_PERIC0_USI02_UART */
  4188. serial_4: uart@10490000 {
  4189. compatible = "samsung,exynos-uart";
  4190. samsung,separate-uart-clk;
  4191. reg = <0x0 0x10490000 0x100>;
  4192. samsung,fifo-size = <64>;
  4193. interrupts = <0 INTREQ__USI02_USI 0>;
  4194. pinctrl-names = "default";
  4195. pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */
  4196. samsung,usi-serial-v2;
  4197. clocks = <&clock GATE_USI02>, <&clock USI02>;
  4198. clock-names = "gate_pclk4", "gate_uart4";
  4199. status = "disabled";
  4200. };
  4201.  
  4202. /* USI_PERIC0_USI03_UART */
  4203. serial_5: uart@104B0000 {
  4204. compatible = "samsung,exynos-uart";
  4205. samsung,separate-uart-clk;
  4206. reg = <0x0 0x104B0000 0x100>;
  4207. samsung,fifo-size = <64>;
  4208. interrupts = <0 INTREQ__USI03_USI 0>;
  4209. pinctrl-names = "default";
  4210. pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */
  4211. samsung,usi-serial-v2;
  4212. clocks = <&clock GATE_USI03>, <&clock USI03>;
  4213. clock-names = "gate_pclk5", "gate_uart5";
  4214. status = "disabled";
  4215. };
  4216.  
  4217. /* USI_PERIC0_USI04_UART */
  4218. serial_6: uart@104D0000 {
  4219. compatible = "samsung,exynos-uart";
  4220. samsung,separate-uart-clk;
  4221. reg = <0x0 0x104D0000 0x100>;
  4222. samsung,fifo-size = <64>;
  4223. interrupts = <0 INTREQ__USI04_USI 0>;
  4224. pinctrl-names = "default";
  4225. pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */
  4226. samsung,usi-serial-v2;
  4227. clocks = <&clock GATE_USI04>, <&clock USI04>;
  4228. clock-names = "gate_pclk6", "gate_uart6";
  4229. status = "disabled";
  4230. };
  4231.  
  4232. /* USI_PERIC0_USI05_UART */
  4233. serial_7: uart@104F0000 {
  4234. compatible = "samsung,exynos-uart";
  4235. samsung,separate-uart-clk;
  4236. reg = <0x0 0x104F0000 0x100>;
  4237. samsung,fifo-size = <64>;
  4238. interrupts = <0 INTREQ__USI05_USI 0>;
  4239. pinctrl-names = "default";
  4240. pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */
  4241. samsung,usi-serial-v2;
  4242. clocks = <&clock GATE_USI05>, <&clock USI05>;
  4243. clock-names = "gate_pclk7", "gate_uart7";
  4244. status = "disabled";
  4245. };
  4246.  
  4247. /* USI_PERIC1_USI06_UART */
  4248. serial_8: uart@108A0000 {
  4249. compatible = "samsung,exynos-uart";
  4250. samsung,separate-uart-clk;
  4251. reg = <0x0 0x108A0000 0x100>;
  4252. samsung,fifo-size = <64>;
  4253. interrupts = <0 INTREQ__USI06_USI 0>;
  4254. pinctrl-names = "default";
  4255. pinctrl-0 = <&uart8_bus_single>; /* or _bus_dual */
  4256. samsung,usi-serial-v2;
  4257. clocks = <&clock GATE_USI06>, <&clock USI06>;
  4258. clock-names = "gate_pclk8", "gate_uart8";
  4259. status = "disabled";
  4260. };
  4261.  
  4262. /* USI_PERIC1_USI07_UART */
  4263. serial_9: uart@108C0000 {
  4264. compatible = "samsung,exynos-uart";
  4265. samsung,separate-uart-clk;
  4266. reg = <0x0 0x108C0000 0x100>;
  4267. samsung,fifo-size = <64>;
  4268. interrupts = <0 INTREQ__USI07_USI 0>;
  4269. pinctrl-names = "default";
  4270. pinctrl-0 = <&uart9_bus_single>; /* or _bus_dual */
  4271. samsung,usi-serial-v2;
  4272. clocks = <&clock GATE_USI07>, <&clock USI07>;
  4273. clock-names = "gate_pclk9", "gate_uart9";
  4274. status = "disabled";
  4275. };
  4276.  
  4277. /* USI_PERIC1_USI08_UART */
  4278. serial_10: uart@108E0000 {
  4279. compatible = "samsung,exynos-uart";
  4280. samsung,separate-uart-clk;
  4281. reg = <0x0 0x108E0000 0x100>;
  4282. samsung,fifo-size = <256>;
  4283. interrupts = <0 INTREQ__USI08_USI 0>;
  4284. pinctrl-names = "default";
  4285. pinctrl-0 = <&uart10_bus_single>; /* or _bus_dual */
  4286. samsung,usi-serial-v2;
  4287. clocks = <&clock GATE_USI08>, <&clock USI08>;
  4288. clock-names = "gate_pclk10", "gate_uart10";
  4289. status = "disabled";
  4290. };
  4291.  
  4292. /* USI_PERIC1_USI09_UART */
  4293. serial_11: uart@10900000 {
  4294. compatible = "samsung,exynos-uart";
  4295. samsung,separate-uart-clk;
  4296. reg = <0x0 0x10900000 0x100>;
  4297. samsung,fifo-size = <256>;
  4298. interrupts = <0 INTREQ__USI09_USI 0>;
  4299. pinctrl-names = "default";
  4300. pinctrl-0 = <&uart11_bus_single>; /* or _bus_dual */
  4301. samsung,usi-serial-v2;
  4302. clocks = <&clock GATE_USI09>, <&clock USI09>;
  4303. clock-names = "gate_pclk11", "gate_uart11";
  4304. status = "disabled";
  4305. };
  4306.  
  4307. /* USI_PERIC1_USI10_UART */
  4308. serial_12: uart@10920000 {
  4309. compatible = "samsung,exynos-uart";
  4310. samsung,separate-uart-clk;
  4311. reg = <0x0 0x10920000 0x100>;
  4312. samsung,fifo-size = <256>;
  4313. interrupts = <0 INTREQ__USI10_USI 0>;
  4314. pinctrl-names = "default";
  4315. pinctrl-0 = <&uart12_bus_single>; /* or _bus_dual */
  4316. samsung,usi-serial-v2;
  4317. clocks = <&clock GATE_USI10>, <&clock USI10>;
  4318. clock-names = "gate_pclk12", "gate_uart12";
  4319. status = "disabled";
  4320. };
  4321.  
  4322. /* USI_PERIC1_USI11_UART */
  4323. serial_13: uart@10940000 {
  4324. compatible = "samsung,exynos-uart";
  4325. samsung,separate-uart-clk;
  4326. reg = <0x0 0x10940000 0x100>;
  4327. samsung,fifo-size = <64>;
  4328. interrupts = <0 INTREQ__USI11_USI 0>;
  4329. pinctrl-names = "default";
  4330. pinctrl-0 = <&uart13_bus_single>; /* or _bus_dual */
  4331. samsung,usi-serial-v2;
  4332. clocks = <&clock GATE_USI11>, <&clock USI11>;
  4333. clock-names = "gate_pclk13", "gate_uart13";
  4334. status = "disabled";
  4335. };
  4336.  
  4337. /* USI_PERIC0_USI12_UART */
  4338. serial_14: uart@10520000 {
  4339. compatible = "samsung,exynos-uart";
  4340. samsung,separate-uart-clk;
  4341. reg = <0x0 0x10520000 0x100>;
  4342. samsung,fifo-size = <64>;
  4343. interrupts = <0 INTREQ__USI12_USI 0>;
  4344. pinctrl-names = "default";
  4345. pinctrl-0 = <&uart14_bus_single>; /* or _bus_dual */
  4346. samsung,usi-serial-v2;
  4347. clocks = <&clock GATE_USI12>, <&clock USI12>;
  4348. clock-names = "gate_pclk14", "gate_uart14";
  4349. status = "disabled";
  4350. };
  4351.  
  4352. /* USI_PERIC0_USI13_UART */
  4353. serial_15: uart@10540000 {
  4354. compatible = "samsung,exynos-uart";
  4355. samsung,separate-uart-clk;
  4356. reg = <0x0 0x10540000 0x100>;
  4357. samsung,fifo-size = <64>;
  4358. interrupts = <0 INTREQ__USI13_USI 0>;
  4359. pinctrl-names = "default";
  4360. pinctrl-0 = <&uart15_bus_single>; /* or _bus_dual */
  4361. samsung,usi-serial-v2;
  4362. clocks = <&clock GATE_USI13>, <&clock USI13>;
  4363. clock-names = "gate_pclk15", "gate_uart15";
  4364. status = "disabled";
  4365. };
  4366.  
  4367. /* USI_PERIC0_USI14_UART */
  4368. serial_16: uart@10560000 {
  4369. compatible = "samsung,exynos-uart";
  4370. samsung,separate-uart-clk;
  4371. reg = <0x0 0x10560000 0x100>;
  4372. samsung,fifo-size = <64>;
  4373. interrupts = <0 INTREQ__USI14_USI 0>;
  4374. pinctrl-names = "default";
  4375. pinctrl-0 = <&uart16_bus_single>; /* or _bus_dual */
  4376. samsung,usi-serial-v2;
  4377. clocks = <&clock GATE_USI14>, <&clock USI14>;
  4378. clock-names = "gate_pclk16", "gate_uart16";
  4379. status = "disabled";
  4380. };
  4381.  
  4382. /* USI_CMGP00_UART */
  4383. serial_17: uart@14300000 {
  4384. compatible = "samsung,exynos-uart";
  4385. samsung,separate-uart-clk;
  4386. reg = <0x0 0x14300000 0x100>;
  4387. samsung,fifo-size = <64>;
  4388. interrupts = <0 INTREQ__USI_CMGP00 0>;
  4389. pinctrl-names = "default";
  4390. pinctrl-0 = <&uart17_bus_single>; /* or _bus_dual */
  4391. samsung,usi-serial-v2;
  4392. clocks = <&clock GATE_USI_CMGP00>, <&clock USI_CMGP00>;
  4393. clock-names = "gate_pclk17", "gate_uart17";
  4394. status = "disabled";
  4395. };
  4396.  
  4397. /* USI_CMGP01_UART */
  4398. serial_18: uart@14320000 {
  4399. compatible = "samsung,exynos-uart";
  4400. samsung,separate-uart-clk;
  4401. reg = <0x0 0x14320000 0x100>;
  4402. samsung,fifo-size = <64>;
  4403. interrupts = <0 INTREQ__USI_CMGP01 0>;
  4404. pinctrl-names = "default";
  4405. pinctrl-0 = <&uart18_bus_single>; /* or _bus_dual */
  4406. samsung,usi-serial-v2;
  4407. clocks = <&clock GATE_USI_CMGP01>, <&clock USI_CMGP01>;
  4408. clock-names = "gate_pclk18", "gate_uart18";
  4409. status = "disabled";
  4410. };
  4411.  
  4412. /* USI_CMGP02_UART */
  4413. serial_19: uart@14340000 {
  4414. compatible = "samsung,exynos-uart";
  4415. samsung,separate-uart-clk;
  4416. reg = <0x0 0x14340000 0x100>;
  4417. samsung,fifo-size = <64>;
  4418. interrupts = <0 INTREQ__USI_CMGP02 0>;
  4419. pinctrl-names = "default";
  4420. pinctrl-0 = <&uart19_bus_single>; /* or _bus_dual */
  4421. samsung,usi-serial-v2;
  4422. clocks = <&clock GATE_USI_CMGP02>, <&clock USI_CMGP02>;
  4423. clock-names = "gate_pclk19", "gate_uart10";
  4424. status = "disabled";
  4425. };
  4426.  
  4427. /* USI_CMGP03_UART */
  4428. serial_20: uart@14360000 {
  4429. compatible = "samsung,exynos-uart";
  4430. samsung,separate-uart-clk;
  4431. reg = <0x0 0x14360000 0x100>;
  4432. samsung,fifo-size = <64>;
  4433. interrupts = <0 INTREQ__USI_CMGP03 0>;
  4434. pinctrl-names = "default";
  4435. pinctrl-0 = <&uart20_bus_single>; /* or _bus_dual */
  4436. samsung,usi-serial-v2;
  4437. clocks = <&clock GATE_USI_CMGP03>, <&clock USI_CMGP03>;
  4438. clock-names = "gate_pclk20", "gate_uart20";
  4439. status = "disabled";
  4440. };
  4441.  
  4442. /* USI_CHUB00_UART */
  4443. serial_21: uart@13AC0000 {
  4444. compatible = "samsung,exynos-uart";
  4445. samsung,separate-uart-clk;
  4446. reg = <0x0 0x13ac0000 0x100>;
  4447. samsung,fifo-size = <64>;
  4448. interrupts = <0 INTREQ__USI_CHUB00 0>;
  4449. pinctrl-names = "default";
  4450. pinctrl-0 = <&uart21_bus_single>; /* or _bus_dual */
  4451. samsung,usi-serial-v2;
  4452. clocks = <&clock GATE_USI_CHUB00>, <&clock CHUB_USI00>;
  4453. clock-names = "gate_pclk21", "gate_uart21";
  4454. status = "disabled";
  4455. };
  4456.  
  4457. /* USI_CHUB01_UART */
  4458. serial_22: uart@13AE0000 {
  4459. compatible = "samsung,exynos-uart";
  4460. samsung,separate-uart-clk;
  4461. reg = <0x0 0x13ae0000 0x100>;
  4462. samsung,fifo-size = <64>;
  4463. interrupts = <0 INTREQ__USI_CHUB01 0>;
  4464. pinctrl-names = "default";
  4465. pinctrl-0 = <&uart22_bus_single>; /* or _bus_dual */
  4466. samsung,usi-serial-v2;
  4467. clocks = <&clock GATE_USI_CHUB01>, <&clock CHUB_USI01>;
  4468. clock-names = "gate_pclk22", "gate_uart22";
  4469. status = "disabled";
  4470. };
  4471.  
  4472. coresight@1e000000 {
  4473. compatible = "exynos,coresight";
  4474. base = <0x1e000000>;
  4475. sj-offset = <0x6000>;
  4476. /* coresight component count */
  4477. funnel-num = <3>;
  4478. etf-num = <2>;
  4479.  
  4480. cl0_cpu0@800000 {
  4481. device_type = "cs";
  4482. dbg-offset = <0x810000>;
  4483. etm-offset = <0x840000>;
  4484. funnel-port = <1 0>;
  4485. };
  4486. cl0_cpu1@900000 {
  4487. device_type = "cs";
  4488. dbg-offset = <0x910000>;
  4489. etm-offset = <0x940000>;
  4490. funnel-port = <1 1>;
  4491. };
  4492. cl0_cpu2@A00000 {
  4493. device_type = "cs";
  4494. dbg-offset = <0xA10000>;
  4495. etm-offset = <0xA40000>;
  4496. funnel-port = <1 2>;
  4497. };
  4498. cl0_cpu3@B00000 {
  4499. device_type = "cs";
  4500. dbg-offset = <0xB10000>;
  4501. etm-offset = <0xB40000>;
  4502. funnel-port = <1 3>;
  4503. };
  4504. cl1_cpu0@400000 {
  4505. device_type = "cs";
  4506. dbg-offset = <0x410000>;
  4507. etm-offset = <0x440000>;
  4508. funnel-port = <0 0>;
  4509. };
  4510. cl1_cpu1@500000 {
  4511. device_type = "cs";
  4512. dbg-offset = <0x510000>;
  4513. etm-offset = <0x540000>;
  4514. funnel-port = <0 1>;
  4515. };
  4516. cl1_cpu2@600000 {
  4517. device_type = "cs";
  4518. dbg-offset = <0x610000>;
  4519. etm-offset = <0x640000>;
  4520. funnel-port = <0 2>;
  4521. };
  4522. cl1_cpu3@700000 {
  4523. device_type = "cs";
  4524. dbg-offset = <0x710000>;
  4525. etm-offset = <0x740000>;
  4526. funnel-port = <0 3>;
  4527. };
  4528. cs_etf0: cs_etf0@C000 {
  4529. device_type = "etf";
  4530. offset = <0x4000>;
  4531. funnel-port = <2 0>;
  4532. };
  4533. cs_etf1: cs_etf1@5000 {
  4534. device_type = "etf";
  4535. offset = <0x5000>;
  4536. funnel-port = <2 1>;
  4537. };
  4538. cs_funnel0@4000 {
  4539. device_type = "funnel";
  4540. offset = <0x7000>;
  4541. };
  4542. cs_funnel1@9000 {
  4543. device_type = "funnel";
  4544. offset = <0x8000>;
  4545. };
  4546. cs_funnelm2@9000 {
  4547. device_type = "funnel";
  4548. offset = <0x9000>;
  4549. };
  4550. cs_etr@A000 {
  4551. device_type = "etr";
  4552. samsung,cs-sfr = <0x1E00c000 0x100>;
  4553. samsung,q-offset = <0x2c>;
  4554. offset = <0xA000>;
  4555. };
  4556. };
  4557.  
  4558. sec_pwm: pwm@10510000 {
  4559. compatible = "samsung,s3c6400-pwm";
  4560. reg = <0x0 0x10510000 0x1000>;
  4561. samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
  4562. #pwm-cells = <3>;
  4563. clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock OSCCLK>;
  4564. clock-names = "pwm_pclk", "pwm_sclk";
  4565. status = "ok";
  4566. };
  4567.  
  4568. dwmmc_2: dwmmc2@11500000 {
  4569. compatible = "samsung,exynos-dw-mshc";
  4570. reg = <0x0 0x11500000 0x2000>;
  4571. reg-names = "dw_mmc";
  4572. interrupts = <0 INTREQ__MMC_CARD 0>;
  4573. #address-cells = <1>;
  4574. #size-cells = <0>;
  4575. clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>;
  4576. clock-names = "ciu", "ciu_gate";
  4577. status = "disabled";
  4578. };
  4579.  
  4580. abox_gic: abox_gic@0x17CF0000 {
  4581. compatible = "samsung,abox_gic";
  4582. reg = <0x0 0x17CF1000 0x1000>, <0x0 0x17CF2000 0x1004>;
  4583. reg-names = "gicd", "gicc";
  4584. interrupts = <0 INTREQ__ABOX_GIC400 0>;
  4585. };
  4586.  
  4587. abox: abox@0x17C50000 {
  4588. compatible = "samsung,abox";
  4589. reg = <0x0 0x17C50000 0x10000>, <0x0 0x17C10000 0x10000>, <0x0 0x17D00000 0x31000>;
  4590. reg-names = "sfr", "sysreg", "sram";
  4591. #address-cells = <2>;
  4592. #size-cells = <1>;
  4593. ranges;
  4594. quirks = "try to asrc off";
  4595. #sound-dai-cells = <1>;
  4596. samsung,power-domain = <&pd_aud>;
  4597. ipc_tx_offset = <0x30000>;
  4598. ipc_rx_offset = <0x30300>;
  4599. ipc_tx_ack_offset = <0x302FC>;
  4600. ipc_rx_ack_offset = <0x305FC>;
  4601. abox_gic = <&abox_gic>;
  4602. clocks = <&clock PLL_OUT_AUD>, <&clock GATE_ABOX_DUMMY>,
  4603. <&clock DOUT_CLK_ABOX_AUDIF>, <&clock DOUT_CLK_ABOX_DMIC>,
  4604. <&clock DOUT_CLK_ABOX_ACLK>;
  4605. clock-names = "pll", "cpu", "audif", "dmic", "bus";
  4606. uaif_max_div = <512>;
  4607. iommus = <&sysmmu_aud>;
  4608. pm_qos_int = <0 0 0 0 0>;
  4609. pm_qos_aud = <1180000 800000 590000 394000 0>;
  4610.  
  4611. abox_rdma_0: abox_rdma@0x17C51000 {
  4612. compatible = "samsung,abox-rdma";
  4613. reg = <0x0 0x17C51000 0x100>;
  4614. id = <0>;
  4615. type = "normal";
  4616. };
  4617.  
  4618. abox_rdma_1: abox_rdma@0x17C51100 {
  4619. compatible = "samsung,abox-rdma";
  4620. reg = <0x0 0x17C51100 0x100>;
  4621. id = <1>;
  4622. type = "normal";
  4623. };
  4624.  
  4625. abox_rdma_2: abox_rdma@0x17C51200 {
  4626. compatible = "samsung,abox-rdma";
  4627. reg = <0x0 0x17C51200 0x100>;
  4628. id = <2>;
  4629. type = "normal";
  4630. };
  4631.  
  4632. abox_rdma_3: abox_rdma@0x17C51300 {
  4633. compatible = "samsung,abox-rdma";
  4634. reg = <0x0 0x17C51300 0x100>;
  4635. id = <3>;
  4636. type = "sync";
  4637. };
  4638.  
  4639. abox_rdma_4: abox_rdma@0x17C51400 {
  4640. compatible = "samsung,abox-rdma";
  4641. reg = <0x0 0x17C51400 0x100>;
  4642. id = <4>;
  4643. type = "call";
  4644. };
  4645.  
  4646. abox_rdma_5: abox_rdma@0x17C51500 {
  4647. compatible = "samsung,abox-rdma";
  4648. reg = <0x0 0x17C51500 0x100>, <0x0 0x17D30600 0x70>;
  4649. id = <5>;
  4650. type = "compress";
  4651. };
  4652.  
  4653. abox_rdma_6: abox_rdma@0x17C51600 {
  4654. compatible = "samsung,abox-rdma";
  4655. reg = <0x0 0x17C51600 0x100>;
  4656. id = <6>;
  4657. type = "realtime";
  4658. };
  4659.  
  4660. abox_rdma_7: abox_rdma@0x17C51700 {
  4661. compatible = "samsung,abox-rdma";
  4662. reg = <0x0 0x17C51700 0x100>;
  4663. id = <7>;
  4664. type = "realtime";
  4665. };
  4666.  
  4667. abox_wdma_0: abox_wdma@0x17C52000 {
  4668. compatible = "samsung,abox-wdma";
  4669. reg = <0x0 0x17C52000 0x100>;
  4670. id = <0>;
  4671. type = "realtime";
  4672. };
  4673.  
  4674. abox_wdma_1: abox_wdma@0x17C52100 {
  4675. compatible = "samsung,abox-wdma";
  4676. reg = <0x0 0x17C52100 0x100>;
  4677. id = <1>;
  4678. type = "normal";
  4679. };
  4680.  
  4681. abox_wdma_2: abox_wdma@0x17C52200 {
  4682. compatible = "samsung,abox-wdma";
  4683. reg = <0x0 0x17C52200 0x100>;
  4684. id = <2>;
  4685. type = "call";
  4686. };
  4687.  
  4688. abox_wdma_3: abox_wdma@0x17C52300 {
  4689. compatible = "samsung,abox-wdma";
  4690. reg = <0x0 0x17C52300 0x100>;
  4691. id = <3>;
  4692. type = "realtime";
  4693. };
  4694.  
  4695. abox_wdma_4: abox_wdma@0x17C52400 {
  4696. compatible = "samsung,abox-wdma";
  4697. reg = <0x0 0x17C52400 0x100>;
  4698. id = <4>;
  4699. type = "vi-sensing";
  4700. };
  4701.  
  4702. abox_uaif_0: abox_uaif@0x17C50500 {
  4703. compatible = "samsung,abox-uaif";
  4704. reg = <0x0 0x17C50500 0x10>;
  4705. id = <0>;
  4706. clocks = <&clock DOUT_CLK_ABOX_UAIF0>, <&clock GATE_ABOX_BCLK0>;
  4707. clock-names = "bclk", "bclk_gate";
  4708. pinctrl-names = "default", "sleep";
  4709. pinctrl-0 = <&aud_i2s0_bus>;
  4710. pinctrl-1 = <&aud_i2s0_idle>;
  4711. };
  4712.  
  4713. abox_uaif_1: abox_uaif@0x17C50510 {
  4714. compatible = "samsung,abox-uaif";
  4715. reg = <0x0 0x17C50510 0x10>;
  4716. id = <1>;
  4717. clocks = <&clock DOUT_CLK_ABOX_UAIF1>, <&clock GATE_ABOX_BCLK1>;
  4718. clock-names = "bclk", "bclk_gate";
  4719. pinctrl-names = "default", "sleep";
  4720. pinctrl-0 = <&aud_i2s1_bus>;
  4721. pinctrl-1 = <&aud_i2s1_idle>;
  4722. };
  4723.  
  4724. abox_uaif_2: abox_uaif@0x17C50520 {
  4725. compatible = "samsung,abox-uaif";
  4726. reg = <0x0 0x17C50520 0x10>;
  4727. id = <2>;
  4728. clocks = <&clock DOUT_CLK_ABOX_UAIF2>, <&clock GATE_ABOX_BCLK2>;
  4729. clock-names = "bclk", "bclk_gate";
  4730. pinctrl-names = "default", "sleep";
  4731. pinctrl-0 = <&aud_i2s2_bus>;
  4732. pinctrl-1 = <&aud_i2s2_idle>;
  4733. };
  4734.  
  4735. abox_uaif_3: abox_uaif@0x17C50530 {
  4736. compatible = "samsung,abox-uaif";
  4737. reg = <0x0 0x17C50530 0x10>;
  4738. id = <3>;
  4739. clocks = <&clock DOUT_CLK_ABOX_UAIF3>, <&clock GATE_ABOX_BCLK3>;
  4740. clock-names = "bclk", "bclk_gate";
  4741. pinctrl-names = "default", "sleep";
  4742. pinctrl-0 = <&aud_i2s3_bus>;
  4743. pinctrl-1 = <&aud_i2s3_idle>;
  4744. };
  4745.  
  4746. abox_dsif: abox_dsif@0x17C50550 {
  4747. compatible = "samsung,abox-dsif";
  4748. reg = <0x0 0x17C50550 0x10>;
  4749. id = <5>;
  4750. clocks = <&clock DOUT_CLK_ABOX_DSIF>, <&clock GATE_ABOX_BCLK_DSIF>;
  4751. clock-names = "bclk", "bclk_gate";
  4752. /* DSIF and UAIF2 shares GPIO
  4753. * pinctrl-names = "default", "sleep";
  4754. * pinctrl-0 = <&aud_dsd_bus>;
  4755. * pinctrl-1 = <&aud_dsd_idle>;
  4756. */
  4757. };
  4758.  
  4759. abox_effect: abox_effect@0x17D2E000 {
  4760. compatible = "samsung,abox-effect";
  4761. reg = <0x0 0x17D2E000 0x1000>;
  4762. reg-names = "reg";
  4763. abox = <&abox>;
  4764. };
  4765.  
  4766. abox_debug: abox_debug@0 {
  4767. compatible = "samsung,abox-debug";
  4768. memory-region = <&abox_rmem>;
  4769. reg = <0x0 0x0 0x0>;
  4770. };
  4771.  
  4772. abox_vss: abox_vss@0 {
  4773. compatible = "samsung,abox-vss";
  4774. magic_offset = <0x600000>;
  4775. reg = <0x0 0x0 0x0>;
  4776. };
  4777.  
  4778. ext_bin_0: ext_bin@0 {
  4779. status = "disabled";
  4780. samsung,name = "dsm.bin";
  4781. samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */
  4782. samsung,offset = <0x502000>;
  4783. };
  4784. ext_bin_1: ext_bin@1 {
  4785. status = "okay";
  4786. samsung,name = "AP_AUDIO_SLSI.bin";
  4787. samsung,area = <1>;
  4788. samsung,offset = <0x7E0000>;
  4789. };
  4790. ext_bin_2: ext_bin@2 {
  4791. status = "okay";
  4792. samsung,name = "APBargeIn_AUDIO_SLSI.bin";
  4793. samsung,area = <1>;
  4794. samsung,offset = <0x7DC000>;
  4795. };
  4796. ext_bin_3: ext_bin@3 {
  4797. status = "disabled";
  4798. samsung,name = "SoundBoosterParam.bin";
  4799. samsung,area = <1>;
  4800. samsung,offset = <0x4FC000>;
  4801. };
  4802. ext_bin_4: ext_bin@4 {
  4803. status = "okay";
  4804. samsung,name = "APDV_AUDIO_SLSI.bin";
  4805. samsung,area = <1>;
  4806. samsung,offset = <0x4D0000>;
  4807. };
  4808. ext_bin_5: ext_bin@5 {
  4809. status = "okay";
  4810. samsung,name = "APBiBF_AUDIO_SLSI.bin";
  4811. samsung,area = <1>;
  4812. samsung,offset = <0x7DF000>;
  4813. };
  4814. ext_bin_6: ext_bin@6 {
  4815. status = "disabled";
  4816. samsung,name = "dummy.bin";
  4817. samsung,area = <1>;
  4818. samsung,offset = <0x800000>;
  4819. };
  4820. ext_bin_7: ext_bin@7 {
  4821. status = "disabled";
  4822. samsung,name = "dummy.bin";
  4823. samsung,area = <1>;
  4824. samsung,offset = <0x800000>;
  4825. };
  4826. };
  4827.  
  4828. /* tbase */
  4829. tee {
  4830. compatible = "samsung,exynos-tee";
  4831. interrupts = <0 233 0>;
  4832. };
  4833.  
  4834. seclog {
  4835. compatible = "samsung,exynos-seclog";
  4836. interrupts = <0 INTREQ__PPMU_DPUD1_UPPER_OR_NORMAL 0>;
  4837. };
  4838.  
  4839. /* Secure RPMB */
  4840. ufs-srpmb {
  4841. compatible = "samsung,ufs-srpmb";
  4842. interrupts = <0 460 0>;
  4843. };
  4844.  
  4845. exynos_dm: exynos-dm@17000000 {
  4846. compatible = "samsung,exynos-dvfs-manager";
  4847. reg = <0x0 0x17000000 0x0>;
  4848. acpm-ipc-channel = <1>;
  4849. cpufreq_cl0 {
  4850. dm-index = <DM_CPU_CL0>;
  4851. available = "true";
  4852. cal_id = <ACPM_DVFS_CPUCL0>;
  4853. };
  4854. cpufreq_cl1 {
  4855. dm-index = <DM_CPU_CL1>;
  4856. available = "true";
  4857. cal_id = <ACPM_DVFS_CPUCL1>;
  4858. };
  4859. devfreq_mif {
  4860. dm-index = <DM_MIF>;
  4861. available = "true";
  4862. policy_use = "true";
  4863. cal_id = <ACPM_DVFS_MIF>;
  4864. };
  4865. devfreq_int {
  4866. dm-index = <DM_INT>;
  4867. available = "true";
  4868. policy_use = "true";
  4869. cal_id = <ACPM_DVFS_INT>;
  4870. };
  4871. devfreq_intcam {
  4872. dm-index = <DM_INTCAM>;
  4873. available = "true";
  4874. cal_id = <ACPM_DVFS_INTCAM>;
  4875. };
  4876. devfreq_fsys0 {
  4877. dm-index = <DM_FSYS0>;
  4878. available = "true";
  4879. cal_id = <ACPM_DVFS_FSYS0>;
  4880. };
  4881. devfreq_cam {
  4882. dm-index = <DM_CAM>;
  4883. available = "true";
  4884. cal_id = <ACPM_DVFS_CAM>;
  4885. };
  4886. devfreq_disp {
  4887. dm-index = <DM_DISP>;
  4888. available = "true";
  4889. cal_id = <ACPM_DVFS_DISP>;
  4890. };
  4891. devfreq_aud {
  4892. dm-index = <DM_AUD>;
  4893. available = "true";
  4894. cal_id = <ACPM_DVFS_AUD>;
  4895. };
  4896. devfreq_iva {
  4897. dm-index = <DM_IVA>;
  4898. available = "true";
  4899. cal_id = <ACPM_DVFS_IVA>;
  4900. };
  4901. devfreq_score {
  4902. dm-index = <DM_SCORE>;
  4903. available = "true";
  4904. cal_id = <ACPM_DVFS_SCORE>;
  4905. };
  4906. dvfs_gpu {
  4907. dm-index = <DM_GPU>;
  4908. available = "false";
  4909. cal_id = <ACPM_DVFS_G3D>;
  4910. };
  4911. };
  4912.  
  4913. schedutil {
  4914. domain@0 {
  4915. device_type = "freqvar-tune";
  4916. shared-cpus = "0-3";
  4917.  
  4918. boost_table = < 100 598000 60 715000 30 832000 20 949000 10 1053000 0 >;
  4919. up_rate_limit_table = < 5 >;
  4920. down_rate_limit_table = < 5 >;
  4921. upscale_ratio_table = < 80 >;
  4922. };
  4923. domain@1 {
  4924. device_type = "freqvar-tune";
  4925. shared-cpus = "4-7";
  4926.  
  4927. boost_table = < 20 858000 15 962000 5 1261000 0 >;
  4928. up_rate_limit_table = < 5 >;
  4929. down_rate_limit_table = < 5 >;
  4930. upscale_ratio_table = < 80 >;
  4931. };
  4932. };
  4933.  
  4934. cpu_hotplug {
  4935. compatible = "exynos, cpu_hotplug";
  4936. boot_lock_time = <40>;
  4937. fast_hp_cpus = "5-7";
  4938. };
  4939.  
  4940. hotplug_governor {
  4941. compatible = "exynos, hotplug_governor";
  4942.  
  4943. single_change_ms = <30>;
  4944. dual_change_ms = <30>;
  4945. quad_change_ms = <15>;
  4946. big_heavy_thr = <600>;
  4947. lit_heavy_thr = <180>;
  4948. big_idle_thr = <106>;
  4949. lit_idle_thr = <46>;
  4950. ldsum_heavy_thr = <800>;
  4951. ldsum_enabled = <0>;
  4952. skip_lit_enabled = <0>;
  4953. cl_busy_ratio = <65>;
  4954. /* single_freq is parsed from ECT */
  4955. dual_freq = <2314000>;
  4956. triple_freq = <1794000>;
  4957. quad_freq = <1794000>;
  4958. cal-id = <ACPM_DVFS_CPUCL1>;
  4959. };
  4960.  
  4961. schedutil_gov {
  4962. schedutil_domain0: domain@0 {
  4963. device_type = "schedutil-domain";
  4964. shared-cpus = "0-3";
  4965.  
  4966. enabled = <0>; /* Disable */
  4967. qos_min_class = <3>;
  4968. };
  4969.  
  4970. schedutil_domain1: domain@1 {
  4971. device_type = "schedutil-domain";
  4972. shared-cpus = "4-7";
  4973.  
  4974. enabled = <1>; /* Enabled */
  4975. expired_time = <80>; /* 80ms */
  4976. qos_min_class = <5>;
  4977. };
  4978. };
  4979.  
  4980. cpufreq {
  4981. cpufreq_domain0: domain@0 {
  4982. device_type = "cpufreq-domain";
  4983. sibling-cpus = "0-3";
  4984. cal-id = <ACPM_DVFS_CPUCL0>;
  4985. dm-type = <DM_CPU_CL0>;
  4986.  
  4987. min-freq = <455000>;
  4988.  
  4989. /* PM QoS Class ID*/
  4990. pm_qos-min-class = <3>;
  4991. pm_qos-max-class = <4>;
  4992.  
  4993. user-default-qos = <715000>;
  4994.  
  4995. #cooling-cells = <2>; /* min followed by max */
  4996.  
  4997. dm-constraints {
  4998. mif-perf {
  4999. const-type = <CONSTRAINT_MIN>;
  5000. dm-type = <DM_MIF>;
  5001. /* cpu mif */
  5002. table = < 2002000 845000
  5003. 1898000 845000
  5004. 1794000 845000
  5005. 1690000 845000
  5006. 1456000 676000
  5007. 1248000 676000
  5008. 1053000 676000
  5009. 949000 676000
  5010. 832000 546000
  5011. 715000 546000
  5012. 598000 421000
  5013. 455000 0
  5014. >;
  5015. };
  5016. mif-skew {
  5017. guidance;
  5018. const-type = <CONSTRAINT_MIN>;
  5019. dm-type = <DM_MIF>;
  5020. ect-name = "dvfs_cpucl0";
  5021. };
  5022. };
  5023. };
  5024. cpufreq_domain1: domain@1 {
  5025. device_type = "cpufreq-domain";
  5026. sibling-cpus = "4-7";
  5027. cal-id = <ACPM_DVFS_CPUCL1>;
  5028. dm-type = <DM_CPU_CL1>;
  5029.  
  5030. min-freq = <650000>;
  5031. max-freq = <1794000>;
  5032. policy-max = <1794000>;
  5033.  
  5034. /* PM QoS Class ID*/
  5035. pm_qos-min-class = <5>;
  5036. pm_qos-max-class = <6>;
  5037.  
  5038. pm_qos-booting = <1794000>;
  5039.  
  5040. #cooling-cells = <2>; /* min followed by max */
  5041.  
  5042. dm-constraints {
  5043. mif-perf {
  5044. const-type = <CONSTRAINT_MIN>;
  5045. dm-type = <DM_MIF>;
  5046. /* cpu mif */
  5047. table = < 2964000 1794000
  5048. 2860000 1794000
  5049. 2704000 1794000
  5050. 2652000 1794000
  5051. 2496000 1794000
  5052. 2314000 1794000
  5053. 2158000 1794000
  5054. 2002000 1794000
  5055. 1924000 1794000
  5056. 1794000 1794000
  5057. 1690000 1539000
  5058. 1586000 1014000
  5059. 1469000 845000
  5060. 1261000 676000
  5061. 1170000 676000
  5062. 1066000 676000
  5063. 962000 546000
  5064. 858000 546000
  5065. 741000 421000
  5066. 650000 421000
  5067. 598000 421000 >;
  5068. };
  5069. mif-skew {
  5070. guidance;
  5071. const-type = <CONSTRAINT_MIN>;
  5072. dm-type = <DM_MIF>;
  5073. ect-name = "dvfs_cpucl1";
  5074. };
  5075. };
  5076. };
  5077. };
  5078.  
  5079. tmuctrl_0: BIG@10070000 {
  5080. compatible = "samsung,exynos9810-tmu";
  5081. reg = <0x0 0x10070000 0x700>;
  5082. interrupts = <0 INTREQ__TMU_TMU_TOP 0>;
  5083. tmu_name = "BIG";
  5084. id = <0>;
  5085. sensors = <94>; /* 0x5E */
  5086. sensing_mode = "balance";
  5087. hotplug_enable = <1>;
  5088. hotplug_in_threshold = <91>;
  5089. hotplug_out_threshold = <96>;
  5090. #include "exynos9810-tmu-sensor-conf.dtsi"
  5091. };
  5092.  
  5093. tmuctrl_1: LITTLE@10070000 {
  5094. compatible = "samsung,exynos9810-tmu";
  5095. reg = <0x0 0x10070000 0x700>;
  5096. interrupts = <0 INTREQ__TMU_TMU_TOP 0>;
  5097. tmu_name = "LITTLE";
  5098. id = <1>;
  5099. sensors = <32>; /* 0x20 */
  5100. sensing_mode = "max";
  5101. #include "exynos9810-tmu-sensor-conf.dtsi"
  5102. };
  5103.  
  5104. tmuctrl_2: G3D@10074000 {
  5105. compatible = "samsung,exynos9810-tmu";
  5106. reg = <0x0 0x10074000 0x700>;
  5107. interrupts = <0 INTREQ__TMU_TMU_SUB 0>;
  5108. tmu_name = "G3D";
  5109. id = <2>;
  5110. sensors = <2>; /* 0x02 */
  5111. sensing_mode = "max";
  5112. #include "exynos9810-tmu-sensor-conf.dtsi"
  5113. };
  5114.  
  5115. tmuctrl_3: ISP@10074000 {
  5116. compatible = "samsung,exynos9810-tmu";
  5117. reg = <0x0 0x10074000 0x700>;
  5118. interrupts = <0 INTREQ__TMU_TMU_SUB 0>;
  5119. tmu_name = "ISP";
  5120. id = <3>;
  5121. sensors = <4>; /* 0x04 */
  5122. sensing_mode = "max";
  5123. #include "exynos9810-tmu-sensor-conf.dtsi"
  5124. };
  5125.  
  5126. acpm_tmu {
  5127. acpm-ipc-channel = <12>;
  5128. };
  5129.  
  5130. thermal-zones {
  5131. big_thermal: BIG {
  5132. zone_name = "BIG_THERMAL";
  5133. polling-delay-passive = <50>;
  5134. polling-delay = <1000>;
  5135. thermal-sensors = <&tmuctrl_0>;
  5136. governor = "power_allocator";
  5137. sustainable-power = <0>;
  5138. k_po = <0>;
  5139. k_pu = <0>;
  5140. k_i = <0>;
  5141. i_max = <0>;
  5142. integral_cutoff = <0>;
  5143.  
  5144. trips {
  5145. big_cold: big-cold {
  5146. temperature = <20000>;
  5147. hysteresis = <5000>; /* millicelsius */
  5148. type = "active";
  5149. };
  5150. big_switch_on: big-switch-on {
  5151. temperature = <55000>; /* millicelsius */
  5152. hysteresis = <2000>; /* millicelsius */
  5153. type = "active";
  5154. };
  5155. big_control_temp: big-control-temp {
  5156. temperature = <83000>; /* millicelsius */
  5157. hysteresis = <5000>; /* millicelsius */
  5158. type = "passive";
  5159. };
  5160. big_alert0: big-alert0 {
  5161. temperature = <95000>; /* millicelsius */
  5162. hysteresis = <5000>; /* millicelsius */
  5163. type = "active";
  5164. };
  5165. big_alert1: big-alert1 {
  5166. temperature = <100000>; /* millicelsius */
  5167. hysteresis = <5000>; /* millicelsius */
  5168. type = "active";
  5169. };
  5170. big_alert2: big-alert2 {
  5171. temperature = <105000>; /* millicelsius */
  5172. hysteresis = <5000>; /* millicelsius */
  5173. type = "active";
  5174. };
  5175. big_alert3: big-alert3 {
  5176. temperature = <110000>; /* millicelsius */
  5177. hysteresis = <5000>; /* millicelsius */
  5178. type = "active";
  5179. };
  5180. big_hot: big-hot {
  5181. temperature = <115000>; /* millicelsius */
  5182. hysteresis = <5000>; /* millicelsius */
  5183. type = "hot";
  5184. };
  5185. };
  5186.  
  5187. cooling-maps {
  5188. map0 {
  5189. trip = <&big_control_temp>;
  5190. cooling-device = <&cpufreq_domain1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  5191. };
  5192. };
  5193. };
  5194.  
  5195. little_thermal: LITTLE {
  5196. zone_name = "LITTLE_THERMAL";
  5197. polling-delay-passive = <0>;
  5198. polling-delay = <0>;
  5199. thermal-sensors = <&tmuctrl_1>;
  5200.  
  5201. trips {
  5202. little_alert0: little-alert0 {
  5203. temperature = <20000>; /* millicelsius */
  5204. hysteresis = <5000>; /* millicelsius */
  5205. type = "active";
  5206. };
  5207. little_alert1: little-alert1 {
  5208. temperature = <76000>; /* millicelsius */
  5209. hysteresis = <5000>; /* millicelsius */
  5210. type = "active";
  5211. };
  5212. little_alert2: little-alert2 {
  5213. temperature = <81000>; /* millicelsius */
  5214. hysteresis = <5000>; /* millicelsius */
  5215. type = "active";
  5216. };
  5217. little_alert3: little-alert3 {
  5218. temperature = <86000>; /* millicelsius */
  5219. hysteresis = <5000>; /* millicelsius */
  5220. type = "active";
  5221. };
  5222. little_alert4: little-alert4 {
  5223. temperature = <91000>; /* millicelsius */
  5224. hysteresis = <5000>; /* millicelsius */
  5225. type = "active";
  5226. };
  5227. little_alert5: little-alert5 {
  5228. temperature = <96000>; /* millicelsius */
  5229. hysteresis = <5000>; /* millicelsius */
  5230. type = "active";
  5231. };
  5232. little_alert6: little-alert6 {
  5233. temperature = <101000>; /* millicelsius */
  5234. hysteresis = <5000>; /* millicelsius */
  5235. type = "active";
  5236. };
  5237. little_hot: little-hot {
  5238. temperature = <115000>; /* millicelsius */
  5239. hysteresis = <5000>; /* millicelsius */
  5240. type = "hot";
  5241. };
  5242. };
  5243.  
  5244. cooling-maps {
  5245. map0 {
  5246. trip = <&little_alert0>;
  5247. /* Corresponds to 1794MHz at freq_table */
  5248. cooling-device = <&cpufreq_domain0 0 0>;
  5249. };
  5250. map1 {
  5251. trip = <&little_alert1>;
  5252. /* Corresponds to 1690MHz at freq_table */
  5253. cooling-device = <&cpufreq_domain0 0 0>;
  5254. };
  5255. map2 {
  5256. trip = <&little_alert2>;
  5257. /* Corresponds to 1456MHz at freq_table */
  5258. cooling-device = <&cpufreq_domain0 0 0>;
  5259. };
  5260. map3 {
  5261. trip = <&little_alert3>;
  5262. /* Corresponds to 1248MHz at freq_table */
  5263. cooling-device = <&cpufreq_domain0 0 0>;
  5264. };
  5265. map4 {
  5266. trip = <&little_alert4>;
  5267. /* Corresponds to 1053MHz at freq_table */
  5268. cooling-device = <&cpufreq_domain0 0 0>;
  5269. };
  5270. map5 {
  5271. trip = <&little_alert5>;
  5272. /* Corresponds to 455MHz at freq_table */
  5273. cooling-device = <&cpufreq_domain0 0 0>;
  5274. };
  5275. map6 {
  5276. trip = <&little_alert6>;
  5277. /* Corresponds to 455MHz at freq_table */
  5278. cooling-device = <&cpufreq_domain0 0 0>;
  5279. };
  5280. map7 {
  5281. trip = <&little_hot>;
  5282. /* Corresponds to 455MHz at freq_table */
  5283. cooling-device = <&cpufreq_domain0 0 0>;
  5284. };
  5285. };
  5286. };
  5287.  
  5288. gpu_thermal: G3D {
  5289. zone_name = "G3D_THERMAL";
  5290. polling-delay-passive = <100>;
  5291. polling-delay = <0>;
  5292. thermal-sensors = <&tmuctrl_2>;
  5293. governor = "power_allocator";
  5294. sustainable-power = <0>;
  5295. k_po = <0>;
  5296. k_pu = <0>;
  5297. k_i = <0>;
  5298. i_max = <0>;
  5299. integral_cutoff = <0>;
  5300.  
  5301. trips {
  5302. gpu_cold: gpu-cold {
  5303. temperature = <20000>;
  5304. hysteresis = <5000>; /* millicelsius */
  5305. type = "active";
  5306. };
  5307. gpu_switch_on: gpu-switch-on {
  5308. temperature = <78000>; /* millicelsius */
  5309. hysteresis = <2000>; /* millicelsius */
  5310. type = "active";
  5311. };
  5312. gpu_control_temp: gpu-control-temp {
  5313. temperature = <88000>; /* millicelsius */
  5314. hysteresis = <5000>; /* millicelsius */
  5315. type = "passive";
  5316. };
  5317. gpu_alert0: gpu-alert0 {
  5318. temperature = <105000>; /* millicelsius */
  5319. hysteresis = <5000>; /* millicelsius */
  5320. type = "active";
  5321. };
  5322. gpu_alert1: gpu-alert1 {
  5323. temperature = <110000>; /* millicelsius */
  5324. hysteresis = <5000>; /* millicelsius */
  5325. type = "active";
  5326. };
  5327. gpu_alert2: gpu-alert2 {
  5328. temperature = <115000>; /* millicelsius */
  5329. hysteresis = <5000>; /* millicelsius */
  5330. type = "active";
  5331. };
  5332. gpu_alert3: gpu-alert3 {
  5333. temperature = <115000>; /* millicelsius */
  5334. hysteresis = <5000>; /* millicelsius */
  5335. type = "active";
  5336. };
  5337. gpu_hot: gpu-hot {
  5338. temperature = <115000>; /* millicelsius */
  5339. hysteresis = <5000>; /* millicelsius */
  5340. type = "hot";
  5341. };
  5342. };
  5343.  
  5344. cooling-maps {
  5345. map0 {
  5346. trip = <&gpu_control_temp>;
  5347. cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
  5348. };
  5349. };
  5350. };
  5351.  
  5352. isp_thermal: ISP {
  5353. zone_name = "ISP_THERMAL";
  5354. polling-delay-passive = <0>;
  5355. polling-delay = <0>;
  5356. thermal-sensors = <&tmuctrl_3>;
  5357.  
  5358. trips {
  5359. isp_alert0: isp-alert0 {
  5360. temperature = <20000>; /* millicelsius */
  5361. hysteresis = <5000>; /* millicelsius */
  5362. type = "active";
  5363. };
  5364. isp_alert1: isp-alert1 {
  5365. temperature = <91000>; /* millicelsius */
  5366. hysteresis = <5000>; /* millicelsius */
  5367. type = "active";
  5368. };
  5369. isp_alert2: isp-alert2 {
  5370. temperature = <96000>; /* millicelsius */
  5371. hysteresis = <5000>; /* millicelsius */
  5372. type = "active";
  5373. };
  5374. isp_alert3: isp-alert3 {
  5375. temperature = <101000>; /* millicelsius */
  5376. hysteresis = <5000>; /* millicelsius */
  5377. type = "active";
  5378. };
  5379. isp_alert4: isp-alert4 {
  5380. temperature = <101000>; /* millicelsius */
  5381. hysteresis = <5000>; /* millicelsius */
  5382. type = "active";
  5383. };
  5384. isp_alert5: isp-alert5 {
  5385. temperature = <101000>; /* millicelsius */
  5386. hysteresis = <5000>; /* millicelsius */
  5387. type = "active";
  5388. };
  5389. isp_alert6: isp-alert6 {
  5390. temperature = <101000>; /* millicelsius */
  5391. hysteresis = <5000>; /* millicelsius */
  5392. type = "active";
  5393. };
  5394. isp_hot: isp-hot {
  5395. temperature = <115000>; /* millicelsius */
  5396. hysteresis = <5000>; /* millicelsius */
  5397. type = "hot";
  5398. };
  5399. };
  5400.  
  5401. cooling-maps {
  5402. map0 {
  5403. trip = <&isp_alert0>;
  5404. /* Corresponds to No limit */
  5405. cooling-device = <&fimc_is 0 0>;
  5406. };
  5407. map1 {
  5408. trip = <&isp_alert1>;
  5409. /* Corresponds to No limit */
  5410. cooling-device = <&fimc_is 0 0>;
  5411. };
  5412. map2 {
  5413. trip = <&isp_alert2>;
  5414. /* Corresponds to 15fps at freq_table */
  5415. cooling-device = <&fimc_is 0 0>;
  5416. };
  5417. map3 {
  5418. trip = <&isp_alert3>;
  5419. /* Corresponds to 5fps at freq_table */
  5420. cooling-device = <&fimc_is 0 0>;
  5421. };
  5422. map4 {
  5423. trip = <&isp_alert4>;
  5424. /* Corresponds to 5fps at freq_table */
  5425. cooling-device = <&fimc_is 0 0>;
  5426. };
  5427. map5 {
  5428. trip = <&isp_alert5>;
  5429. /* Corresponds to 5fps at freq_table */
  5430. cooling-device = <&fimc_is 0 0>;
  5431. };
  5432. map6 {
  5433. trip = <&isp_alert6>;
  5434. /* Corresponds to 5fps at freq_table */
  5435. cooling-device = <&fimc_is 0 0>;
  5436. };
  5437. map7 {
  5438. trip = <&isp_hot>;
  5439. /* Corresponds to HW trip */
  5440. cooling-device = <&fimc_is 0 0>;
  5441. };
  5442. };
  5443. };
  5444. };
  5445.  
  5446. smc_info: mcinfo@1B8300000 {
  5447. compatible = "samsung,exynos-mcinfo";
  5448. reg = <0x0 0x1B83004C 0x4>,
  5449. <0x0 0x1B93004C 0x4>,
  5450. <0x0 0x1BA3004C 0x4>,
  5451. <0x0 0x1BB3004C 0x4>;
  5452. bit_field = <20 4>;
  5453. /* start bit, width */
  5454. basecnt = <4>;
  5455. irqcnt = <4>;
  5456.  
  5457. interrupts = <0 INTREQ__DMC_TEMPERR_MIF0 0>,
  5458. <0 INTREQ__DMC_TEMPERR_MIF1 0>,
  5459. <0 INTREQ__DMC_TEMPERR_MIF2 0>,
  5460. <0 INTREQ__DMC_TEMPERR_MIF3 0>;
  5461. };
  5462.  
  5463. fimc_is: fimc_is@16290000 {
  5464. compatible = "samsung,exynos5-fimc-is";
  5465. #pb-id-cells = <6>;
  5466. reg = <0x0 0x162F0000 0x100>, /* CSIS-DMA */
  5467. <0x0 0x16290000 0x10000>, /* FIMC-3AA0 */
  5468. <0x0 0x162A0000 0x10000>, /* FIMC-3AA1 */
  5469. <0x0 0x16430000 0x10000>, /* FIMC_ISPLP */
  5470. <0x0 0x16630000 0x10000>, /* FIMC_ISPHQ */
  5471. <0x0 0x16440000 0x4000>, /* MC_SCALER */
  5472. <0x0 0x16510000 0x10000>, /* FIMC-VRA (Set A) */
  5473. <0x0 0x16520000 0x10000>, /* FIMC-VRA (Set B) */
  5474. <0x0 0x16880000 0x10000>, /* DCP */
  5475. <0x0 0x163A0000 0x100>; /* PDP_STAT_DMA */
  5476. interrupts = <0 INTREQ__TAAM_0 0>, /* 3AA0_0 */
  5477. <0 INTREQ__TAAM_1 0>, /* 3AA0_1 */
  5478. <0 INTREQ__TAA_0 0>, /* 3AA1_0 */
  5479. <0 INTREQ__TAA_1 0>, /* 3AA1_1 */
  5480. <0 INTREQ__ISPLP_0 0>, /* ISPLP_0 */
  5481. <0 INTREQ__ISPLP_1 0>, /* ISPLP_1 */
  5482. <0 INTREQ__BLK_ISPHQ_ISPHQ_INTREQ0 0>, /* ISPHQ_0 */
  5483. <0 INTREQ__BLK_ISPHQ_ISPHQ_INTREQ1 0>, /* ISPHQ_1 */
  5484. <0 INTREQ__MC_SCALER_0 0>, /* MC_SC_0 */
  5485. <0 INTREQ__MC_SCALER_1 0>, /* MC_SC_1 */
  5486. <0 INTREQ__VRA 0>, /* VRA_1 */
  5487. <0 INTREQ_BLK_DCRD_DCP_IntReq_0 0>, /* DCP_0 */
  5488. <0 INTREQ_BLK_DCRD_DCP_IntReq_1 0>; /* DCP_1 */
  5489. pinctrl-names = "default","release";
  5490. pinctrl-0 = <>;
  5491. pinctrl-1 = <>;
  5492. samsung,power-domain = <&pd_isplp>;
  5493. clocks = <&clock GATE_IS_ISPHQ>,
  5494. <&clock GATE_IS_ISPHQ_C2COM>,
  5495. <&clock UMUX_CLKCMU_ISPHQ_BUS>,
  5496.  
  5497. <&clock GATE_IS_ISPLP_MC_SCALER>,
  5498. <&clock GATE_IS_ISPLP>,
  5499. <&clock GATE_IS_ISPLP_VRA>,
  5500. <&clock GATE_IS_ISPLP_GDC>,
  5501. <&clock GATE_IS_ISPLP_C2>,
  5502. <&clock UMUX_CLKCMU_ISPLP_BUS>,
  5503. <&clock UMUX_CLKCMU_ISPLP_VRA>,
  5504. <&clock UMUX_CLKCMU_ISPLP_GDC>,
  5505.  
  5506. <&clock GATE_IS_ISPPRE_CSIS0>,
  5507. <&clock GATE_IS_ISPPRE_CSIS1>,
  5508. <&clock GATE_IS_ISPPRE_CSIS2>,
  5509. <&clock GATE_IS_ISPPRE_CSIS3>,
  5510. <&clock GATE_IS_ISPPRE_PDP_DMA>,
  5511. <&clock GATE_IS_ISPPRE_3AA>,
  5512. <&clock GATE_IS_ISPPRE_3AAM>,
  5513. <&clock GATE_IS_ISPPRE_PDP_CORE0>,
  5514. <&clock GATE_IS_ISPPRE_PDP_CORE1>,
  5515. <&clock UMUX_CLKCMU_ISPPRE_BUS>,
  5516.  
  5517. <&clock CIS_CLK0>,
  5518. <&clock CIS_CLK1>,
  5519. <&clock CIS_CLK2>,
  5520. <&clock CIS_CLK3>,
  5521.  
  5522. <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
  5523. <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
  5524. <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
  5525. <&clock GATE_DFTMUX_TOP_CIS_CLK3>;
  5526. clock-names = "GATE_IS_ISPHQ",
  5527. "GATE_IS_ISPHQ_C2COM",
  5528. "UMUX_CLKCMU_ISPHQ_BUS",
  5529.  
  5530. "GATE_IS_ISPLP_MC_SCALER",
  5531. "GATE_IS_ISPLP",
  5532. "GATE_IS_ISPLP_VRA",
  5533. "GATE_IS_ISPLP_GDC",
  5534. "GATE_IS_ISPLP_C2",
  5535. "UMUX_CLKCMU_ISPLP_BUS",
  5536. "UMUX_CLKCMU_ISPLP_VRA",
  5537. "UMUX_CLKCMU_ISPLP_GDC",
  5538.  
  5539. "GATE_IS_ISPPRE_CSIS0",
  5540. "GATE_IS_ISPPRE_CSIS1",
  5541. "GATE_IS_ISPPRE_CSIS2",
  5542. "GATE_IS_ISPPRE_CSIS3",
  5543. "GATE_IS_ISPPRE_PDP_DMA",
  5544. "GATE_IS_ISPPRE_3AA",
  5545. "GATE_IS_ISPPRE_3AAM",
  5546. "GATE_IS_ISPPRE_PDP_CORE0",
  5547. "GATE_IS_ISPPRE_PDP_CORE1",
  5548. "UMUX_CLKCMU_ISPPRE_BUS",
  5549.  
  5550. "CIS_CLK0",
  5551. "CIS_CLK1",
  5552. "CIS_CLK2",
  5553. "CIS_CLK3",
  5554.  
  5555. "MUX_CIS_CLK0",
  5556. "MUX_CIS_CLK1",
  5557. "MUX_CIS_CLK2",
  5558. "MUX_CIS_CLK3";
  5559. status = "ok";
  5560. iommus = <&sysmmu_isppre>, <&sysmmu_isplp0>, <&sysmmu_isplp1>, <&sysmmu_isphq>;
  5561. #cooling-cells = <2>; /* min followed by max */
  5562. ewf-index = <EWF_CMU_BUSC>;
  5563. };
  5564.  
  5565. camerapp_gdc: gdc@16530000 {
  5566. compatible = "samsung,exynos5-camerapp-gdc";
  5567. #pb-id-cells = <6>;
  5568. reg = <0x0 0x16530000 0x10000>; /* GDC */
  5569. interrupts = <0 INTREQ__GDC 0>; /* GDC */
  5570. pinctrl-names = "default","release";
  5571. pinctrl-0 = <>;
  5572. pinctrl-1 = <>;
  5573. samsung,power-domain = <&pd_isplp>;
  5574. clocks = <&clock GATE_IS_ISPLP_GDC>,
  5575. <&clock UMUX_CLKCMU_ISPLP_GDC>;
  5576. clock-names = "gate",
  5577. "gate2";
  5578. status = "ok";
  5579. iommus = <&sysmmu_isplp0>;
  5580. #cooling-cells = <2>; /* min followed by max */
  5581. };
  5582.  
  5583. mipi_phy_csis0_m4s4_top: dphy_m4s4_csis0@0x16210500 {
  5584. /* DCPHY 4.5 Gbps 4lane */
  5585. compatible = "samsung,mipi-phy-m4s4-top";
  5586. samsung,pmu-syscon = <&pmu_system_controller>;
  5587. isolation = <0x70C>; /* PMU address offset */
  5588. reg = <0x0 0x16210500 0x4>; /* SYSREG address for reset */
  5589. reset = <0>; /* reset bit */
  5590. owner = <1>; /* 0: DSI, 1: CSI */
  5591. #phy-cells = <1>;
  5592. };
  5593.  
  5594. mipi_phy_csis2_m4s4_mod: dphy_m4s4_csis2@0x16210500 {
  5595. /* DCPHY 4.5 Gbps 4lane */
  5596. compatible = "samsung,mipi-phy-m4s4-mod";
  5597. samsung,pmu-syscon = <&pmu_system_controller>;
  5598. isolation = <0x710>; /* PMU address offset */
  5599. reset = <1>; /* reset bit */
  5600. owner = <1>; /* 0: DSI, 1: CSI */
  5601. #phy-cells = <1>;
  5602. };
  5603.  
  5604. mipi_phy_csis1_m0s4s2: dphy_m0s4s2_csis1@0x16210500 {
  5605. /* DPHY 2.5 Gbps 4lane */
  5606. compatible = "samsung,mipi-phy-m1s2s2";
  5607. samsung,pmu-syscon = <&pmu_system_controller>;
  5608. isolation = <0x730>; /* PMU address offset */
  5609. reset = <2>; /* reset bit */
  5610. owner = <1>; /* 0: DSI, 1: CSI */
  5611. #phy-cells = <1>;
  5612. };
  5613.  
  5614. mipi_phy_csis3_m0s4s2: dphy_m0s4s2_csis3@0x16210500 {
  5615. /* DPHY 2.5 Gbps 2lane */
  5616. compatible = "samsung,mipi-phy-m1s2s2";
  5617. samsung,pmu-syscon = <&pmu_system_controller>;
  5618. isolation = <0x730>; /* PMU address offset */
  5619. reset = <3>; /* reset bit */
  5620. owner = <1>; /* 0: DSI, 1: CSI */
  5621. #phy-cells = <1>;
  5622. };
  5623.  
  5624. fimc_is_sensor0: fimc_is_sensor@16230000 {
  5625. /* REAR/CSIS0 */
  5626. compatible = "samsung,exynos5-fimc-is-sensor";
  5627. #pb-id-cells = <4>;
  5628. reg = <0x0 0x16230000 0x1000>, /* MIPI-CSI0 */
  5629. <0x0 0x16160000 0x10000>, /* PHY: TOP_M4S4 */
  5630.  
  5631. <0x0 0x162B0000 0x100>, /* VC0 DMA0 */
  5632. <0x0 0x162B0400 0x100>, /* VC0 DMA0 COMMON */
  5633. <0x0 0x162B0100 0x100>, /* VC1 DMA0 */
  5634. <0x0 0x162B0400 0x100>, /* VC1 DMA0 COMMON */
  5635. <0x0 0x162B0200 0x100>, /* VC2 DMA0 */
  5636. <0x0 0x162B0400 0x100>, /* VC2 DMA0 COMMON */
  5637. <0x0 0x162B0300 0x100>, /* VC3 DMA0 */
  5638. <0x0 0x162B0400 0x100>, /* VC3 DMA0 COMMON */
  5639.  
  5640. <0x0 0x162B0000 0x100>, /* VC0 DMA0 */
  5641. <0x0 0x162B0400 0x100>, /* VC0 DMA0 COMMON */
  5642. <0x0 0x16380000 0x100>, /* VC0 DMA4 */
  5643. <0x0 0x16380400 0x100>, /* VC0 DMA4 COMMON */
  5644. <0x0 0x16380100 0x100>, /* VC1 DMA4 */
  5645. <0x0 0x16380400 0x100>, /* VC1 DMA4 COMMON */
  5646. <0x0 0x16380200 0x100>, /* NOTHING */
  5647. <0x0 0x16380400 0x100>; /* NOTHING */
  5648. interrupts = <0 INTREQ__CSIS0 0>, /* MIPI-CSI0 */
  5649. <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC0 DMA0 */
  5650. <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC1 DMA0 */
  5651. <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC2 DMA0 */
  5652. <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC3 DMA0 */
  5653.  
  5654. <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC0 DMA0 */
  5655. <0 INTREQ__PDP0_STAT_DMA 0>, /* VC0 DMA4 */
  5656. <0 INTREQ__PDP0_STAT_DMA 0>, /* VC1 DMA4 */
  5657. <0 INTREQ__PDP0_STAT_DMA 0>; /* NOTHING */
  5658. samsung,power-domain = <&pd_isppre>;
  5659. phys = <&mipi_phy_csis0_m4s4_top 0>;
  5660. phy-names = "csis_dphy";
  5661. clocks = <&clock CIS_CLK0>,
  5662. <&clock CIS_CLK1>,
  5663. <&clock CIS_CLK2>,
  5664. <&clock CIS_CLK3>,
  5665.  
  5666. <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
  5667. <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
  5668. <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
  5669. <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
  5670.  
  5671. <&clock GATE_IS_ISPPRE_CSIS0>,
  5672. <&clock GATE_IS_ISPPRE_CSIS1>,
  5673. <&clock GATE_IS_ISPPRE_CSIS2>,
  5674. <&clock GATE_IS_ISPPRE_CSIS3>;
  5675. clock-names = "CIS_CLK0",
  5676. "CIS_CLK1",
  5677. "CIS_CLK2",
  5678. "CIS_CLK3",
  5679.  
  5680. "MUX_CIS_CLK0",
  5681. "MUX_CIS_CLK1",
  5682. "MUX_CIS_CLK2",
  5683. "MUX_CIS_CLK3",
  5684.  
  5685. "GATE_IS_ISPPRE_CSIS0",
  5686. "GATE_IS_ISPPRE_CSIS1",
  5687. "GATE_IS_ISPPRE_CSIS2",
  5688. "GATE_IS_ISPPRE_CSIS3";
  5689. iommus = <&sysmmu_isppre>;
  5690. };
  5691.  
  5692. fimc_is_sensor1: fimc_is_sensor@16240000 {
  5693. /* FRONT/CSIS0 */
  5694. compatible = "samsung,exynos5-fimc-is-sensor";
  5695. #pb-id-cells = <4>;
  5696. reg = <0x0 0x16240000 0x1000>, /* MIPI-CSI0 */
  5697. <0x0 0x16180000 0x10000>, /* PHY: MODULE_M0S4S2(S4) */
  5698.  
  5699. <0x0 0x162C0000 0x100>, /* VC0 DMA1 */
  5700. <0x0 0x162C0400 0x100>, /* VC0 DMA1 COMMON */
  5701. <0x0 0x162C0100 0x100>, /* VC1 DMA1 */
  5702. <0x0 0x162C0400 0x100>, /* VC1 DMA1 COMMON */
  5703. <0x0 0x162C0200 0x100>, /* VC2 DMA1 */
  5704. <0x0 0x162C0400 0x100>, /* VC2 DMA1 COMMON */
  5705. <0x0 0x162C0300 0x100>, /* VC3 DMA1 */
  5706. <0x0 0x162C0400 0x100>; /* VC3 DMA1 COMMON */
  5707. interrupts = <0 INTREQ__CSIS1 0>, /* MIPI-CSI1 */
  5708. <0 INTREQ__CSIS1_PDP_DMA 0>, /* VC0 DMA1 */
  5709. <0 INTREQ__CSIS1_PDP_DMA 0>, /* VC1 DMA1 */
  5710. <0 INTREQ__CSIS1_PDP_DMA 0>, /* VC2 DMA1 */
  5711. <0 INTREQ__CSIS1_PDP_DMA 0>; /* VC3 DMA1 */
  5712. samsung,power-domain = <&pd_isppre>;
  5713. phys = <&mipi_phy_csis1_m0s4s2 0>;
  5714. phy-names = "csis_dphy";
  5715. clocks = <&clock CIS_CLK0>,
  5716. <&clock CIS_CLK1>,
  5717. <&clock CIS_CLK2>,
  5718. <&clock CIS_CLK3>,
  5719.  
  5720. <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
  5721. <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
  5722. <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
  5723. <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
  5724.  
  5725. <&clock GATE_IS_ISPPRE_CSIS0>,
  5726. <&clock GATE_IS_ISPPRE_CSIS1>,
  5727. <&clock GATE_IS_ISPPRE_CSIS2>,
  5728. <&clock GATE_IS_ISPPRE_CSIS3>;
  5729. clock-names = "CIS_CLK0",
  5730. "CIS_CLK1",
  5731. "CIS_CLK2",
  5732. "CIS_CLK3",
  5733.  
  5734. "MUX_CIS_CLK0",
  5735. "MUX_CIS_CLK1",
  5736. "MUX_CIS_CLK2",
  5737. "MUX_CIS_CLK3",
  5738.  
  5739. "GATE_IS_ISPPRE_CSIS0",
  5740. "GATE_IS_ISPPRE_CSIS1",
  5741. "GATE_IS_ISPPRE_CSIS2",
  5742. "GATE_IS_ISPPRE_CSIS3";
  5743. iommus = <&sysmmu_isppre>;
  5744. };
  5745.  
  5746. fimc_is_sensor2: fimc_is_sensor@16250000 {
  5747. /* REAR_SUB/CSIS2 */
  5748. compatible = "samsung,exynos5-fimc-is-sensor";
  5749. #pb-id-cells = <4>;
  5750. reg = <0x0 0x16250000 0x1000>, /* MIPI-CSI0 */
  5751. <0x0 0x16170000 0x10000>, /* PHY: MODULE_M4S4*/
  5752.  
  5753. <0x0 0x162D0000 0x100>, /* VC0 DMA2 */
  5754. <0x0 0x162D0400 0x100>, /* VC0 DMA2 COMMON */
  5755. <0x0 0x162D0100 0x100>, /* VC1 DMA2 */
  5756. <0x0 0x162D0400 0x100>, /* VC1 DMA2 COMMON */
  5757. <0x0 0x162D0200 0x100>, /* VC2 DMA2 */
  5758. <0x0 0x162D0400 0x100>, /* VC2 DMA2 COMMON */
  5759. <0x0 0x162D0300 0x100>, /* VC3 DMA2 */
  5760. <0x0 0x162D0400 0x100>; /* VC3 DMA2 COMMON */
  5761. interrupts = <0 INTREQ__CSIS2 0>, /* MIPI-CSI2 */
  5762. <0 INTREQ__CSIS2_PDP_DMA 0>, /* VC0 DMA2 */
  5763. <0 INTREQ__CSIS2_PDP_DMA 0>, /* VC1 DMA2 */
  5764. <0 INTREQ__CSIS2_PDP_DMA 0>, /* VC2 DMA2 */
  5765. <0 INTREQ__CSIS2_PDP_DMA 0>; /* VC3 DMA2 */
  5766. samsung,power-domain = <&pd_isppre>;
  5767. phys = <&mipi_phy_csis2_m4s4_mod 0>;
  5768. phy-names = "csis_dphy";
  5769. clocks = <&clock CIS_CLK0>,
  5770. <&clock CIS_CLK1>,
  5771. <&clock CIS_CLK2>,
  5772. <&clock CIS_CLK3>,
  5773.  
  5774. <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
  5775. <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
  5776. <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
  5777. <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
  5778.  
  5779. <&clock GATE_IS_ISPPRE_CSIS0>,
  5780. <&clock GATE_IS_ISPPRE_CSIS1>,
  5781. <&clock GATE_IS_ISPPRE_CSIS2>,
  5782. <&clock GATE_IS_ISPPRE_CSIS3>;
  5783. clock-names = "CIS_CLK0",
  5784. "CIS_CLK1",
  5785. "CIS_CLK2",
  5786. "CIS_CLK3",
  5787.  
  5788. "MUX_CIS_CLK0",
  5789. "MUX_CIS_CLK1",
  5790. "MUX_CIS_CLK2",
  5791. "MUX_CIS_CLK3",
  5792.  
  5793. "GATE_IS_ISPPRE_CSIS0",
  5794. "GATE_IS_ISPPRE_CSIS1",
  5795. "GATE_IS_ISPPRE_CSIS2",
  5796. "GATE_IS_ISPPRE_CSIS3";
  5797. iommus = <&sysmmu_isppre>;
  5798. };
  5799.  
  5800. fimc_is_sensor3: fimc_is_sensor@16260000 {
  5801. /* IRIS/CSIS3 */
  5802. compatible = "samsung,exynos5-fimc-is-sensor";
  5803. #pb-id-cells = <4>;
  5804. reg = <0x0 0x16260000 0x1000>, /* MIPI-CSI0 */
  5805. <0x0 0x16190000 0x10000>, /* PHY: MODULE_M0S4S2(S2) */
  5806.  
  5807. <0x0 0x162E0000 0x100>, /* VC0 DMA3 */
  5808. <0x0 0x162E0400 0x100>, /* VC0 DMA3 COMMON */
  5809. <0x0 0x162E0100 0x100>, /* VC1 DMA3 */
  5810. <0x0 0x162E0400 0x100>, /* VC1 DMA3 COMMON */
  5811. <0x0 0x162E0200 0x100>, /* VC2 DMA3 */
  5812. <0x0 0x162E0400 0x100>, /* VC2 DMA3 COMMON */
  5813. <0x0 0x162E0300 0x100>, /* VC3 DMA3 */
  5814. <0x0 0x162E0400 0x100>; /* VC3 DMA3 COMMON */
  5815. interrupts = <0 INTREQ__CSIS3 0>, /* MIPI-CSI3 */
  5816. <0 INTREQ__CSIS3_PDP_DMA 0>, /* VC0 DMA3 */
  5817. <0 INTREQ__CSIS3_PDP_DMA 0>, /* VC1 DMA3 */
  5818. <0 INTREQ__CSIS3_PDP_DMA 0>, /* VC2 DMA3 */
  5819. <0 INTREQ__CSIS3_PDP_DMA 0>; /* VC3 DMA3 */
  5820. samsung,power-domain = <&pd_isppre>;
  5821. phys = <&mipi_phy_csis3_m0s4s2 0>;
  5822. phy-names = "csis_dphy";
  5823. clocks = <&clock CIS_CLK0>,
  5824. <&clock CIS_CLK1>,
  5825. <&clock CIS_CLK2>,
  5826. <&clock CIS_CLK3>,
  5827.  
  5828. <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
  5829. <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
  5830. <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
  5831. <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
  5832.  
  5833. <&clock GATE_IS_ISPPRE_CSIS0>,
  5834. <&clock GATE_IS_ISPPRE_CSIS1>,
  5835. <&clock GATE_IS_ISPPRE_CSIS2>,
  5836. <&clock GATE_IS_ISPPRE_CSIS3>;
  5837. clock-names = "CIS_CLK0",
  5838. "CIS_CLK1",
  5839. "CIS_CLK2",
  5840. "CIS_CLK3",
  5841.  
  5842. "MUX_CIS_CLK0",
  5843. "MUX_CIS_CLK1",
  5844. "MUX_CIS_CLK2",
  5845. "MUX_CIS_CLK3",
  5846.  
  5847. "GATE_IS_ISPPRE_CSIS0",
  5848. "GATE_IS_ISPPRE_CSIS1",
  5849. "GATE_IS_ISPPRE_CSIS2",
  5850. "GATE_IS_ISPPRE_CSIS3";
  5851. iommus = <&sysmmu_isppre>;
  5852. };
  5853.  
  5854. fimc_is_pdp0: fimc_is_pdp@16270000 {
  5855. /* PDP CORE0 */
  5856. compatible = "samsung,exynos5-fimc-is-pdp";
  5857. reg = <0x0 0x16270000 0x2000>; /* PDP CORE0 */
  5858. interrupts = <0 INTREQ__PDP_CORE0 0>;
  5859. id = <0>;
  5860. };
  5861.  
  5862. fimc_is_pdp1: fimc_is_pdp@16280000 {
  5863. /* PDP CORE1 */
  5864. compatible = "samsung,exynos5-fimc-is-pdp";
  5865. interrupts = <0 INTREQ__PDP_CORE1 0>;
  5866. reg = <0x0 0x16280000 0x2000>; /* PDP CORE1 */
  5867. id = <1>;
  5868. };
  5869.  
  5870. sysreg_fsys1_controller: sysreg-controller@11410000 {
  5871. compatible = "samsung,exynos8895-sysreg", "syscon";
  5872. reg = <0x0 0x11410000 0x1200>;
  5873. };
  5874.  
  5875. sysmmu_pcie: sysmmu@11420000 {
  5876. compatible = "samsung,pcie-sysmmu";
  5877. reg = <0x0 0x11420000 0x9000>;
  5878. interrupts = <0 INTREQ__SYSMMU_FSYS1 0>;
  5879. clock-names = "aclk";
  5880. clocks = <&clock GATE_SYSMMU_FSYS1>;
  5881. port-name = "PCIe";
  5882. #iommu-cells = <0>;
  5883. use-tlb-pinning = "true";
  5884. };
  5885.  
  5886. pcie0@116A0000 {
  5887. compatible = "samsung,exynos-pcie";
  5888. gpios = <&gpf2 2 0x1 /* PERST */>;
  5889. reg = <0x0 0x116A0000 0x1000 /* elbi base */
  5890. 0x0 0x116D0000 0x1000 /* phy base */
  5891. 0x0 0x11411044 0x10 /* sysreg base */
  5892. 0x0 0x11700000 0x1000 /* DBI base */
  5893. 0x0 0x116C0000 0x1FC /* phy pcs base */
  5894. 0x0 0x127FE000 0x2000 /* configuration space */
  5895. 0x0 0x11680000 0x1000>; /* I/A space */
  5896. reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config", "ia";
  5897. interrupts = <0 INTREQ__PCIE_WIFI0 0>; /* IRQ_PULSE */
  5898. samsung,syscon-phandle = <&pmu_system_controller>;
  5899. samsung,sysreg-phandle = <&sysreg_fsys1_controller>;
  5900. clocks = <&clock GATE_PCIE_GEN2_MSTR>;
  5901. pinctrl-names = "default";
  5902. pinctrl-0 = <&pcie0_clkreq &pcie0_perst &pcie_wake>;
  5903. #address-cells = <3>;
  5904. #size-cells = <2>;
  5905. device_type = "pci";
  5906. /* non-prefetchable memory */
  5907. ranges = <0x82000000 0 0x11800000 0 0x11800000 0 0xFF0000>;
  5908. /* ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x20000000>; */
  5909. #interrupt-cells = <1>;
  5910. interrupt-map-mask = <0 0 0 0>;
  5911. interrupt-map = <0 0 0 0 &gic 0 253 0x4>;
  5912. ip-ver = <0x981000>;
  5913. num-lanes = <1>;
  5914. ch-num = <0>;
  5915. pcie-clk-num = <0>;
  5916. phy-clk-num = <0>;
  5917. pcie-pm-qos-int = <0>;
  5918. use-cache-coherency = "false";
  5919. use-msi = "false";
  5920. use-sicd = "true";
  5921. use-sysmmu = "false";
  5922. use-ia = "true";
  5923. max-link-speed = <LINK_SPEED_GEN2>;
  5924. status = "disabled";
  5925. };
  5926.  
  5927. pcie1@116B0000 {
  5928. compatible = "samsung,exynos-pcie";
  5929. gpios = <&gpf2 5 0x1 /* PERST */>;
  5930. reg = <0x0 0x116B0000 0x1000 /* elbi base */
  5931. 0x0 0x116F0000 0x1000 /* phy base */
  5932. 0x0 0x11411054 0x10 /* sysreg base */
  5933. 0x0 0x11710000 0x1000 /* DBI base */
  5934. 0x0 0x116E0000 0x1FC /* phy pcs base */
  5935. 0x0 0x137FE000 0x2000>; /* configuration space */
  5936. reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config";
  5937. interrupts = <0 INTREQ__PCIE_WIFI1 0>; /* IRQ_PULSE */
  5938. samsung,syscon-phandle = <&pmu_system_controller>;
  5939. clocks = <&clock GATE_PCIE_GEN3_MSTR>;
  5940. pinctrl-names = "default";
  5941. pinctrl-0 = <&pcie1_clkreq &pcie1_perst>;
  5942. #address-cells = <3>;
  5943. #size-cells = <2>;
  5944. device_type = "pci";
  5945. /* non-prefetchable memory */
  5946. ranges = <0x82000000 0 0x12800000 0 0x12800000 0 0xFF0000>;
  5947. /* ranges = <0x82000000 0 0x40000000 0 0x40000000 0 0x20000000>; */
  5948. #interrupt-cells = <1>;
  5949. interrupt-map-mask = <0 0 0 0>;
  5950. interrupt-map = <0 0 0 0 &gic 0 254 0x4>;
  5951. ip-ver = <0x981000>;
  5952. num-lanes = <1>;
  5953. ch-num = <1>;
  5954. pcie-clk-num = <0>;
  5955. phy-clk-num = <0>;
  5956. pcie-pm-qos-int = <0>;
  5957. use-cache-coherency = "false";
  5958. use-msi = "false";
  5959. use-sicd = "true";
  5960. use-sysmmu = "false";
  5961. max-link-speed = <LINK_SPEED_GEN3>;
  5962. status = "disabled";
  5963. };
  5964.  
  5965. mailbox_vts: mailbox@0x141B0000 {
  5966. compatible = "samsung,mailbox-asoc";
  5967. reg = <0x0 0x141B0000 0x10000>;
  5968. reg-names = "sfr";
  5969. interrupts = <0 INTREQ__MAILBOX_VTS2AP 0>;
  5970. interrupt-controller;
  5971. #interrupt-cells = <1>;
  5972. };
  5973.  
  5974. vts: vts@0x13870000 {
  5975. compatible = "samsung,vts";
  5976. reg = <0x0 0x13810000 0x1000>, <0x0 0x13B00000 0x10010>, <0x0 0x13870000 0x8>, <0x0 0x13900000 0x67070>,
  5977. <0x0 0x138F0000 0x50>;
  5978. reg-names = "sfr", "baaw", "dmic", "sram", "gpr";
  5979. pinctrl-names = "dmic_default", "amic_default", "idle";
  5980. pinctrl-0 = <&dmic_bus_clk &dmic_pdm>;
  5981. pinctrl-1 = <&amic_bus_clk &amic_pdm>;
  5982. pinctrl-2 = <&mic_bus_clk_idle &dmic_pdm_idle &amic_pdm_idle>;
  5983. samsung,power-domain = <&pd_vts>;
  5984. clocks = <&clock DOUT_CLK_VTS_DMIC>,
  5985. <&clock DOUT_CLK_VTS_DMICIF>, <&clock DOUT_CLK_VTS_DMIC_DIV2>;
  5986. clock-names = "dmic", "dmic_if", "dmic_sync";
  5987. mailbox = <&mailbox_vts>;
  5988. #sound-dai-cells = <1>;
  5989. interrupt-parent = <&mailbox_vts>;
  5990. interrupts = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, <24>, <25>;
  5991. interrupt-names = "error", "boot_completed", "ipc_received", "voice_triggered",
  5992. "trigger_period_elapsed", "record_period_elapsed",
  5993. "debuglog_bufzero", "debuglog_bufone",
  5994. "audio_dump", "log_dump";
  5995. };
  5996.  
  5997. vts_dma0: vts_dma0 {
  5998. compatible = "samsung,vts-dma";
  5999. vts = <&vts>;
  6000. id = <0>;
  6001. type = "vts-trigger";
  6002. };
  6003.  
  6004. vts_dma1: vts_dma1 {
  6005. compatible = "samsung,vts-dma";
  6006. vts = <&vts>;
  6007. id = <1>;
  6008. type = "vts-record";
  6009. };
  6010.  
  6011. cmu_ewf {
  6012. compatible = "samsung,exynos-cmuewf";
  6013. #address-cells = <2>;
  6014. #size-cells = <1>;
  6015. reg = <0x0 0x1A240000 0x1000>;
  6016. };
  6017. };
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