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- /*
- * SAMSUNG EXYNOS9810 SoC device tree source
- *
- * Copyright (c) 2017 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * SAMSUNG EXYNOS9810 SoC device nodes are listed in this file.
- * EXYNOS9810 based board files can include this file and provide
- * values for board specfic bindings.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
- #include <dt-bindings/clock/exynos9810.h>
- #include <dt-bindings/interrupt-controller/exynos9810.h>
- #include <dt-bindings/sysmmu/sysmmu.h>
- #include <dt-bindings/soc/samsung/exynos9810.h>
- #include <dt-bindings/thermal/thermal.h>
- #include <dt-bindings/camera/fimc_is.h>
- #include <dt-bindings/pci/pci.h>
- #include "exynos9810-pinctrl.dtsi"
- #include <dt-bindings/ufs/ufs.h>
- #include "exynos9810-pm-domains.dtsi"
- #include "exynos9810-etm.dtsi"
- #include "exynos9810-inputbooster.dtsi"
- #include "exynos9810-ess.dtsi"
- / {
- compatible = "samsung,armv8", "samsung,exynos9810";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <1>;
- aliases {
- pinctrl0 = &pinctrl_0;
- pinctrl1 = &pinctrl_1;
- pinctrl2 = &pinctrl_2;
- pinctrl3 = &pinctrl_3;
- pinctrl4 = &pinctrl_4;
- pinctrl5 = &pinctrl_5;
- pinctrl6 = &pinctrl_6;
- pinctrl7 = &pinctrl_7;
- pinctrl8 = &pinctrl_8;
- mshc2 = &dwmmc_2;
- usi0 = &usi_0;
- usi1 = &usi_0_i2c;
- usi2 = &usi_1;
- usi3 = &usi_1_i2c;
- usi4 = &usi_2;
- usi5 = &usi_2_i2c;
- usi6 = &usi_3;
- usi7 = &usi_3_i2c;
- usi8 = &usi_4;
- usi9 = &usi_4_i2c;
- usi10 = &usi_5;
- usi11 = &usi_5_i2c;
- usi12 = &usi_6;
- usi13 = &usi_6_i2c;
- usi14 = &usi_7;
- usi15 = &usi_7_i2c;
- usi16 = &usi_8;
- usi17 = &usi_8_i2c;
- usi18 = &usi_9;
- usi19 = &usi_9_i2c;
- usi20 = &usi_10;
- usi21 = &usi_10_i2c;
- usi22 = &usi_11;
- usi23 = &usi_11_i2c;
- usi24 = &usi_12;
- usi25 = &usi_12_i2c;
- usi26 = &usi_13;
- usi27 = &usi_13_i2c;
- usi28 = &usi_14;
- usi29 = &usi_14_i2c;
- usi30 = &usi_00_cmgp;
- usi31 = &usi_00_cmgp_i2c;
- usi32 = &usi_01_cmgp;
- usi33 = &usi_01_cmgp_i2c;
- usi34 = &usi_02_cmgp;
- usi35 = &usi_02_cmgp_i2c;
- usi36 = &usi_03_cmgp;
- usi37 = &usi_03_cmgp_i2c;
- usi38 = &usi_00_chub;
- usi39 = &usi_00_chub_i2c;
- usi40 = &usi_01_chub;
- usi41 = &usi_01_chub_i2c;
- hsi2c0 = &hsi2c_0;
- hsi2c1 = &hsi2c_1;
- hsi2c2 = &hsi2c_2;
- hsi2c3 = &hsi2c_3;
- hsi2c4 = &hsi2c_4;
- hsi2c5 = &hsi2c_5;
- hsi2c6 = &hsi2c_6;
- hsi2c7 = &hsi2c_7;
- hsi2c8 = &hsi2c_8;
- hsi2c9 = &hsi2c_9;
- hsi2c10 = &hsi2c_10;
- hsi2c11 = &hsi2c_11;
- hsi2c12 = &hsi2c_12;
- hsi2c13 = &hsi2c_13;
- hsi2c14 = &hsi2c_14;
- hsi2c15 = &hsi2c_15;
- hsi2c16 = &hsi2c_16;
- hsi2c17 = &hsi2c_17;
- hsi2c18 = &hsi2c_18;
- hsi2c19 = &hsi2c_19;
- hsi2c20 = &hsi2c_20;
- hsi2c21 = &hsi2c_21;
- hsi2c22 = &hsi2c_22;
- hsi2c23 = &hsi2c_23;
- hsi2c24 = &hsi2c_24;
- hsi2c25 = &hsi2c_25;
- hsi2c26 = &hsi2c_26;
- hsi2c27 = &hsi2c_27;
- hsi2c28 = &hsi2c_28;
- hsi2c29 = &hsi2c_29;
- hsi2c30 = &hsi2c_30;
- hsi2c31 = &hsi2c_31;
- hsi2c32 = &hsi2c_32;
- hsi2c33 = &hsi2c_33;
- hsi2c34 = &hsi2c_34;
- hsi2c35 = &hsi2c_35;
- hsi2c36 = &hsi2c_36;
- hsi2c37 = &hsi2c_37;
- hsi2c38 = &hsi2c_38;
- hsi2c39 = &hsi2c_39;
- hsi2c40 = &hsi2c_40;
- hsi2c41 = &hsi2c_41;
- hsi2c42 = &hsi2c_42;
- hsi2c43 = &hsi2c_43;
- hsi2c44 = &hsi2c_44;
- hsi2c45 = &hsi2c_45;
- spi0 = &spi_0;
- spi1 = &spi_1;
- spi2 = &spi_2;
- spi3 = &spi_3;
- spi4 = &spi_4;
- spi5 = &spi_5;
- spi6 = &spi_6;
- spi7 = &spi_7;
- spi8 = &spi_8;
- spi9 = &spi_9;
- spi10 = &spi_10;
- spi11 = &spi_11;
- spi12 = &spi_12;
- spi13 = &spi_13;
- spi14 = &spi_14;
- spi15 = &spi_15;
- spi16 = &spi_16;
- spi17 = &spi_17;
- spi18 = &spi_18;
- spi19 = &spi_19;
- spi20 = &spi_20;
- spi21 = &spi_21;
- ecduart = &serial_0;
- uart0 = &serial_0;
- dpp0 = &idma_g0;
- dpp1 = &idma_g1;
- dpp2 = &idma_vg0;
- dpp3 = &idma_vg1;
- dpp4 = &idma_vgf0;
- dpp5 = &idma_vgf1;
- dsim0 = &dsim_0;
- displayport = &displayport;
- decon0 = &decon_f;
- decon2 = &decon_t;
- uart1 = &serial_1;
- uart2 = &serial_2;
- uart3 = &serial_3;
- uart4 = &serial_4;
- uart5 = &serial_5;
- uart6 = &serial_6;
- uart7 = &serial_7;
- uart8 = &serial_8;
- uart9 = &serial_9;
- uart10 = &serial_10;
- uart11 = &serial_11;
- uart12 = &serial_12;
- uart13 = &serial_13;
- uart14 = &serial_14;
- uart15 = &serial_15;
- uart16 = &serial_16;
- uart17 = &serial_17;
- uart18 = &serial_18;
- uart19 = &serial_19;
- uart20 = &serial_20;
- uart21 = &serial_21;
- uart22 = &serial_22;
- mfc0 = &mfc_0;
- scaler0 = &scaler_0;
- };
- chipid@10000000 {
- compatible = "samsung,exynos9810-chipid";
- reg = <0x0 0x10000000 0x100>;
- };
- arm-pmu {
- compatible = "arm,armv8-pmuv3";
- interrupts = <0 INTREQ__CPUCL1_PMUIRQ_0 4>,
- <0 INTREQ__CPUCL1_PMUIRQ_1 4>,
- <0 INTREQ__CPUCL1_PMUIRQ_2 4>,
- <0 INTREQ__CPUCL1_PMUIRQ_3 4>,
- <0 INTREQ__CPUCL0_PMUIRQ_0 4>,
- <0 INTREQ__CPUCL0_PMUIRQ_1 4>,
- <0 INTREQ__CPUCL0_PMUIRQ_2 4>,
- <0 INTREQ__CPUCL0_PMUIRQ_3 4>;
- };
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
- ehmp {
- /* lb trigger */
- #define DISABLED 0xFFFFFFFF
- top-overutil = <DISABLED
- DISABLED
- DISABLED
- DISABLED
- DISABLED
- DISABLED
- DISABLED
- DISABLED>;
- bot-overutil = <35
- 35
- 35
- 35
- DISABLED
- DISABLED
- DISABLED
- DISABLED>;
- /* ontime migration */
- up-threshold = <79>;
- down-threshold = <128>;
- min-residency-us = <8192>;
- };
- cpu0: cpu@0000 {
- device_type = "cpu";
- compatible = "arm,ananke", "arm,armv8";
- reg = <0x0 0x0000>;
- enable-method = "psci";
- cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
- };
- cpu1: cpu@0001 {
- device_type = "cpu";
- compatible = "arm,ananke", "arm,armv8";
- reg = <0x0 0x0001>;
- enable-method = "psci";
- cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
- };
- cpu2: cpu@0002 {
- device_type = "cpu";
- compatible = "arm,ananke", "arm,armv8";
- reg = <0x0 0x0002>;
- enable-method = "psci";
- cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
- };
- cpu3: cpu@0003 {
- device_type = "cpu";
- compatible = "arm,ananke", "arm,armv8";
- reg = <0x0 0x0003>;
- enable-method = "psci";
- cpu-idle-states = <&BOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
- };
- cpu4: cpu@0100 {
- device_type = "cpu";
- compatible = "arm,meerkat", "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
- };
- cpu5: cpu@0101 {
- device_type = "cpu";
- compatible = "arm,meerkat", "arm,armv8";
- reg = <0x0 0x101>;
- enable-method = "psci";
- cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
- };
- cpu6: cpu@0102 {
- device_type = "cpu";
- compatible = "arm,meerkat", "arm,armv8";
- reg = <0x0 0x102>;
- enable-method = "psci";
- cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
- };
- cpu7: cpu@0103 {
- device_type = "cpu";
- compatible = "arm,meerkat", "arm,armv8";
- reg = <0x0 0x103>;
- enable-method = "psci";
- cpu-idle-states = <&NONBOOTCL_CPU_SLEEP>;
- sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
- };
- idle-states {
- entry-method = "arm,psci";
- BOOTCL_CPU_SLEEP: bootcl-cpu-sleep {
- idle-state-name = "c2";
- compatible = "exynos,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <70>;
- exit-latency-us = <160>;
- min-residency-us = <2000>;
- status = "okay";
- };
- NONBOOTCL_CPU_SLEEP: nobootcl-cpu-sleep {
- idle-state-name = "c2";
- compatible = "exynos,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- entry-latency-us = <235>;
- exit-latency-us = <220>;
- min-residency-us = <3500>;
- status = "okay";
- };
- };
- energy-costs {
- CPU_COST_0: core-core0{
- busy-cost-data = <
- 212 215
- 230 225
- 263 250
- 304 289
- 341 341
- 378 431
- 415 517
- 447 605
- 521 866
- 563 1037
- 600 1242
- 637 1452
- 683 1798
- 717 2025
- 747 2680
- 821 3180
- 886 3970
- 941 4861
- 959 5623
- 1015 6412
- 1024 7533
- >;
- idle-cost-data = <
- 10
- 0
- 0
- >;
- };
- CPU_COST_1: core-core1{
- busy-cost-data = <
- 46 22
- 61 31
- 72 39
- 84 51
- 96 63
- 107 77
- 127 105
- 148 149
- 171 231
- 182 240
- 198 250
- >;
- idle-cost-data = <
- 1
- 0
- 0
- >;
- };
- CLUSTER_COST_0: cluster-core0{
- busy-cost-data = <
- 212 61
- 230 64
- 263 70
- 304 76
- 341 93
- 378 123
- 415 151
- 447 181
- 521 268
- 563 325
- 600 393
- 637 463
- 683 579
- 717 654
- 747 873
- 821 1039
- 886 1302
- 941 1600
- 959 1854
- 1015 2117
- 1024 2490
- >;
- idle-cost-data = <
- 268
- 268
- 0
- >;
- };
- CLUSTER_COST_1: cluster-core1{
- busy-cost-data = <
- 46 1
- 61 3
- 72 4
- 84 7
- 96 9
- 107 12
- 127 18
- 148 26
- 171 43
- 182 53
- 198 58
- >;
- idle-cost-data = <
- 5
- 5
- 0
- >;
- };
- };
- };
- exynos-pm {
- compatible = "samsung,exynos-pm";
- reg = <0x0 0x14050000 0x1000>,
- <0x0 0x10101200 0x100>;
- reg-names = "gpio_alive_base",
- "gicd_ispendrn_base";
- num-eint = <34>;
- num-gic = <16>;
- suspend_mode_idx = <8>; /* SYS_SLEEP */
- suspend_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
- cp_call_mode_idx = <10>; /* SYS_SLEEP_AUD_ON */
- cp_call_psci_idx = <133>; /* PSCI_SYSTEM_SLEEP */
- usbl2_suspend_available = <1>; /* SYS_SLEEP_AUD_ON */
- usbl2_suspend_mode_idx = <12>; /* SYS_SLEEP_AUD_ON */
- extra_wakeup_stat = <0x640>;
- wakeup_stat_irqno = <0>, /* [0] EINT */
- <INTREQ__RTC_ALARM_INT>, <INTREQ__RTC_TIC_INT_0>,
- <INTREQ__TOP_RTC_ALARM_INT>, <INTREQ__TOP_RTC_TIC_INT_0>,
- <INTREQ__PCIE_WIFI0>, <INTREQ__PCIE_WIFI1>,
- <0>, <0>, /* [7:8] EXT_PCIE_GEN2,3 */
- <0>, <0>, /* [9:10] RSVD */
- <INTREQ__MMC_CARD>,
- <0>, <0>, /* [12:13] RSVD */
- <INTREQ__MCT_G0>,
- <0>, /* [15] CEC */
- <INTREQ__USB3_REMOTE_WAKEUP>, <INTREQ__USB2_REMOTE_WAKEUP>,
- <0>, /* [18] RSVD */
- <INTREQ__MAILBOX_APM2AP>, <INTREQ__CP2AP_WAKEUP>,
- <INTREQ__GNSS2AP_WAKEUP>, <INTREQ__GNSS2AP_WDOG_RESET>,
- <INTREQ__ALIVE_GNSS_ACTIVE>, <INTREQ__MAILBOX_CP2AP>,
- <INTREQ__ALIVE_CP_ACTIVE>, <INTREQ__MAILBOX_GNSS2AP>,
- <0>, <0>, /* [27] CORTEXM23_APM [28] RSVD */
- <INTREQ__S_MAILBOX_CP2AP>,
- <0>, <0>; /* [30] RSVD [31] WAKEUP */
- extra_wakeup_stat_irqno {
- wakeup_stat4 {
- irqno = <INTREQ__MAILBOX_VTS2CHUB>, <INTREQ__WDT_VTS>,
- <INTREQ__SPEEDY_APM>, <INTREQ__UART_BT>,
- <INTREQ__UART_BT>, <INTREQ__WDT_CHUB>;
- /* [6:31] RSVD */
- };
- };
- };
- exynos-powermode {
- cpd_residency = <10000>;
- sicd_residency = <10000>;
- cpd_enabled = <1>;
- sicd_enabled = <1>;
- idle-ip = "10510000.pwm", /* [ 0] pwm */
- "14230000.adc", /* [ 1] adc */
- "10860000.hsi2c", /* [ 2] hsi2c_0 */
- "10870000.hsi2c", /* [ 3] hsi2c_1 */
- "10880000.hsi2c", /* [ 4] hsi2c_2 */
- "10890000.hsi2c", /* [ 5] hsi2c_3 */
- "10450000.hsi2c", /* [ 6] hsi2c_4 */
- "10460000.hsi2c", /* [ 7] hsi2c_5 */
- "10470000.hsi2c", /* [ 8] hsi2c_6 */
- "10480000.hsi2c", /* [ 9] hsi2c_7 */
- "10490000.hsi2c", /* [10] hsi2c_8 */
- "104a0000.hsi2c", /* [11] hsi2c_9 */
- "104b0000.hsi2c", /* [12] hsi2c_10 */
- "104c0000.hsi2c", /* [13] hsi2c_11 */
- "104d0000.hsi2c", /* [14] hsi2c_12 */
- "104e0000.hsi2c", /* [15] hsi2c_13 */
- "104f0000.hsi2c", /* [16] hsi2c_14 */
- "10500000.hsi2c", /* [17] hsi2c_15 */
- "108a0000.hsi2c", /* [18] hsi2c_16 */
- "108b0000.hsi2c", /* [19] hsi2c_17 */
- "108c0000.hsi2c", /* [20] hsi2c_18 */
- "108d0000.hsi2c", /* [21] hsi2c_19 */
- "108e0000.hsi2c", /* [22] hsi2c_20 */
- "108f0000.hsi2c", /* [23] hsi2c_21 */
- "10900000.hsi2c", /* [24] hsi2c_22 */
- "10910000.hsi2c", /* [25] hsi2c_23 */
- "10920000.hsi2c", /* [26] hsi2c_24 */
- "10930000.hsi2c", /* [27] hsi2c_25 */
- "10940000.hsi2c", /* [28] hsi2c_26 */
- "10950000.hsi2c", /* [29] hsi2c_27 */
- "10520000.hsi2c", /* [30] hsi2c_28 */
- "10530000.hsi2c", /* [31] hsi2c_29 */
- "10540000.hsi2c", /* [32] hsi2c_30 */
- "10550000.hsi2c", /* [33] hsi2c_31 */
- "10560000.hsi2c", /* [34] hsi2c_32 */
- "10570000.hsi2c", /* [35] hsi2c_33 */
- "14300000.hsi2c", /* [36] hsi2c_34 */
- "14310000.hsi2c", /* [37] hsi2c_35 */
- "14320000.hsi2c", /* [38] hsi2c_36 */
- "14330000.hsi2c", /* [39] hsi2c_37 */
- "14340000.hsi2c", /* [40] hsi2c_38 */
- "14350000.hsi2c", /* [41] hsi2c_39 */
- "14360000.hsi2c", /* [42] hsi2c_40 */
- "14370000.hsi2c", /* [43] hsi2c_41 */
- "10850000.spi", /* [44] spi_0 */
- "10450000.spi", /* [45] spi_1 */
- "10470000.spi", /* [46] spi_2 */
- "10490000.spi", /* [47] spi_3 */
- "104b0000.spi", /* [48] spi_4 */
- "104d0000.spi", /* [49] spi_5 */
- "104f0000.spi", /* [50] spi_6 */
- "108a0000.spi", /* [51] spi_7 */
- "108c0000.spi", /* [52] spi_8 */
- "108e0000.spi", /* [53] spi_9 */
- "10900000.spi", /* [54] spi_10 */
- "10920000.spi", /* [55] spi_11 */
- "10940000.spi", /* [56] spi_12 */
- "10520000.spi", /* [57] spi_13 */
- "10540000.spi", /* [58] spi_14 */
- "10560000.spi", /* [59] spi_15 */
- "14300000.spi", /* [60] spi_16 */
- "14320000.spi", /* [61] spi_17 */
- "14340000.spi", /* [62] spi_18 */
- "14360000.spi", /* [63] spi_19 */
- "11120000.ufs", /* [64] ufs */
- "11500000.dwmmc2", /* [65] dwmmc2 */
- "10c00000.usb", /* [66] usb */
- "141a0000.mailbox", /* [67] mailbox */
- "116a0000.pcie0", /* [68] pcie0 */
- "116b0000.pcie1", /* [69] pcie1 */
- "pd-aud", /* [70] pd-aud */
- "pd-dcf", /* [71] pd-dcf */
- "pd-dcpost", /* [72] pd-dcpost*/
- "pd-dcrd", /* [73] pd-dcrd */
- "pd-dpu", /* [74] pd-dpu */
- "pd-dspm", /* [75] pd-dspm */
- "pd-dsps", /* [76] pd-dsps */
- "pd-g2d", /* [77] pd-g2d */
- "pd-embedded_g3d", /* [78] pd-embedded_g3d */
- "pd-isppre", /* [79] pd-isppre */
- "pd-isphq", /* [80] pd-isphq */
- "pd-isplp", /* [81] pd-isplp */
- "pd-iva", /* [82] pd-iva */
- "pd-mfc", /* [83] pd-mfc */
- "pd-vts", /* [84] pd-vts */
- "11090000.displayport", /* [85] displayport */
- "bluetooth"; /* [86] bluetooth */
- fix-idle-ip = "acpm_dvfs";
- fix-idle-ip-index = <96>;
- idle_ip_mask {
- sicd: SYS_SICD {
- mode-index = <0>;
- ref-idle-ip = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>,
- <10>, <11>, <12>, <13>, <14>, <15>, <16>, <17>, <18>, <19>,
- <20>, <21>, <22>, <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>, <31>, <32>, <33>, <34>, <35>, <36>, <37>, <38>, <39>,
- <40>, <41>, <42>, <43>, <44>, <45>, <46>, <47>, <48>, <49>,
- <50>, <51>, <52>, <53>, <54>, <55>, <56>, <57>, <58>, <59>,
- <60>, <61>, <62>, <63>, <64>, <65>, <66>, <67>, <68>, <69>,
- <74>, <75>, <76>, <77>, <78>, <79>,
- <80>, <81>, <82>, <83>, <85>, <86>, <96>;
- };
- };
- wakeup-masks {
- /*
- * wakeup_mask configuration
- * SICD SICD_CPD AFTR STOP
- * LPD LPA ALPA DSTOP
- * SLEEP SLEEP_VTS_ON SLEEP_AUD_ON FAPO USB_L2
- */
- wakeup-mask {
- mask = <0x400001E0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0xD00F7E7E>, <0x500F7E7E>, <0x500F7E7E>, <0x0>, <0xD00D7E7E>;
- reg-offset = <0x610>;
- };
- wakeup-mask2 {
- mask = <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>, <0xFFFF00FF>;
- reg-offset = <0x614>;
- };
- wakeup-mask3 {
- mask = <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0xFFFF00FF>, <0xFFFF00FF>, <0xFFFF00FF>, <0x0>, <0xFFFF00FF>;
- reg-offset = <0x618>;
- };
- wakeup-mask4 {
- mask = <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>,
- <0x0>, <0x0>, <0x0>, <0x0>, <0x0>;
- reg-offset = <0x644>;
- };
- };
- };
- psci {
- compatible = "arm,psci";
- method = "smc";
- cpu_suspend = <0xC4000001>;
- cpu_off = <0x84000002>;
- cpu_on = <0xC4000003>;
- };
- exynos-ocp {
- compatible = "samsung,exynos-ocp";
- interrupts = <0 INTREQ__CPUCL1_GCUIRQ 0>;
- sibling-cpus = "4-7";
- down-step = <1>;
- max-freq-wo-ocp = <1794000>;
- release-mode = <1>; /* 0 : current meter, 1 : cpu utilization */
- release-threshold = <50>; /* @current meter : current(A), @cpu load : capacity ratio(%) */
- release-duration = <15>; /* msec */
- };
- exynos-pmu {
- compatible = "samsung,exynos-pmu";
- samsung,syscon-phandle = <&pmu_system_controller>;
- };
- pmu_system_controller: system-controller@14060000 {
- compatible = "samsung,exynos9810-pmu", "syscon";
- reg = <0x0 0x14060000 0x10000>;
- };
- gic:interrupt-controller@10100000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0x0 0x10101000 0x1000>,
- <0x0 0x10102000 0x1000>,
- <0x0 0x10104000 0x2000>,
- <0x0 0x10106000 0x2000>;
- interrupts = <1 9 0xf04>;
- };
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10
- (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
- clock-frequency = <26000000>;
- use-clocksource-only;
- use-physical-timer;
- };
- clock: clock-controller@0x15a80000 {
- compatible = "samsung,exynos9810-clock";
- reg = <0x0 0x15a80000 0x8000>;
- #clock-cells = <1>;
- };
- mct@10040000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x0 0x10040000 0x800>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>,
- <4>, <5>, <6>, <7>,
- <8>, <9>, <10>, <11>;
- clocks = <&clock OSCCLK>, <&clock GATE_MCT>;
- clock-names = "fin_pll", "mct";
- use-clockevent-only;
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0 &gic 0 INTREQ__MCT_G0 0>,
- <1 &gic 0 INTREQ__MCT_G1 0>,
- <2 &gic 0 INTREQ__MCT_G2 0>,
- <3 &gic 0 INTREQ__MCT_G3 0>,
- <4 &gic 0 INTREQ__MCT_L0 0>,
- <5 &gic 0 INTREQ__MCT_L1 0>,
- <6 &gic 0 INTREQ__MCT_L2 0>,
- <7 &gic 0 INTREQ__MCT_L3 0>,
- <8 &gic 0 INTREQ__MCT_L4 0>,
- <9 &gic 0 INTREQ__MCT_L5 0>,
- <10 &gic 0 INTREQ__MCT_L6 0>,
- <11 &gic 0 INTREQ__MCT_L7 0>;
- };
- };
- /* DMA */
- amba {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "arm,amba-bus";
- interrupt-parent = <&gic>;
- ranges;
- pdma0: pdma0@1A2E0000 {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x0 0x1A2E0000 0x1000>;
- interrupts = <0 INTREQ__PDMA0 0>;
- clocks = <&clock GATE_PDMA0>;
- clock-names = "apb_pclk";
- #dma-cells = <1>;
- #dma-channels = <8>;
- #dma-requests = <32>;
- #dma-multi-irq = <1>;
- dma-arwrapper = <0x1A2E4400>,
- <0x1A2E4420>,
- <0x1A2E4440>,
- <0x1A2E4460>,
- <0x1A2E4480>,
- <0x1A2E44A0>,
- <0x1A2E44C0>,
- <0x1A2E44E0>;
- dma-awwrapper = <0x1A2E4404>,
- <0x1A2E4424>,
- <0x1A2E4444>,
- <0x1A2E4464>,
- <0x1A2E4484>,
- <0x1A2E44A4>,
- <0x1A2E44C4>,
- <0x1A2E44E4>;
- dma-instwrapper = <0x1A2E4500>;
- dma-mask-bit = <36>;
- coherent-mask-bit = <36>;
- };
- };
- mali: mali@17500000 {
- compatible = "arm,mali";
- reg = <0x0 0x17500000 0x5000>;
- interrupts = <0 INTREQ__G3D_IRQJOB 0>,
- <0 INTREQ__G3D_IRQMMU 0>,
- <0 INTREQ__G3D_IRQGPU 0>;
- interrupt-names = "JOB", "MMU", "GPU";
- g3d_cmu_cal_id = <ACPM_DVFS_G3D>;
- samsung,power-domain = <&pd_embedded_g3d>;
- #cooling-cells = <2>; /* min followed by max */
- };
- ITMON@0 {
- compatible = "samsung,exynos-itmon";
- interrupts = <0 INTREQ__TREX_DEBUG 0>, /* DATA_BUS_C */
- <0 INTREQ__TREX_D_CORE_debugInterrupt 0>, /* DATA_CORE */
- <0 INTREQ__TREX_P0_CORE_debugInterrupt 0>, /* PERI_CORE_0 */
- <0 INTREQ__TREX_P_DEBUG 0>, /* PERI_BUS_C */
- <0 INTREQ__TREX_P1_CORE_debugInterrupt 0>, /* PERI_CORE_1 */
- <0 INTREQ__TREX_P_BUS1_DEBUG 0>; /* PERI_BUS_1 */
- };
- /* ALIVE */
- pinctrl_0: pinctrl@14050000 {
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x14050000 0x1000>;
- interrupts = <0 INTREQ__EINT0 0>, <0 INTREQ__EINT1 0>, <0 INTREQ__EINT2 0>,
- <0 INTREQ__EINT3 0>, <0 INTREQ__EINT4 0>, <0 INTREQ__EINT5 0>,
- <0 INTREQ__EINT6 0>, <0 INTREQ__EINT7 0>, <0 INTREQ__EINT8 0>,
- <0 INTREQ__EINT9 0>, <0 INTREQ__EINT10 0>, <0 INTREQ__EINT11 0>,
- <0 INTREQ__EINT12 0>, <0 INTREQ__EINT13 0>, <0 INTREQ__EINT14 0>,
- <0 INTREQ__EINT15 0>, <0 INTREQ__EINT16 0>, <0 INTREQ__EINT17 0>,
- <0 INTREQ__EINT18 0>, <0 INTREQ__EINT19 0>, <0 INTREQ__EINT20 0>,
- <0 INTREQ__EINT21 0>, <0 INTREQ__EINT22 0>, <0 INTREQ__EINT23 0>,
- <0 INTREQ__EINT24 0>, <0 INTREQ__EINT25 0>, <0 INTREQ__EINT26 0>,
- <0 INTREQ__EINT27 0>, <0 INTREQ__EINT28 0>, <0 INTREQ__EINT29 0>,
- <0 INTREQ__EINT30 0>, <0 INTREQ__EINT31 0>, <0 INTREQ__EINT32 0>,
- <0 INTREQ__EINT33 0>;
- wakeup-interrupt-controller {
- compatible = "samsung,exynos7-wakeup-eint";
- };
- };
- /* AUD */
- pinctrl_1: pinctrl@17C60000{
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x17C60000 0x1000>;
- };
- /* CHUB */
- pinctrl_2: pinctrl@13A80000{
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x13A80000 0x1000>;
- interrupts = <0 INTREQ__GPIO_CHUB 0>;
- };
- /* CMGP */
- pinctrl_3: pinctrl@14220000{
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x14220000 0x1000>;
- interrupts = <0 INTREQ__EXT_INTM0_0 0>, <0 INTREQ__EXT_INTM0_1 0>,
- <0 INTREQ__EXT_INTM0_2 0>, <0 INTREQ__EXT_INTM0_3 0>,
- <0 INTREQ__EXT_INTM0_4 0>, <0 INTREQ__EXT_INTM0_5 0>,
- <0 INTREQ__EXT_INTM0_6 0>, <0 INTREQ__EXT_INTM0_7 0>,
- <0 INTREQ__EXT_INTM1_0 0>, <0 INTREQ__EXT_INTM1_1 0>,
- <0 INTREQ__EXT_INTM1_2 0>, <0 INTREQ__EXT_INTM1_3 0>,
- <0 INTREQ__EXT_INTM1_4 0>, <0 INTREQ__EXT_INTM1_5 0>,
- <0 INTREQ__EXT_INTM1_6 0>, <0 INTREQ__EXT_INTM1_7 0>,
- <0 INTREQ__EXT_INTM4_0 0>, <0 INTREQ__EXT_INTM4_1 0>,
- <0 INTREQ__EXT_INTM4_2 0>, <0 INTREQ__EXT_INTM4_3 0>;
- wakeup-interrupt-controller {
- compatible = "samsung,exynos7-wakeup-eint";
- };
- };
- /* FSYS0 */
- pinctrl_4: pinctrl@11050000 {
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x11050000 0x1000>;
- interrupts = <0 INTREQ__GPIO_FSYS0 0>;
- };
- /* FSYS1 */
- pinctrl_5: pinctrl@11430000 {
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x11430000 0x1000>;
- interrupts = <0 INTREQ__GPIO_FSYS1 0>;
- };
- /* PERIC0 */
- pinctrl_6: pinctrl@10430000 {
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x10430000 0x1000>;
- interrupts = <0 INTREQ__GPIO_PERIC0 0>;
- };
- /* PERIC1 */
- pinctrl_7: pinctrl@10830000 {
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x10830000 0x1000>;
- interrupts = <0 INTREQ__GPIO_PERIC1 0>;
- };
- /* VTS */
- pinctrl_8: pinctrl@13880000 {
- compatible = "samsung,exynos9810-pinctrl";
- reg = <0x0 0x13880000 0x1000>;
- };
- idma_g0: dpp@0x16021000 {
- compatible = "samsung,exynos9-dpp";
- #pb-id-cells = <3>;
- /* DPP, DPU_DMA, DPU_DMA_COMMON */
- reg = <0x0 0x16021000 0x1000>, <0x0 0x16071000 0x1000>, <0x0 0x16070000 0x110>;
- /* DPU_DMA IRQ, DPP IRQ */
- interrupts = <0 INTREQ__DPU_DMA_G0 0>, <0 INTREQ__DPU_DPP_G0 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- idma_g1: dpp@0x16022000 {
- compatible = "samsung,exynos9-dpp";
- #pb-id-cells = <3>;
- reg = <0x0 0x16022000 0x1000>, <0x0 0x16072000 0x1000>;
- interrupts = <0 INTREQ__DPU_DMA_G1 0>, <0 INTREQ__DPU_DPP_G1 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- idma_vg0: dpp@0x16023000 {
- compatible = "samsung,exynos9-dpp";
- #pb-id-cells = <3>;
- reg = <0x0 0x16023000 0x1000>, <0x0 0x16073000 0x1000>;
- interrupts = <0 INTREQ__DPU_DMA_VG0 0>, <0 INTREQ__DPU_DPP_VG0 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- idma_vg1: dpp@0x16024000 {
- compatible = "samsung,exynos9-dpp";
- #pb-id-cells = <3>;
- reg = <0x0 0x16024000 0x1000>, <0x0 0x16074000 0x1000>;
- interrupts = <0 INTREQ__DPU_DMA_VG1 0>, <0 INTREQ__DPU_DPP_VG1 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- idma_vgf0: dpp@0x16025000 {
- compatible = "samsung,exynos9-dpp";
- #pb-id-cells = <3>;
- reg = <0x0 0x16025000 0x1000>, <0x0 0x16075000 0x1000>;
- interrupts = <0 INTREQ__DPU_DMA_VGF 0>, <0 INTREQ__DPU_DPP_VGF0 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- idma_vgf1: dpp@0x16026000 {
- compatible = "samsung,exynos9-dpp";
- #pb-id-cells = <3>;
- reg = <0x0 0x16026000 0x1000>, <0x0 0x16076000 0x1000>;
- interrupts = <0 INTREQ__DPU_DMA_VGRF 0>, <0 INTREQ__DPU_DPP_VGF1 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- disp_ss: disp_ss@0x16010000 {
- compatible = "samsung,exynos9-disp_ss";
- reg = <0x0 0x16011000 0x10>;
- };
- mipi_phy_dsim: phy_m4s4top_dsi0@0x16160000 {
- compatible = "samsung,mipi-phy-m4s4-top";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x070C>;
- /* PHY reset be controlled from DSIM */
- /* reg = <0x0 0x12821008 0x4>; */
- /* reset = <0 1>; */
- /* init = <4 5>; */ /* PHY reset control path bit of SYSREG */
- owner = <0>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
- dsim_0: dsim@0x16080000 {
- compatible = "samsung,exynos9-dsim";
- reg = <0x0 0x16080000 0x100>, <0x0 0x16160000 0x4000>;
- interrupts = <0 INTREQ__DPU_DSIM0 0>;
- iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>;
- /* clock */
- clock-names = "aclk";
- clocks = <&clock GATE_DPU>;
- phys = <&mipi_phy_dsim 0>;
- phy-names = "dsim_dphy";
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- displayport_phy: displayport_phy@110A0000 {
- compatible = "samsung,displayport-phy";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x0704>;
- #phy-cells = <1>;
- };
- displayport: displayport@0x11090000 {
- compatible = "samsung,exynos-displayport";
- reg = <0x0 0x11090000 0xFFFF>;
- interrupts = <0 INTREQ__DP_LINK 0>;
- iommus = <&sysmmu_dpu0>, <&sysmmu_dpu1>, <&sysmmu_dpu2>;
- /* clock */
- clock-names = "aclk";
- clocks = <&clock GATE_DPU>;
- phys = <&displayport_phy 0>;
- phy-names = "displayport_phy";
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- };
- displayport_adma: dp_dma {
- compatible = "samsung,displayport-adma";
- /* dma-mode; */
- dmas = <&pdma0 28>;
- dma-names = "tx";
- };
- decon_f: decon_f@0x16030000 {
- compatible = "samsung,exynos9-decon"; /* exynos9810 */
- #pb-id-cells = <4>;
- reg = <0x0 0x16030000 0x10000>;
- /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA, GPIO_PERIC1(EXT_INT_TE: GPD0[0]) */
- interrupts = <0 INTREQ__DPU_DECON0_FRAME_START 0>,
- <0 INTREQ__DPU_DECON0_FRAME_DONE 0>,
- <0 INTREQ__DPU_DECON0_EXTRA 0>,
- <0 INTREQ__GPIO_PERIC1 0>;
- /* pinctrl */
- pinctrl-names = "hw_te_on", "hw_te_off";
- pinctrl-0 = <&decon_f_te_on>;
- pinctrl-1 = <&decon_f_te_off>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- max_win = <6>;
- default_win = <5>;
- default_idma = <0>;
- psr_mode = <2>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
- trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
- dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
- /* 0: DSI, 1: eDP, 2:HDMI, 3: WB */
- out_type = <0>;
- /* 0: DSI0, 1: DSI1, 2: DSI2 */
- out_idx = <0>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- /* EINT for TE */
- gpios = <&gpd0 0 0xf>;
- /* sw te pending register */
- te_eint {
- /* NWEINT_GPD0_PEND */
- reg = <0x0 0x10830a14 0x4>;
- };
- cam-stat {
- /* ISPPRE_STATUS(0x1406404C), ISPHQ_STATUS(0x14064054), ISPLP_STATUS(0x1406405C) */
- reg = <0x0 0x1406404C 0x4>;
- };
- };
- decon_t: decon_t@0x16050000 {
- compatible = "samsung,exynos9-decon"; /* exynos9810 */
- #pb-id-cells = <4>;
- reg = <0x0 0x16050000 0x10000>;
- /* interrupt num : FRAME_START, FRMAE_DONE, EXTRA */
- interrupts = <0 INTREQ__DPU_DECON2_FRAME_START 0>,
- <0 INTREQ__DPU_DECON2_FRAME_DONE 0>,
- <0 INTREQ__DPU_DECON2_EXTRA 0>;
- /* power domain */
- samsung,power-domain = <&pd_dpu>;
- max_win = <6>;
- default_win = <4>;
- default_idma = <1>;
- psr_mode = <0>; /* 0: video mode, 1: DP command mode, 2: MIPI command mode */
- trig_mode = <0>; /* 0: hw trigger, 1: sw trigger */
- dsi_mode = <0>; /* 0: single dsi, 1: dual dsi */
- /* 0: DSI, 1: eDP, 2:DP */
- out_type = <2>;
- /* 0: DSI0, 1: DSI1, 2: DSI2 */
- out_idx = <0>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- };
- udc: usb@10C00000 {
- compatible = "samsung,exynos-dwusb";
- clocks = <&clock GATE_USB30DRD_USB30DRD_LINK>, <&clock USB30DRD>;
- clock-names = "aclk", "sclk";
- reg = <0x0 0x10C00000 0x10000>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- status = "disabled";
- usbdrd_dwc3: dwc3 {
- compatible = "synopsys,dwc3";
- reg = <0x0 0x10C00000 0x10000>;
- interrupts = <0 INTREQ__USB30DRD_Interrupt_00 0>;
- tx-fifo-resize = <0>;
- adj-sof-accuracy = <0>;
- is_not_vbus_pad = <1>;
- enable_sprs_transfer = <1>;
- phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
- phy-names = "usb2-phy", "usb3-phy";
- /* check susphy support */
- xhci_l2_support = <1>;
- /* support usb audio offloading: 1, if not: 0 */
- usb_audio_offloading = <1>;
- abox = <&abox>;
- /* support USB L2 sleep */
- ldos = <6>;
- ldo_number = <9 10 11 12 13 14>;
- };
- };
- usbdrd_phy0: phy@11100000 {
- compatible = "samsung,exynos-usbdrd-phy";
- reg = <0x0 0x11100000 0x200>,
- <0x0 0x110A0000 0x1000>,
- <0x0 0x110B0000 0x800>;
- interrupts = <0 INTREQ__USB2_REMOTE_WAKEUP 0>,
- <0 INTREQ__USB2_REMOTE_CONNECT 0>;
- clocks = <&clock OSCCLK>, <&clock GATE_USB30DRD_USB30DRD_LINK>;
- clock-names = "ext_xtal", "aclk";
- samsung,pmu-syscon = <&pmu_system_controller>;
- pmu_mask = <0x0>;
- pmu_offset = <0x72c>;
- pmu_offset_dp = <0x704>;
- /* USBDP combo phy version - 0x200 */
- phy_version = <0x300>;
- /* if it doesn't need phy user mux, */
- /* you should write "none" */
- /* but refclk shouldn't be omitted */
- phyclk_mux = "none";
- phy_refclk = "ext_xtal";
- /* if Main phy has the other phy, it must be set to 1. jusf for usbphy_info */
- has_other_phy = <0>;
- /* if combo phy is used, it must be set to 1. usbphy_sub_info is enabled */
- has_combo_phy = <1>;
- sub_phy_version = <0x400>;
- /* ip type */
- /* USB3DRD = 0 */
- /* USB3HOST = 1 */
- /* USB2DRD = 2 */
- /* USB2HOST = 3 */
- ip_type = <0x0>;
- /* for PHY CAL */
- /* choice only one item */
- phy_refsel_clockcore = <1>;
- phy_refsel_ext_osc = <0>;
- phy_refsel_xtal = <0>;
- phy_refsel_diff_pad = <0>;
- phy_refsel_diff_internal = <0>;
- phy_refsel_diff_single = <0>;
- /* true : 1 , false : 0 */
- use_io_for_ovc = <0>;
- common_block_disable = <1>;
- is_not_vbus_pad = <1>;
- used_phy_port = <0>;
- status = "disabled";
- #phy-cells = <1>;
- ranges;
- };
- /* USI_00 */
- usi_0: usi@10411004 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411004 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_00_I2C */
- usi_0_i2c: usi@10411008 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411008 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_01 */
- usi_1: usi@1041100c {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1041100c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_01_I2C */
- usi_1_i2c: usi@10411010 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411010 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_02 */
- usi_2: usi@10411014 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411014 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_02_I2C */
- usi_2_i2c: usi@10411018 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411018 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_03 */
- usi_3: usi@1041101C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1041101c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_03_I2C */
- usi_3_i2c: usi@10411020 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411020 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_04 */
- usi_4: usi@10411024 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411024 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_04_I2C */
- usi_4_i2c: usi@10411028 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411028 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_05 */
- usi_5: usi@1041102C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1041102c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_05_I2C */
- usi_5_i2c: usi@10411030 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411030 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_06 */
- usi_6: usi@1081101C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1081101c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_06_I2C */
- usi_6_i2c: usi@10811020 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811020 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_07 */
- usi_7: usi@10811024 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811024 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_07_I2C */
- usi_7_i2c: usi@10811028 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811028 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_08 */
- usi_8: usi@1081102C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1081102c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_08_I2C */
- usi_8_i2c: usi@10811030 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811030 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_09 */
- usi_9: usi@10811034 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811034 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_09_I2C */
- usi_9_i2c: usi@10811038 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811038 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_10 */
- usi_10: usi@1081103C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1081103c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_10_I2C */
- usi_10_i2c: usi@10811040 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811040 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_11 */
- usi_11: usi@10811044 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811044 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_11_I2C */
- usi_11_i2c: usi@10811048 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10811048 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_12 */
- usi_12: usi@10411034 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411034 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_12_I2C */
- usi_12_i2c: usi@10411038 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411038 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_13 */
- usi_13: usi@1041103C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x1041103c 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_13_I2C */
- usi_13_i2c: usi@10411040 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411040 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_14 */
- usi_14: usi@10411044 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411044 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_14_I2C */
- usi_14_i2c: usi@10411048 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x10411048 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_00_CMGP */
- usi_00_cmgp: usi@14212000 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212000 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_00_CMGP_I2C */
- usi_00_cmgp_i2c: usi@14212004 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212004 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_01_CMGP */
- usi_01_cmgp: usi@14212010 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212010 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_01_CMGP_I2C */
- usi_01_cmgp_i2c: usi@14212014 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212014 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_02_CMGP */
- usi_02_cmgp: usi@14212020 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212020 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_02_CMGP_I2C */
- usi_02_cmgp_i2c: usi@14212024 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212024 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_03_CMGP */
- usi_03_cmgp: usi@14212030 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212030 0x4>;
- /* usi_mode_v2 = "i2c" or "spi" or "uart" */
- status = "disabled";
- };
- /* USI_03_CMGP_I2C */
- usi_03_cmgp_i2c: usi@14212034 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x14212034 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_00_CHUB */
- usi_00_chub: usi@13A13000 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x13a13000 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_00_CHUB_I2C */
- usi_00_chub_i2c: usi@13A13008 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x13a13008 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_01_CHUB */
- usi_01_chub: usi@13A13004 {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x13a13004 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* USI_01_CHUB_I2C */
- usi_01_chub_i2c: usi@13A1300C {
- compatible = "samsung,exynos-usi-v2";
- reg = <0x0 0x13a1300c 0x4>;
- /* usi_mode_v2 = "i2c" */
- status = "disabled";
- };
- /* PERIC1 CAM0 */
- hsi2c_0: hsi2c@10860000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10860000 0x1000>;
- interrupts = <0 INTREQ__I2C_CAM0 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c0_bus>;
- clocks = <&clock I2C_CAM0>, <&clock GATE_I2C_CAM0>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpc0 0 0x1>;
- gpio_sda= <&gpc0 1 0x1>;
- status = "disabled";
- };
- /* PERI1 CAM1 */
- hsi2c_1: hsi2c@10870000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10870000 0x1000>;
- interrupts = <0 INTREQ__I2C_CAM1 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c1_bus>;
- clocks = <&clock I2C_CAM1>, <&clock GATE_I2C_CAM1>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpc0 2 0x1>;
- gpio_sda= <&gpc0 3 0x1>;
- status = "disabled";
- };
- /* PERI1 CAM2 */
- hsi2c_2: hsi2c@10880000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10880000 0x1000>;
- interrupts = <0 INTREQ__I2C_CAM2 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c2_bus>;
- clocks = <&clock I2C_CAM2>, <&clock GATE_I2C_CAM2>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpc0 4 0x1>;
- gpio_sda= <&gpc0 5 0x1>;
- status = "disabled";
- };
- /* PERI1 CAM3 */
- hsi2c_3: hsi2c@10890000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10890000 0x1000>;
- interrupts = <0 INTREQ__I2C_CAM3 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c3_bus>;
- clocks = <&clock I2C_CAM3>, <&clock GATE_I2C_CAM3>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpc0 6 0x1>;
- gpio_sda= <&gpc0 7 0x1>;
- status = "disabled";
- };
- /* USI00_USI */
- hsi2c_4: hsi2c@10450000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10450000 0x1000>;
- interrupts = <0 INTREQ__USI00_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c4_bus>;
- clocks = <&clock USI00>, <&clock GATE_USI00>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp0 0 0x1>;
- gpio_sda= <&gpp0 1 0x1>;
- status = "disabled";
- };
- /* USI00_USI_I2C */
- hsi2c_5: hsi2c@10460000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10460000 0x1000>;
- interrupts = <0 INTREQ__USI00_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c5_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI00_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp0 2 0x1>;
- gpio_sda= <&gpp0 3 0x1>;
- status = "disabled";
- };
- /* USI01_USI */
- hsi2c_6: hsi2c@10470000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10470000 0x1000>;
- interrupts = <0 INTREQ__USI01_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c6_bus>;
- clocks = <&clock USI01>, <&clock GATE_USI01>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp0 4 0x1>;
- gpio_sda= <&gpp0 5 0x1>;
- status = "disabled";
- };
- /* USI01_USI_I2C */
- hsi2c_7: hsi2c@10480000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10480000 0x1000>;
- interrupts = <0 INTREQ__USI01_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c7_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI01_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp0 6 0x1>;
- gpio_sda= <&gpp0 7 0x1>;
- status = "disabled";
- };
- /* USI02_USI */
- hsi2c_8: hsi2c@10490000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10490000 0x1000>;
- interrupts = <0 INTREQ__USI02_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c8_bus>;
- clocks = <&clock USI02>, <&clock GATE_USI02>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp1 0 0x1>;
- gpio_sda= <&gpp1 1 0x1>;
- status = "disabled";
- };
- /* USI02_USI_I2C */
- hsi2c_9: hsi2c@104A0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x104a0000 0x1000>;
- interrupts = <0 INTREQ__USI02_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c9_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI02_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp1 2 0x1>;
- gpio_sda= <&gpp1 3 0x1>;
- status = "disabled";
- };
- /* USI03_USI */
- hsi2c_10: hsi2c@104B0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x104B0000 0x1000>;
- interrupts = <0 INTREQ__USI03_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c10_bus>;
- clocks = <&clock USI03>, <&clock GATE_USI03>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp1 4 0x1>;
- gpio_sda= <&gpp1 5 0x1>;
- status = "disabled";
- };
- /* USI03_USI_I2C */
- hsi2c_11: hsi2c@104C0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x104C0000 0x1000>;
- interrupts = <0 INTREQ__USI03_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c11_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI03_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp1 6 0x1>;
- gpio_sda= <&gpp1 7 0x1>;
- status = "disabled";
- };
- /* USI04_USI */
- hsi2c_12: hsi2c@104D0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x104D0000 0x1000>;
- interrupts = <0 INTREQ__USI04_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c12_bus>;
- clocks = <&clock USI04>, <&clock GATE_USI04>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp2 0 0x1>;
- gpio_sda= <&gpp2 1 0x1>;
- status = "disabled";
- };
- /* USI04_USI_I2C */
- hsi2c_13: hsi2c@104E0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x104E0000 0x1000>;
- interrupts = <0 INTREQ__USI04_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c13_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI04_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp2 2 0x1>;
- gpio_sda= <&gpp2 3 0x1>;
- status = "disabled";
- };
- /* USI05_USI */
- hsi2c_14: hsi2c@104F0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x104F0000 0x1000>;
- interrupts = <0 INTREQ__USI05_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c14_bus>;
- clocks = <&clock USI05>, <&clock GATE_USI05>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp2 4 0x1>;
- gpio_sda= <&gpp2 5 0x1>;
- status = "disabled";
- };
- /* USI05_USI_I2C */
- hsi2c_15: hsi2c@10500000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10500000 0x1000>;
- interrupts = <0 INTREQ__USI05_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c15_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI05_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp2 6 0x1>;
- gpio_sda= <&gpp2 7 0x1>;
- status = "disabled";
- };
- /* USI06_USI */
- hsi2c_16: hsi2c@108A0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x108A0000 0x1000>;
- interrupts = <0 INTREQ__USI06_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c16_bus>;
- clocks = <&clock USI06>, <&clock GATE_USI06>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp4 0 0x1>;
- gpio_sda= <&gpp4 1 0x1>;
- status = "disabled";
- };
- /* USI06_USI_I2C */
- hsi2c_17: hsi2c@108B0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x108B0000 0x1000>;
- interrupts = <0 INTREQ__USI06_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c17_bus>;
- clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI06_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp4 2 0x1>;
- gpio_sda= <&gpp4 3 0x1>;
- status = "disabled";
- };
- /* USI07_USI */
- hsi2c_18: hsi2c@108C0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x108C0000 0x1000>;
- interrupts = <0 INTREQ__USI07_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c18_bus>;
- clocks = <&clock USI07>, <&clock GATE_USI07>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp4 4 0x1>;
- gpio_sda= <&gpp4 5 0x1>;
- status = "disabled";
- };
- /* USI07_USI_I2C */
- hsi2c_19: hsi2c@108D0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x108D0000 0x1000>;
- interrupts = <0 INTREQ__USI07_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c19_bus>;
- clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI07_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp4 6 0x1>;
- gpio_sda= <&gpp4 7 0x1>;
- status = "disabled";
- };
- /* USI08_USI */
- hsi2c_20: hsi2c@108E0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x108E0000 0x1000>;
- interrupts = <0 INTREQ__USI08_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c20_bus>;
- clocks = <&clock USI08>, <&clock GATE_USI08>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp5 0 0x1>;
- gpio_sda= <&gpp5 1 0x1>;
- status = "disabled";
- };
- /* USI08_USI_I2C */
- hsi2c_21: hsi2c@108F0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x108F0000 0x1000>;
- interrupts = <0 INTREQ__USI08_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c21_bus>;
- clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI08_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp5 2 0x1>;
- gpio_sda= <&gpp5 3 0x1>;
- status = "disabled";
- };
- /* USI09_USI */
- hsi2c_22: hsi2c@10900000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10900000 0x1000>;
- interrupts = <0 INTREQ__USI09_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c22_bus>;
- clocks = <&clock USI09>, <&clock GATE_USI09>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp5 4 0x1>;
- gpio_sda= <&gpp5 5 0x1>;
- status = "disabled";
- };
- /* USI09_USI_I2C */
- hsi2c_23: hsi2c@10910000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10910000 0x1000>;
- interrupts = <0 INTREQ__USI09_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c23_bus>;
- clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI09_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp5 6 0x1>;
- gpio_sda= <&gpp5 7 0x1>;
- status = "disabled";
- };
- /* USI10_USI */
- hsi2c_24: hsi2c@10920000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10920000 0x1000>;
- interrupts = <0 INTREQ__USI10_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c24_bus>;
- clocks = <&clock USI10>, <&clock GATE_USI10>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp6 0 0x1>;
- gpio_sda= <&gpp6 1 0x1>;
- status = "disabled";
- };
- /* USI10_USI_I2C */
- hsi2c_25: hsi2c@10930000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10930000 0x1000>;
- interrupts = <0 INTREQ__USI10_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c25_bus>;
- clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI10_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpp6 2 0x1>;
- gpio_sda= <&gpp6 3 0x1>;
- status = "disabled";
- };
- /* USI11_USI */
- hsi2c_26: hsi2c@10940000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10940000 0x1000>;
- interrupts = <0 INTREQ__USI11_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c26_bus>;
- clocks = <&clock USI11>, <&clock GATE_USI11>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg3 3 0x1>;
- gpio_sda= <&gpg3 4 0x1>;
- status = "disabled";
- };
- /* USI11_USI_I2C */
- hsi2c_27: hsi2c@10950000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10950000 0x1000>;
- interrupts = <0 INTREQ__USI11_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c27_bus>;
- clocks = <&clock PERIC1_USI_I2C>, <&clock GATE_USI11_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg3 5 0x1>;
- gpio_sda= <&gpg3 6 0x1>;
- status = "disabled";
- };
- /* USI12_USI */
- hsi2c_28: hsi2c@10520000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10520000 0x1000>;
- interrupts = <0 INTREQ__USI12_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c28_bus>;
- clocks = <&clock USI12>, <&clock GATE_USI12>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg0 4 0x1>;
- gpio_sda= <&gpg0 5 0x1>;
- status = "disabled";
- };
- /* USI12_USI_I2C */
- hsi2c_29: hsi2c@10530000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10530000 0x1000>;
- interrupts = <0 INTREQ__USI12_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c29_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI12_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg0 6 0x1>;
- gpio_sda= <&gpg0 7 0x1>;
- status = "disabled";
- };
- /* USI13_USI */
- hsi2c_30: hsi2c@10540000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10540000 0x1000>;
- interrupts = <0 INTREQ__USI13_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c30_bus>;
- clocks = <&clock USI13>, <&clock GATE_USI13>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg1 0 0x1>;
- gpio_sda= <&gpg1 1 0x1>;
- status = "disabled";
- };
- /* USI13_USI_I2C */
- hsi2c_31: hsi2c@10550000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10550000 0x1000>;
- interrupts = <0 INTREQ__USI13_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c31_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI13_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg1 2 0x1>;
- gpio_sda= <&gpg1 3 0x1>;
- status = "disabled";
- };
- /* USI14_USI */
- hsi2c_32: hsi2c@10560000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10560000 0x1000>;
- interrupts = <0 INTREQ__USI14_USI 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c32_bus>;
- clocks = <&clock USI14>, <&clock GATE_USI14>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg1 4 0x1>;
- gpio_sda= <&gpg1 5 0x1>;
- status = "disabled";
- };
- /* USI14_USI_I2C */
- hsi2c_33: hsi2c@10570000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x10570000 0x1000>;
- interrupts = <0 INTREQ__USI14_I2C 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c33_bus>;
- clocks = <&clock PERIC0_USI_I2C>, <&clock GATE_USI14_I2C>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpg1 6 0x1>;
- gpio_sda= <&gpg1 7 0x1>;
- status = "disabled";
- };
- /* USI_CMGP00 */
- hsi2c_34: hsi2c@14300000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14300000 0x1000>;
- interrupts = <0 INTREQ__USI_CMGP00 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c34_bus>;
- clocks = <&clock USI_CMGP00>, <&clock GATE_USI_CMGP00>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm0 0 0x1>;
- gpio_sda= <&gpm1 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP00_I2C */
- hsi2c_35: hsi2c@14310000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14310000 0x1000>;
- interrupts = <0 INTREQ__I2C_CMGP00 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c35_bus>;
- clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP00>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm2 0 0x1>;
- gpio_sda= <&gpm3 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP01 */
- hsi2c_36: hsi2c@14320000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14320000 0x1000>;
- interrupts = <0 INTREQ__USI_CMGP01 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c36_bus>;
- clocks = <&clock USI_CMGP01>, <&clock GATE_USI_CMGP01>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm4 0 0x1>;
- gpio_sda= <&gpm5 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP01_I2C */
- hsi2c_37: hsi2c@14330000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14330000 0x1000>;
- interrupts = <0 INTREQ__I2C_CMGP01 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c37_bus>;
- clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP01>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm6 0 0x1>;
- gpio_sda= <&gpm7 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP02 */
- hsi2c_38: hsi2c@14340000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14340000 0x1000>;
- interrupts = <0 INTREQ__USI_CMGP02 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c38_bus>;
- clocks = <&clock USI_CMGP02>, <&clock GATE_USI_CMGP02>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm10 0 0x1>;
- gpio_sda= <&gpm11 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP02_I2C */
- hsi2c_39: hsi2c@14350000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14350000 0x1000>;
- interrupts = <0 INTREQ__I2C_CMGP02 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c39_bus>;
- clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP02>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm12 0 0x1>;
- gpio_sda= <&gpm13 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP03 */
- hsi2c_40: hsi2c@14360000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14360000 0x1000>;
- interrupts = <0 INTREQ__USI_CMGP03 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c40_bus>;
- clocks = <&clock USI_CMGP03>, <&clock GATE_USI_CMGP03>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm14 0 0x1>;
- gpio_sda= <&gpm15 0 0x1>;
- status = "disabled";
- };
- /* USI_CMGP03_I2C */
- hsi2c_41: hsi2c@14370000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x14370000 0x1000>;
- interrupts = <0 INTREQ__I2C_CMGP03 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c41_bus>;
- clocks = <&clock CMGP_USI_I2C>, <&clock GATE_I2C_CMGP03>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gpm16 0 0x1>;
- gpio_sda= <&gpm17 0 0x1>;
- status = "disabled";
- };
- /* USI_CHUB00 */
- hsi2c_42: hsi2c@13AC0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x13ac0000 0x1000>;
- interrupts = <0 INTREQ__USI_CHUB00 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c42_bus>;
- clocks = <&clock CHUB_USI00>, <&clock GATE_USI_CHUB00>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gph0 0 0x1>;
- gpio_sda= <&gph0 1 0x1>;
- status = "disabled";
- };
- /* USI_CHUB00_I2C */
- hsi2c_43: hsi2c@13AD0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x13ad0000 0x1000>;
- interrupts = <0 INTREQ__I2C_CHUB00 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c43_bus>;
- clocks = <&clock CHUB_USI_I2C>, <&clock GATE_I2C_CHUB00>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gph0 2 0x1>;
- gpio_sda= <&gph0 3 0x1>;
- status = "disabled";
- };
- /* USI_CHUB01 */
- hsi2c_44: hsi2c@13AE0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x13ae0000 0x1000>;
- interrupts = <0 INTREQ__USI_CHUB01 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c44_bus>;
- clocks = <&clock CHUB_USI01>, <&clock GATE_USI_CHUB01>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gph0 4 0x1>;
- gpio_sda= <&gph0 5 0x1>;
- status = "disabled";
- };
- /* USI_CHUB01_I2C */
- hsi2c_45: hsi2c@13AF0000 {
- compatible = "samsung,exynos5-hsi2c";
- samsung,check-transdone-int;
- default-clk = <200000000>;
- reg = <0x0 0x13af0000 0x1000>;
- interrupts = <0 INTREQ__I2C_CHUB01 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&hsi2c45_bus>;
- clocks = <&clock CHUB_USI_I2C>, <&clock GATE_I2C_CHUB01>;
- clock-names = "rate_hsi2c", "gate_hsi2c";
- samsung,scl-clk-stretching;
- samsung,usi-i2c-v2;
- gpio_scl= <&gph0 6 0x1>;
- gpio_sda= <&gph0 7 0x1>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_SPI_CAM0 */
- spi_0: spi@10850000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10850000 0x100>;
- samsung,spi-fifosize = <256>;
- interrupts = <0 INTREQ__SPI_CAM0 0>;
- /*
- dma-mode;
- dmas = <&pdma0 25 &pdma0 24>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_SPI_CAM0>, <&clock SPI_CAM0>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi0_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI00_SPI */
- spi_1: spi@10450000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10450000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI00_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 1 &pdma0 0>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI00>, <&clock USI00>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI01_SPI */
- spi_2: spi@10470000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10470000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI01_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 3 &pdma0 2>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI01>, <&clock USI01>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi2_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI02_SPI */
- spi_3: spi@10490000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10490000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI02_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 5 &pdma0 4>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI02>, <&clock USI02>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi3_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI03_SPI */
- spi_4: spi@104B0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x104B0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI03_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 7 &pdma0 6>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI03>, <&clock USI03>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi4_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI04_SPI */
- spi_5: spi@104D0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x104D0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI04_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 9 &pdma0 8>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI04>, <&clock USI04>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi5_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI05_SPI */
- spi_6: spi@104F0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x104F0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI05_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 11 &pdma0 10>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI05>, <&clock USI05>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi6_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_USI06_SPI */
- spi_7: spi@108A0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x108A0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI06_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 15 &pdma0 14>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI06>, <&clock USI06>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi7_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_USI07_SPI */
- spi_8: spi@108C0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x108C0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI07_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 17 &pdma0 16>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI07>, <&clock USI07>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi8_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_USI08_SPI */
- spi_9: spi@108E0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x108E0000 0x100>;
- samsung,spi-fifosize = <256>;
- interrupts = <0 INTREQ__USI08_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 19 &pdma0 18>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI08>, <&clock USI08>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi9_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_USI09_SPI */
- spi_10: spi@10900000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10900000 0x100>;
- samsung,spi-fifosize = <256>;
- interrupts = <0 INTREQ__USI09_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 21 &pdma0 20>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI09>, <&clock USI09>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi10_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_USI10_SPI */
- spi_11: spi@10920000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10920000 0x100>;
- samsung,spi-fifosize = <256>;
- interrupts = <0 INTREQ__USI10_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 23 &pdma0 22>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI10>, <&clock USI10>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi11_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC1_USI11_SPI */
- spi_12: spi@10940000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10940000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI11_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI11>, <&clock USI11>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi12_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI12_SPI */
- spi_13: spi@10520000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10520000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI12_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI12>, <&clock USI12>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi13_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI13_SPI */
- spi_14: spi@10540000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10540000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI13_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI13>, <&clock USI13>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi14_bus>;
- status = "disabled";
- };
- /* SPI USI_PERIC0_USI14_SPI */
- spi_15: spi@10560000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x10560000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI14_USI 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI14>, <&clock USI14>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi15_bus>;
- status = "disabled";
- };
- /* SPI USI_CMGP00 */
- spi_16: spi@14300000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x14300000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI_CMGP00 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI_CMGP00>, <&clock USI_CMGP00>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi16_bus>;
- status = "disabled";
- };
- /* SPI USI_CMGP01 */
- spi_17: spi@14320000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x1432000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI_CMGP01 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI_CMGP01>, <&clock USI_CMGP01>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi17_bus>;
- status = "disabled";
- };
- /* SPI USI_CMGP02 */
- spi_18: spi@14340000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x14340000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI_CMGP02 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI_CMGP02>, <&clock USI_CMGP02>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi18_bus>;
- status = "disabled";
- };
- /* SPI USI_CMGP03 */
- spi_19: spi@14360000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x14360000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI_CMGP03 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI_CMGP03>, <&clock USI_CMGP03>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi19_bus>;
- status = "disabled";
- };
- /* SPI USI_CHUB00 */
- spi_20: spi@13AC0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x13ac0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI_CHUB00 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI_CHUB00>, <&clock CHUB_USI00>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi20_bus>;
- status = "disabled";
- };
- /* SPI USI_CHUB01 */
- spi_21: spi@13AE0000 {
- compatible = "samsung,exynos-spi";
- reg = <0x0 0x13AE0000 0x100>;
- samsung,spi-fifosize = <64>;
- interrupts = <0 INTREQ__USI_CHUB01 0>;
- /*
- dma-mode;
- dmas = <&pdma0 31 &pdma0 30>;
- */
- dma-names = "tx", "rx";
- swap-mode;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock GATE_USI_CHUB01>, <&clock CHUB_USI01>;
- clock-names = "spi", "spi_busclk0";
- pinctrl-names = "default";
- pinctrl-0 = <&spi21_bus>;
- status = "disabled";
- };
- /* USI_PERIC0_UART_DBG */
- serial_0: uart@10440000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10440000 0x100>;
- samsung,fifo-size = <256>;
- interrupts = <0 INTREQ__UART_DBG 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_bus>;
- samsung,usi-serial-v2;
- clocks = <&clock GATE_UART_DBG>, <&clock UART_DBG>;
- clock-names = "gate_pclk0", "gate_uart0";
- status = "disabled";
- };
- smu: smu {
- compatible = "samsung,exynos-smu";
- };
- fmp: fmp {
- compatible = "samsung,exynos-fmp";
- exynos,host-type = "ufs";
- exynos-host = <&ufs>;
- exynos,block-type = "sda";
- exynos,fips-block_offset = <5>;
- };
- ufs: ufs@0x11120000 {
- /* ----------------------- */
- /* 1. SYSTEM CONFIGURATION */
- /* ----------------------- */
- compatible ="samsung,exynos-ufs";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- reg =
- <0x0 0x11120000 0x200>, /* 0: HCI standard */
- <0x0 0x11121100 0x200>, /* 1: Vendor specificed */
- <0x0 0x11110000 0x8000>, /* 2: UNIPRO */
- <0x0 0x11130000 0x100>; /* 3: UFS protector */
- interrupts = <0 INTREQ__UFS_EMBD 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
- clocks =
- /* aclk clock */
- <&clock GATE_UFS_EMBD>,
- /* unipro clocks */
- <&clock UFS_EMBD>;
- clock-names =
- /* aclk clocks */
- "GATE_UFS_EMBD",
- /* unipro clocks */
- "UFS_EMBD";
- /* PM QoS for INT power domain */
- /* ufs-pm-qos-int = <400000>;*/
- /* PM QoS for FSYS0 power domain */
- ufs-pm-qos-fsys0 = <200000>;
- /* DMA coherent callback, should be coupled with 'ufs-sys' */
- dma-coherent;
- /* ----------------------- */
- /* 2. UFS COMMON */
- /* ----------------------- */
- freq-table-hz = <0 0>, <0 0>;
- vcc-supply = <&ufs_fixed_vcc>;
- vcc-fixed-regulator;
- /* ----------------------- */
- /* 3. UFS EXYNOS */
- /* ----------------------- */
- hw-rev = <UFS_VER_0005>;
- /* power mode change */
- ufs,pmd-attr-lane = /bits/ 8 <2>;
- ufs,pmd-attr-gear = /bits/ 8 <3>;
- /* hiberantion */
- ufs-rx-min-activate-time-cap = <3>;
- ufs-rx-hibern8-time-cap = <2>;
- ufs-tx-hibern8-time-cap = <2>;
- /* board type for UFS CAL */
- brd-for-cal = <0>;
- /* smu */
- ufs-exynos-smu = <&smu>;
- /* ----------------------- */
- /* 4. ADDITIONAL NODES */
- /* ----------------------- */
- /* PHY isolation */
- ufs-phy {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- reg = <0x0 0x11124000 0x800>;
- ufs-phy-sys {
- reg = <0x0 0x14060724 0x4>;
- };
- };
- /* SYSREG */
- ufs-io-coherency {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- reg =
- <0x0 0x11010700 0x4>;
- mask = <(BIT_8 | BIT_9)>;
- bits = <(BIT_8 | BIT_9)>;
- };
- };
- ufs_fixed_vcc: fixedregulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "ufs-vcc";
- gpio = <&gpd0 2 0>;
- regulator-boot-on;
- enable-active-high;
- };
- reboot {
- compatible = "exynos,reboot";
- pmu_base = <0x14060000>;
- };
- handler {
- compatible = "exynos,handler";
- interrupts = <0 INTREQ__CPUCL0_ERRIRQ_0 0>, /* CPUCL0 L3 ECC */
- <0 INTREQ__CPUCL0_ERRIRQ_1 0>, /* CPUCL0_0 L1 ECC */
- <0 INTREQ__CPUCL0_ERRIRQ_2 0>, /* CPUCL0_1 L1 ECC */
- <0 INTREQ__CPUCL0_ERRIRQ_3 0>, /* CPUCL0_2 L1 ECC */
- <0 INTREQ__CPUCL0_ERRIRQ_4 0>, /* CPUCL0_3 L1 ECC */
- <0 INTREQ__CPUCL1_INTERRIRQ 0>; /* CPUCL1 L2, L3 ECC */
- };
- sysmmu_dpu0: sysmmu@160A0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x160A0000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_DPUD0_NONSECURE 0>,
- <0 INTREQ__SYSMMU_DPUD0_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SYSMMU_DPUD0>;
- port-name = "VGRF, VGF";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x160D0000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL4) SYSMMU_NOID>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x5, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x6, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x7, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0xC, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0xD, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x0, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x1, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x2, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x3, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x8, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL4) SYSMMU_ID_MASK(0x9, 0xF)>;
- #iommu-cells = <0>;
- };
- sysmmu_dpu1: sysmmu@160B0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x160B0000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_DPUD1_NONSECURE 0>,
- <0 INTREQ__SYSMMU_DPUD1_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SYSMMU_DPUD1>;
- port-name = "G0, VG0";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x160E0000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0xF)>;
- #iommu-cells = <0>;
- };
- sysmmu_dpu2: sysmmu@160C0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x160C0000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_DPUD2_NONSECURE 0>,
- <0 INTREQ__SYSMMU_DPUD2_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SYSMMU_DPUD2>;
- port-name = "G1, VG1, WB";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x160F0000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0xF)>,
- <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x18)>,
- <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x18)>,
- <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x18)>,
- <(SYSMMU_PORT_NO_PREFETCH_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x18)>;
- #iommu-cells = <0>;
- };
- iommu-domain_disp {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <&dsim_0>, <&displayport>;
- };
- iva: iva@0x17200000 {
- compatible = "samsung,iva";
- reg = <0x0 0x17200000 0x200000>;
- iommus = <&sysmmu_iva>;
- interrupt-names = "iva_mbox_irq";
- interrupts = <0 INTREQ__BLK_IVA_IVA_iva_ap_irq_aq_0 0>;
- clocks = <&clock GATE_IVA>;
- clock-names = "clk_iva";
- samsung,power-domain = <&pd_iva>;
- dvfs-dev = <&devfreq_6>;
- qos_rate = <534000>;
- mcu-info {
- mem_size = <0x20000>;
- shmem_size = <0x1000>;
- print_delay = <0>; /* us */
- };
- };
- sysmmu_iva: sysmmu@17020000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x17020000 0x9000>;
- interrupts = <0 INTREQ__BLK_IVA_SYSMMU_IVA_O_INTERRUPT_NONSECURE 0>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_IVA>;
- #iommu-cells = <0>;
- };
- iommu-domain_iva_score {
- compatible = "samsung,exynos-iommu-bus";
- /* #address-cells = <2>; */
- /* #size-cells = <1>; */
- /* ranges; */
- #dma-address-cells = <1>;
- #dma-size-cells = <1>;
- /* start address, size */
- dma-window = <0x80000000 0x70000000>;
- domain-clients = <&iva>;
- };
- score: score@16D00000 {
- compatible = "samsung,score";
- dma-coherent;
- reg = <0x0 0x16D00000 0x100000>;
- interrupts = <0 222 0>;
- clocks = <&clock GATE_SCORE_MASTER>, <&clock GATE_SCORE_KNIGHT>;
- clock-names = "dspm", "dsps";
- samsung,power-domain = <&pd_dsps>;
- iommus = <&sysmmu_score0>, <&sysmmu_score1>;
- qos_table = <534000 467000 336000 168000 34000>;
- default_qos = <534000>;
- };
- iommu-domain_score {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- /* #dma-address-cells = <1>; */
- /* #dma-size-cells = <1>; */
- /* start address, size */
- /* dma-window = <0x80000000 0x20000000>; */
- domain-clients = <&score>;
- };
- sysmmu_score0: sysmmu@16C20000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x16C20000 0x9000>;
- interrupts = <0 INTREQ__BLK_DSPM_SYSMMU_DSPM0_O_INTERRUPT_NONSECURE 0>,
- <0 INTREQ__BLK_DSPM_SYSMMU_DSPM0_O_INTERRUPT_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_DSPM0>;
- port-name = "SCore0";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x16C50000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
- #iommu-cells = <0>;
- };
- sysmmu_score1: sysmmu@16C30000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x16C30000 0x9000>;
- interrupts = <0 INTREQ__BLK_DSPM_SYSMMU_DSPM1_O_INTERRUPT_NONSECURE 0>,
- <0 INTREQ__BLK_DSPM_SYSMMU_DSPM1_O_INTERRUPT_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_DSPM1>;
- port-name = "SCore1";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x16C60000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
- #iommu-cells = <0>;
- };
- sysmmu_g2d0: sysmmu@17660000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x17660000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_G2DD0_interrupt_nonsecure 0>,
- <0 INTREQ__SYSMMU_G2DD0_interrupt_secure 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_G2DD0>;
- port-name = "G2D port0";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x17670000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL32) SYSMMU_NOID>;
- #iommu-cells = <0>;
- };
- sysmmu_g2d1: sysmmu@17680000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x17680000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_G2DD1_interrupt_nonsecure 0>,
- <0 INTREQ__SYSMMU_G2DD1_interrupt_secure 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_G2DD1>;
- port-name = "G2D port1";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x17690000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL32) SYSMMU_NOID>;
- #iommu-cells = <0>;
- };
- iommu-domain_g2d {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <&fimg2d>;
- #dma-address-cells = <1>;
- #dma-size-cells = <1>;
- dma-ranges;
- dma-window = <0x10000000 0x70000000>;
- };
- fimg2d: g2d@17620000 {
- compatible = "samsung,exynos9810-g2d";
- reg = <0x0 0x17620000 0x9000>;
- interrupts = <0 INTREQ__G2D 0>;
- clock-names = "gate";
- clocks = <&clock GATE_G2D>;
- samsung,power-domain = <&pd_g2d>;
- iommus = <&sysmmu_g2d0>, <&sysmmu_g2d1>;
- hw_ppc =
- /* sc_up none x1 x1/4 x1/9 x1/16 */
- <3400 3100 2200 3600 5100 7000 /* rgb32 non-rotated */
- 3300 2700 2000 3000 5200 6500 /* rgb32 rotated */
- 3000 2900 2600 3400 5100 11900 /* yuv2p non-rotated */
- 3200 2000 1900 3300 5200 7000 /* yuv2p rotated */
- 2400 1900 1900 2700 3100 4100 /* 8+2 non-rotated */
- 2500 900 900 2200 2900 3700 /* 8+2 rotated */
- 3800>; /* colorfill */
- g2d_dvfs_table = <534000 711000
- 400000 534000
- 336000 400000
- 267000 356000
- 178000 200000
- 107000 134000
- >;
- dma-coherent;
- };
- sysmmu_g2d2: sysmmu@17780000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x17780000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_G2DD2_interrupt_nonsecure 0>,
- <0 INTREQ__SYSMMU_G2DD2_interrupt_secure 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_G2DD2>;
- port-name = "MSCL, SMFC";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x17790000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL32) SYSMMU_NOID>,
- <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
- <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
- <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
- <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x0, 0x3)>,
- <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x1) | SYSMMU_BL2) SYSMMU_ID_MASK(0x2, 0x3)>;
- #iommu-cells = <0>;
- };
- iommu-domain_mscl_smfc {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <&astc>, <&smfc>, <&scaler_0>;
- };
- smfc: smfc@17700000 {
- compatible = "samsung,exynos8890-jpeg";
- dma-coherent;
- reg = <0x0 0x17700000 0x1000>;
- interrupts = <0 INTREQ__JPEG 0>;
- clocks = <&clock GATE_JPEG>;
- clock-names = "gate";
- iommus = <&sysmmu_g2d2>;
- smfc,int_qos_minlock = <534000>;
- samsung,power-domain = <&pd_g2d>;
- };
- astc: astc@17720000 {
- compatible = "samsung,exynos-astc";
- dma-coherent;
- reg = <0x0 0x17720000 0x1000>;
- interrupts = <0 INTREQ__ASTC 0>;
- clocks = <&clock GATE_ASTC>;
- clock-names = "gate";
- iommus = <&sysmmu_g2d2>;
- /* ASTC IP uses 533000, not 534000 */
- astc,int_qos_minlock = <533000>;
- samsung,power-domain = <&pd_g2d>;
- };
- scaler_0: scaler@17710000 {
- compatible = "samsung,exynos5-scaler";
- reg = <0x0 0x17710000 0x3000>;
- interrupts = <0 INTREQ__MSCL 0>;
- clocks = <&clock GATE_MSCL>;
- clock-names = "gate";
- iommus = <&sysmmu_g2d2>;
- dma-coherent;
- /* MIF / INT */
- mscl_qos_table = <
- 1794000 534000 2143260
- 1352000 400000 1610280
- 1014000 400000 1458000
- 845000 336000 648000
- 676000 267000 367200
- >;
- /* power domain */
- samsung,power-domain = <&pd_g2d>;
- };
- sysmmu_mfc0: sysmmu@17880000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x17880000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_MFCD0_interrupt_nonsecure 0>,
- <0 INTREQ__SYSMMU_MFCD0_interrupt_secure 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_MFCD0>;
- port-name = "MFC port0";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x17890000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>;
- #iommu-cells = <0>;
- };
- sysmmu_mfc1: sysmmu@178A0000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x178A0000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_MFCD1_interrupt_nonsecure 0>,
- <0 INTREQ__SYSMMU_MFCD1_interrupt_secure 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_MFCD1>;
- port-name = "MFC port1, WFD";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x178B0000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL8) SYSMMU_NOID>,
- <(SYSMMU_PORT_NO_PREFETCH_READWRITE(0x0) | SYSMMU_BL2) SYSMMU_ID_MASK(0x1, 0x1)>;
- #iommu-cells = <0>;
- };
- iommu-domain_mfc {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <&mfc_0>, <&tsmux>;
- };
- mfc_0: mfc0@178D0000 {
- compatible = "samsung,mfc-v6";
- reg = <0x0 0x178D0000 0x10000>;
- interrupts = <0 INTREQ__MFC 0>;
- clock-names = "aclk_mfc";
- clocks = <&clock GATE_MFC>;
- iommus = <&sysmmu_mfc0>, <&sysmmu_mfc1>;
- samsung,power-domain = <&pd_mfc>;
- status = "ok";
- ip_ver = <17>;
- clock_rate = <400000000>;
- min_rate = <100000>;
- num_qos_steps = <8>;
- max_qos_steps = <9>;
- max_mb = <4757298>;
- mfc_qos_table {
- mfc_qos_variant_0 {
- thrd_mb = <0>;
- freq_mfc = <200000>;
- freq_int = <178000>;
- freq_mif = <421000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <607>;
- };
- mfc_qos_variant_1 {
- thrd_mb = <253209>;
- freq_mfc = <336000>;
- freq_int = <267000>;
- freq_mif = <546000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <432>;
- };
- mfc_qos_variant_2 {
- thrd_mb = <518600>;
- freq_mfc = <400000>;
- freq_int = <336000>;
- freq_mif = <845000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <323>;
- };
- mfc_qos_variant_3 {
- thrd_mb = <1086358>;
- freq_mfc = <534000>;
- freq_int = <400000>;
- freq_mif = <1352000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <241>;
- };
- mfc_qos_variant_4 {
- thrd_mb = <1694860>;
- freq_mfc = <672000>;
- freq_int = <534000>;
- freq_mif = <1794000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <191>;
- };
- mfc_qos_variant_5 {
- thrd_mb = <2347751>;
- freq_mfc = <672000>;
- freq_int = <534000>;
- freq_mif = <1014000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <1>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <236>;
- };
- mfc_qos_variant_6 {
- thrd_mb = <3122858>;
- freq_mfc = <672000>;
- freq_int = <534000>;
- freq_mif = <1794000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <1>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <0>;
- time_fw = <191>;
- };
- mfc_qos_variant_7 {
- thrd_mb = <4230819>;
- freq_mfc = <672000>;
- freq_int = <534000>;
- freq_mif = <1794000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <1>;
- mo_uhd_enc60_value = <0>;
- time_fw = <191>;
- };
- /* special level for uhd 60fps enc */
- mfc_qos_variant_8 {
- thrd_mb = <1694860>;
- freq_mfc = <672000>;
- freq_int = <534000>;
- freq_mif = <1794000>;
- freq_cpu = <0>;
- freq_kfc = <0>;
- mo_value = <0>;
- mo_10bit_value = <0>;
- mo_uhd_enc60_value = <1>;
- time_fw = <191>;
- };
- };
- };
- tsmux: tsmux@178E0000 {
- compatible = "samsung,exynos-tsmux";
- reg = <0x0 0x178E0000 0x1000>;
- interrupts = <0 INTREQ__WFD 0>;
- iommus = <&sysmmu_mfc1>;
- /* power domain */
- samsung,power-domain = <&pd_mfc>;
- };
- sysmmu_aud: sysmmu@17E00000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x17E00000 0x9000>;
- interrupts = <0 INTREQ__AUD_SMMU 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_SMMU_ABOX>;
- port-name = "Abox";
- sysmmu,no-suspend;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>;
- #iommu-cells = <0>;
- };
- iommu-domain_aud {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <&abox>;
- };
- repeater: repeater@15100000 {
- compatible = "samsung,exynos-repeater";
- /* power domain */
- samsung,power-domain = <&pd_g2d>;
- };
- sysmmu_isphq: sysmmu@16650000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x16650000 0x9000>;
- interrupts = <0 INTREQ__BLK_ISPHQ_SYSMMU_ISPHQ_O_INTERRUPT_NONSECURE 0>,
- <0 INTREQ__BLK_ISPHQ_SYSMMU_ISPHQ_O_INTERRUPT_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_IS_ISPHQ_SYSMMU>;
- port-name = "ISPHQ";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x16660000>;
- sysmmu,tlb_property =
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL16) SYSMMU_NOID>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x1, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x2, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x0, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL16) SYSMMU_ID_MASK(0x1, 0xF)>;
- #iommu-cells = <0>;
- };
- sysmmu_isplp0: sysmmu@16450000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x16450000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_ISPLP0_NONSECURE 0>,
- <0 INTREQ__SYSMMU_ISPLP0_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_IS_SYSMMU_ISPLP0>;
- port-name = "GDC, ISPLP, VRA";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x16460000>;
- sysmmu,tlb_property =
- /* GDC */
- <(SYSMMU_PORT_NO_PREFETCH_READ(0x0) | SYSMMU_BL16) SYSMMU_NOID>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x1, 0xF)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL32) SYSMMU_ID_MASK(0x5, 0xF)>,
- /* ISPLP */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
- /* VRA */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3)>;
- #iommu-cells = <0>;
- };
- sysmmu_isplp1: sysmmu@16470000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x16470000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_ISPLP1_NONSECURE 0>,
- <0 INTREQ__SYSMMU_ISPLP1_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_IS_SYSMMU_ISPLP1>;
- port-name = "MC_SCALER";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x16480000>;
- sysmmu,tlb_property =
- /* RDMA0 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
- /* RDMA0 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
- /* WDMA0 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
- /* WDMA1 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0x3F)>,
- /* WDMA2 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
- /* WDMA3 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x9, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xA, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xB, 0x3F)>,
- /* WDMA4 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xD, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xE, 0x3F)>,
- /* WDMA5 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x11, 0x3F)>,
- /* WDMA0 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x15, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x16, 0x3F)>,
- /* WDMA1 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x17, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x3F)>,
- /* WDMA2 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x19, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1A, 0x3F)>,
- /* WDMA3 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1B, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1C, 0x3F)>,
- /* WDMA4 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1D, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1E, 0x3F)>,
- /* WDMA5 (2bit) */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1F, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x20, 0x3F)>;
- #iommu-cells = <0>;
- };
- sysmmu_isppre: sysmmu@16310000 {
- compatible = "samsung,exynos-sysmmu";
- reg = <0x0 0x16310000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_ISPPRE_NONSECURE 0>,
- <0 INTREQ__SYSMMU_ISPPRE_SECURE 0>;
- qos = <15>;
- clock-names = "aclk";
- clocks = <&clock GATE_IS_ISPPRE_SYSMMU>;
- port-name = "3AAM, 3AA, PDP";
- sysmmu,secure-irq;
- sysmmu,secure_base = <0x16300000>;
- sysmmu,tlb_property =
- /* 3AA0 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x0) | SYSMMU_BL1) SYSMMU_NOID>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xA, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xE, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x12, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x6, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xA, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xE, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x12, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x16, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1A, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1E, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x22, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x26, 0x3F)>,
- /* 3AA1 */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xB, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_READ(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x13, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x7, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xB, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xF, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x13, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x17, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1B, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1F, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x23, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x27, 0x3F)>,
- /* PDP */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x0, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x4, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x8, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0xC, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x10, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x14, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x18, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1C, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x20, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x24, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x28, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x2C, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x30, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x34, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x38, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x3C, 0x3F)>,
- /* PDP stat */
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x1, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x5, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x21, 0x3F)>,
- <(SYSMMU_PORT_PREFETCH_PREDICTION_WRITE(0x1) | SYSMMU_BL1) SYSMMU_ID_MASK(0x25, 0x3F)>;
- #iommu-cells = <0>;
- };
- iommu-domain_isp {
- compatible = "samsung,exynos-iommu-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- domain-clients = <&fimc_is>, <&fimc_is_sensor0>, <&fimc_is_sensor1>,
- <&fimc_is_sensor2>, <&fimc_is_sensor3>, <&camerapp_gdc>;
- };
- speedy@141C0000 {
- compatible = "samsung,exynos-speedy";
- reg = <0x0 0x141C0000 0x2000>;
- interrupts = <0 INTREQ__SPEEDY_APM 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&speedy_bus>;
- #if 0
- clocks = <&clock GATE_SPEEDY_BATCHER_WRAP_BATCHER_AP>;
- clock-names = "gate_speedy";
- #endif
- status = "disabled";
- };
- acpm {
- compatible = "samsung,exynos-acpm";
- #address-cells = <2>;
- #size-cells = <1>;
- acpm-ipc-channel = <4>;
- fvmap_offset = <0x6700>;
- reg = <0x0 0x14020000 0x1000>; /* TIMER_APM */
- reg-names = "timer_apm";
- peritimer-cnt = <0xFFFF>;
- };
- acpm_ipc {
- compatible = "samsung,exynos-acpm-ipc";
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <0 INTREQ__MAILBOX_APM2AP 0>; /* AP2APM MAILBOX SPI NUM*/
- reg = <0x0 0x14100000 0x1000>, /* AP2APM MAILBOX */
- <0x0 0x2039000 0x30000>; /* APM SRAM */
- initdata-base = <0x7F00>;
- num-timestamps = <32>;
- debug-log-level = <0>;
- logging-period = <500>;
- dump-base = <0x203C000>;
- dump-size = <0x1D000>; /* 116KB */
- };
- exynos_flexpmu_dbg {
- compatible = "samsung,exynos-flexpmu-dbg";
- #address-cells = <2>;
- #size-cells = <1>;
- data-base = <0x204F800>;
- data-size = <0x400>;
- };
- acpm_dvfs {
- compatible = "samsung,exynos-acpm-dvfs";
- acpm-ipc-channel = <5>;
- };
- acpm_s2d {
- compatible = "samsung,exynos-acpm-s2d";
- acpm-ipc-channel = <11>;
- };
- devfreq_0: devfreq_mif@17000010 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000010 0x0>;
- devfreq_type = "mif";
- devfreq_domain_name = "dvfs_mif";
- /* Delay time */
- use_delay_time = "true";
- delay_time_list = "20";
- freq_info = <2093000 208000 1014000 208000 2093000 2093000>;
- /* initial_freq, default_qos, suspend_freq, min_freq, max_freq reboot_freq */
- /* Booting value */
- boot_info = <40 1794000>;
- /* boot_qos_timeout, boot_freq */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_MIF>;
- acpm-ipc-channel = <1>;
- use_acpm = "true";
- };
- devfreq_1: devfreq_int@17000020 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000020 0x0>;
- devfreq_type = "int";
- devfreq_domain_name = "dvfs_int";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <667000 178000 107000 107000 667000 667000>;
- /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 667000>;
- /* boot_qos_timeout, boot_freq */
- /* default_dev_profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_INT>;
- acpm-ipc-channel = <1>;
- use_acpm = "true";
- };
- devfreq_2: devfreq_intcam@17000030 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000030 0x0>;
- devfreq_type = "intcam";
- devfreq_domain_name = "dvfs_intcam";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <690000 630000 690000 630000 690000 690000>;
- /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 640000>;
- /* boot_qos_timeout, boot_freq */
- /* default_dev_profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_INTCAM>;
- };
- devfreq_3: devfreq_disp@17000040 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000040 0x0>;
- devfreq_type = "disp";
- devfreq_domain_name = "dvfs_disp";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <640000 200000 640000 200000 640000 640000>;
- /* <initial_freq, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 640000>;
- /* boot_qos_timeout, boot_freq */
- /* default dev profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_DISP>;
- };
- devfreq_4: devfreq_cam@17000050 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000050 0x0>;
- devfreq_type = "cam";
- devfreq_domain_name = "dvfs_cam";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <690000 590000 690000 590000 690000 690000>;
- /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 630000>;
- /* boot_qos_timeout, boot_freq */
- /* default dev profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_CAM>;
- };
- devfreq_5: devfreq_aud@17000060 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000060 0x0>;
- devfreq_type = "aud";
- devfreq_domain_name = "dvfs_aud";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <295000 295000 295000 295000 1180000 295000>;
- /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 295000>;
- /* boot_qos_timeout, boot_freq */
- /* default dev profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_AUD>;
- };
- devfreq_6: devfreq_iva@17000070 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000070 0x0>;
- devfreq_type = "iva";
- devfreq_domain_name = "dvfs_iva";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <34000 34000 34000 34000 534000 34000>;
- /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 34000>;
- /* boot_qos_timeout, boot_freq */
- /* default dev profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_IVA>;
- };
- devfreq_7: devfreq_score@17000080 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000080 0x0>;
- devfreq_type = "score";
- devfreq_domain_name = "dvfs_score";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <34000 34000 34000 34000 534000 34000>;
- /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 34000>;
- /* boot_qos_timeout, boot_freq */
- /* default dev profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_SCORE>;
- };
- devfreq_8: devfreq_fsys0@17000090 {
- compatible = "samsung,exynos-devfreq";
- reg = <0x0 0x17000090 0x0>;
- devfreq_type = "fsys0";
- devfreq_domain_name = "dvfs_fsys0";
- /* Delay time */
- use_delay_time = "false";
- freq_info = <336000 73000 336000 73000 336000 336000>;
- /* <initial, default_qos, suspend_freq, min, max, reboot_freq> */
- /* Booting value */
- boot_info = <40 336000>;
- /* boot_qos_timeout, boot_freq */
- /* default dev profile */
- use_get_dev = "false";
- polling_ms = <0>;
- /* governor data */
- gov_name = "interactive";
- use_reg = "false";
- use_tmu = "true";
- use_cl_dvfs = "false";
- use_sw_clk = "false";
- dfs_id = <ACPM_DVFS_FSYS0>;
- };
- exynos_adc: adc@14230000 {
- compatible = "samsung,exynos-adc-v3";
- reg = <0x0 0x14230000 0x100>;
- interrupts = <0 INTREQ__ADC_CMGP_S0 0>;
- #io-channel-cells = <1>;
- io-channel-ranges;
- clocks = <&clock GATE_ADC_CMGP>;
- clock-names = "gate_adcif";
- };
- rtc@141E0000 {
- compatible = "samsung,exynos8-rtc";
- reg = <0x0 0x141E0000 0x100>;
- interrupts = <0 INTREQ__RTC_ALARM_INT 0>, <0 INTREQ__RTC_TIC_INT_0 0>;
- };
- watchdog_cl0@10050000 {
- compatible = "samsung,exynos8-wdt";
- reg = <0x0 0x10050000 0x100>;
- interrupts = <0 INTREQ__WDT_CLUSTER0 0>;
- clocks = <&clock OSCCLK>, <&clock UMUX_CLKCMU_PERIS_BUS>;
- clock-names = "rate_watchdog", "gate_watchdog";
- timeout-sec = <30>;
- samsung,syscon-phandle = <&pmu_system_controller>;
- index = <0>; /* if little cluster then index is 0 */
- };
- watchdog_cl1@10060000 {
- compatible = "samsung,exynos7-wdt";
- reg = <0x0 0x10060000 0x100>;
- interrupts = <0 INTREQ__WDT_CLUSTER1 0>;
- clocks = <&clock OSCCLK>, <&clock UMUX_CLKCMU_PERIS_BUS>;
- clock-names = "rate_watchdog", "gate_watchdog";
- timeout-sec = <20>;
- samsung,syscon-phandle = <&pmu_system_controller>;
- index = <1>; /* if big cluster then index is 1*/
- use_multistage_wdt; /* Use FIQ debug watchdog */
- };
- /* USI_PERIC1_UART_BT */
- serial_1: uart@10840000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10840000 0x100>;
- samsung,fifo-size = <256>;
- interrupts = <0 INTREQ__UART_BT 0>;
- pinctrl-names = "default", "rts";
- pinctrl-0 = <&uart1_bus_single &uart1_rxd_pull>; /* or _bus_dual */
- pinctrl-1 = <&uart1_bus_rts>;
- samsung,usi-serial-v2;
- clocks = <&clock GATE_UART_BT>, <&clock UART_BT>;
- clock-names = "gate_pclk1", "gate_uart1";
- status = "disabled";
- };
- /* USI_PERIC0_USI00_UART */
- serial_2: uart@10450000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10450000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI00_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI00>, <&clock USI00>;
- clock-names = "gate_pclk2", "gate_uart2";
- status = "disabled";
- };
- /* USI_PERIC0_USI01_UART */
- serial_3: uart@10470000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10470000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI01_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI01>, <&clock USI01>;
- clock-names = "gate_pclk3", "gate_uart3";
- status = "disabled";
- };
- /* USI_PERIC0_USI02_UART */
- serial_4: uart@10490000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10490000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI02_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart4_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI02>, <&clock USI02>;
- clock-names = "gate_pclk4", "gate_uart4";
- status = "disabled";
- };
- /* USI_PERIC0_USI03_UART */
- serial_5: uart@104B0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x104B0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI03_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart5_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI03>, <&clock USI03>;
- clock-names = "gate_pclk5", "gate_uart5";
- status = "disabled";
- };
- /* USI_PERIC0_USI04_UART */
- serial_6: uart@104D0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x104D0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI04_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart6_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI04>, <&clock USI04>;
- clock-names = "gate_pclk6", "gate_uart6";
- status = "disabled";
- };
- /* USI_PERIC0_USI05_UART */
- serial_7: uart@104F0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x104F0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI05_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart7_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI05>, <&clock USI05>;
- clock-names = "gate_pclk7", "gate_uart7";
- status = "disabled";
- };
- /* USI_PERIC1_USI06_UART */
- serial_8: uart@108A0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x108A0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI06_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart8_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI06>, <&clock USI06>;
- clock-names = "gate_pclk8", "gate_uart8";
- status = "disabled";
- };
- /* USI_PERIC1_USI07_UART */
- serial_9: uart@108C0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x108C0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI07_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart9_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI07>, <&clock USI07>;
- clock-names = "gate_pclk9", "gate_uart9";
- status = "disabled";
- };
- /* USI_PERIC1_USI08_UART */
- serial_10: uart@108E0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x108E0000 0x100>;
- samsung,fifo-size = <256>;
- interrupts = <0 INTREQ__USI08_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart10_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI08>, <&clock USI08>;
- clock-names = "gate_pclk10", "gate_uart10";
- status = "disabled";
- };
- /* USI_PERIC1_USI09_UART */
- serial_11: uart@10900000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10900000 0x100>;
- samsung,fifo-size = <256>;
- interrupts = <0 INTREQ__USI09_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart11_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI09>, <&clock USI09>;
- clock-names = "gate_pclk11", "gate_uart11";
- status = "disabled";
- };
- /* USI_PERIC1_USI10_UART */
- serial_12: uart@10920000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10920000 0x100>;
- samsung,fifo-size = <256>;
- interrupts = <0 INTREQ__USI10_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart12_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI10>, <&clock USI10>;
- clock-names = "gate_pclk12", "gate_uart12";
- status = "disabled";
- };
- /* USI_PERIC1_USI11_UART */
- serial_13: uart@10940000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10940000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI11_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart13_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI11>, <&clock USI11>;
- clock-names = "gate_pclk13", "gate_uart13";
- status = "disabled";
- };
- /* USI_PERIC0_USI12_UART */
- serial_14: uart@10520000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10520000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI12_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart14_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI12>, <&clock USI12>;
- clock-names = "gate_pclk14", "gate_uart14";
- status = "disabled";
- };
- /* USI_PERIC0_USI13_UART */
- serial_15: uart@10540000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10540000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI13_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart15_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI13>, <&clock USI13>;
- clock-names = "gate_pclk15", "gate_uart15";
- status = "disabled";
- };
- /* USI_PERIC0_USI14_UART */
- serial_16: uart@10560000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x10560000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI14_USI 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart16_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI14>, <&clock USI14>;
- clock-names = "gate_pclk16", "gate_uart16";
- status = "disabled";
- };
- /* USI_CMGP00_UART */
- serial_17: uart@14300000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x14300000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI_CMGP00 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart17_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI_CMGP00>, <&clock USI_CMGP00>;
- clock-names = "gate_pclk17", "gate_uart17";
- status = "disabled";
- };
- /* USI_CMGP01_UART */
- serial_18: uart@14320000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x14320000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI_CMGP01 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart18_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI_CMGP01>, <&clock USI_CMGP01>;
- clock-names = "gate_pclk18", "gate_uart18";
- status = "disabled";
- };
- /* USI_CMGP02_UART */
- serial_19: uart@14340000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x14340000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI_CMGP02 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart19_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI_CMGP02>, <&clock USI_CMGP02>;
- clock-names = "gate_pclk19", "gate_uart10";
- status = "disabled";
- };
- /* USI_CMGP03_UART */
- serial_20: uart@14360000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x14360000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI_CMGP03 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart20_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI_CMGP03>, <&clock USI_CMGP03>;
- clock-names = "gate_pclk20", "gate_uart20";
- status = "disabled";
- };
- /* USI_CHUB00_UART */
- serial_21: uart@13AC0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x13ac0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI_CHUB00 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart21_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI_CHUB00>, <&clock CHUB_USI00>;
- clock-names = "gate_pclk21", "gate_uart21";
- status = "disabled";
- };
- /* USI_CHUB01_UART */
- serial_22: uart@13AE0000 {
- compatible = "samsung,exynos-uart";
- samsung,separate-uart-clk;
- reg = <0x0 0x13ae0000 0x100>;
- samsung,fifo-size = <64>;
- interrupts = <0 INTREQ__USI_CHUB01 0>;
- pinctrl-names = "default";
- pinctrl-0 = <&uart22_bus_single>; /* or _bus_dual */
- samsung,usi-serial-v2;
- clocks = <&clock GATE_USI_CHUB01>, <&clock CHUB_USI01>;
- clock-names = "gate_pclk22", "gate_uart22";
- status = "disabled";
- };
- coresight@1e000000 {
- compatible = "exynos,coresight";
- base = <0x1e000000>;
- sj-offset = <0x6000>;
- /* coresight component count */
- funnel-num = <3>;
- etf-num = <2>;
- cl0_cpu0@800000 {
- device_type = "cs";
- dbg-offset = <0x810000>;
- etm-offset = <0x840000>;
- funnel-port = <1 0>;
- };
- cl0_cpu1@900000 {
- device_type = "cs";
- dbg-offset = <0x910000>;
- etm-offset = <0x940000>;
- funnel-port = <1 1>;
- };
- cl0_cpu2@A00000 {
- device_type = "cs";
- dbg-offset = <0xA10000>;
- etm-offset = <0xA40000>;
- funnel-port = <1 2>;
- };
- cl0_cpu3@B00000 {
- device_type = "cs";
- dbg-offset = <0xB10000>;
- etm-offset = <0xB40000>;
- funnel-port = <1 3>;
- };
- cl1_cpu0@400000 {
- device_type = "cs";
- dbg-offset = <0x410000>;
- etm-offset = <0x440000>;
- funnel-port = <0 0>;
- };
- cl1_cpu1@500000 {
- device_type = "cs";
- dbg-offset = <0x510000>;
- etm-offset = <0x540000>;
- funnel-port = <0 1>;
- };
- cl1_cpu2@600000 {
- device_type = "cs";
- dbg-offset = <0x610000>;
- etm-offset = <0x640000>;
- funnel-port = <0 2>;
- };
- cl1_cpu3@700000 {
- device_type = "cs";
- dbg-offset = <0x710000>;
- etm-offset = <0x740000>;
- funnel-port = <0 3>;
- };
- cs_etf0: cs_etf0@C000 {
- device_type = "etf";
- offset = <0x4000>;
- funnel-port = <2 0>;
- };
- cs_etf1: cs_etf1@5000 {
- device_type = "etf";
- offset = <0x5000>;
- funnel-port = <2 1>;
- };
- cs_funnel0@4000 {
- device_type = "funnel";
- offset = <0x7000>;
- };
- cs_funnel1@9000 {
- device_type = "funnel";
- offset = <0x8000>;
- };
- cs_funnelm2@9000 {
- device_type = "funnel";
- offset = <0x9000>;
- };
- cs_etr@A000 {
- device_type = "etr";
- samsung,cs-sfr = <0x1E00c000 0x100>;
- samsung,q-offset = <0x2c>;
- offset = <0xA000>;
- };
- };
- sec_pwm: pwm@10510000 {
- compatible = "samsung,s3c6400-pwm";
- reg = <0x0 0x10510000 0x1000>;
- samsung,pwm-outputs = <0>, <1>, <2>, <3>, <4>;
- #pwm-cells = <3>;
- clocks = <&clock UMUX_CLKCMU_PERIC0_BUS>, <&clock OSCCLK>;
- clock-names = "pwm_pclk", "pwm_sclk";
- status = "ok";
- };
- dwmmc_2: dwmmc2@11500000 {
- compatible = "samsung,exynos-dw-mshc";
- reg = <0x0 0x11500000 0x2000>;
- reg-names = "dw_mmc";
- interrupts = <0 INTREQ__MMC_CARD 0>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clock MMC_CARD>, <&clock GATE_MMC_CARD>;
- clock-names = "ciu", "ciu_gate";
- status = "disabled";
- };
- abox_gic: abox_gic@0x17CF0000 {
- compatible = "samsung,abox_gic";
- reg = <0x0 0x17CF1000 0x1000>, <0x0 0x17CF2000 0x1004>;
- reg-names = "gicd", "gicc";
- interrupts = <0 INTREQ__ABOX_GIC400 0>;
- };
- abox: abox@0x17C50000 {
- compatible = "samsung,abox";
- reg = <0x0 0x17C50000 0x10000>, <0x0 0x17C10000 0x10000>, <0x0 0x17D00000 0x31000>;
- reg-names = "sfr", "sysreg", "sram";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
- quirks = "try to asrc off";
- #sound-dai-cells = <1>;
- samsung,power-domain = <&pd_aud>;
- ipc_tx_offset = <0x30000>;
- ipc_rx_offset = <0x30300>;
- ipc_tx_ack_offset = <0x302FC>;
- ipc_rx_ack_offset = <0x305FC>;
- abox_gic = <&abox_gic>;
- clocks = <&clock PLL_OUT_AUD>, <&clock GATE_ABOX_DUMMY>,
- <&clock DOUT_CLK_ABOX_AUDIF>, <&clock DOUT_CLK_ABOX_DMIC>,
- <&clock DOUT_CLK_ABOX_ACLK>;
- clock-names = "pll", "cpu", "audif", "dmic", "bus";
- uaif_max_div = <512>;
- iommus = <&sysmmu_aud>;
- pm_qos_int = <0 0 0 0 0>;
- pm_qos_aud = <1180000 800000 590000 394000 0>;
- abox_rdma_0: abox_rdma@0x17C51000 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51000 0x100>;
- id = <0>;
- type = "normal";
- };
- abox_rdma_1: abox_rdma@0x17C51100 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51100 0x100>;
- id = <1>;
- type = "normal";
- };
- abox_rdma_2: abox_rdma@0x17C51200 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51200 0x100>;
- id = <2>;
- type = "normal";
- };
- abox_rdma_3: abox_rdma@0x17C51300 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51300 0x100>;
- id = <3>;
- type = "sync";
- };
- abox_rdma_4: abox_rdma@0x17C51400 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51400 0x100>;
- id = <4>;
- type = "call";
- };
- abox_rdma_5: abox_rdma@0x17C51500 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51500 0x100>, <0x0 0x17D30600 0x70>;
- id = <5>;
- type = "compress";
- };
- abox_rdma_6: abox_rdma@0x17C51600 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51600 0x100>;
- id = <6>;
- type = "realtime";
- };
- abox_rdma_7: abox_rdma@0x17C51700 {
- compatible = "samsung,abox-rdma";
- reg = <0x0 0x17C51700 0x100>;
- id = <7>;
- type = "realtime";
- };
- abox_wdma_0: abox_wdma@0x17C52000 {
- compatible = "samsung,abox-wdma";
- reg = <0x0 0x17C52000 0x100>;
- id = <0>;
- type = "realtime";
- };
- abox_wdma_1: abox_wdma@0x17C52100 {
- compatible = "samsung,abox-wdma";
- reg = <0x0 0x17C52100 0x100>;
- id = <1>;
- type = "normal";
- };
- abox_wdma_2: abox_wdma@0x17C52200 {
- compatible = "samsung,abox-wdma";
- reg = <0x0 0x17C52200 0x100>;
- id = <2>;
- type = "call";
- };
- abox_wdma_3: abox_wdma@0x17C52300 {
- compatible = "samsung,abox-wdma";
- reg = <0x0 0x17C52300 0x100>;
- id = <3>;
- type = "realtime";
- };
- abox_wdma_4: abox_wdma@0x17C52400 {
- compatible = "samsung,abox-wdma";
- reg = <0x0 0x17C52400 0x100>;
- id = <4>;
- type = "vi-sensing";
- };
- abox_uaif_0: abox_uaif@0x17C50500 {
- compatible = "samsung,abox-uaif";
- reg = <0x0 0x17C50500 0x10>;
- id = <0>;
- clocks = <&clock DOUT_CLK_ABOX_UAIF0>, <&clock GATE_ABOX_BCLK0>;
- clock-names = "bclk", "bclk_gate";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&aud_i2s0_bus>;
- pinctrl-1 = <&aud_i2s0_idle>;
- };
- abox_uaif_1: abox_uaif@0x17C50510 {
- compatible = "samsung,abox-uaif";
- reg = <0x0 0x17C50510 0x10>;
- id = <1>;
- clocks = <&clock DOUT_CLK_ABOX_UAIF1>, <&clock GATE_ABOX_BCLK1>;
- clock-names = "bclk", "bclk_gate";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&aud_i2s1_bus>;
- pinctrl-1 = <&aud_i2s1_idle>;
- };
- abox_uaif_2: abox_uaif@0x17C50520 {
- compatible = "samsung,abox-uaif";
- reg = <0x0 0x17C50520 0x10>;
- id = <2>;
- clocks = <&clock DOUT_CLK_ABOX_UAIF2>, <&clock GATE_ABOX_BCLK2>;
- clock-names = "bclk", "bclk_gate";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&aud_i2s2_bus>;
- pinctrl-1 = <&aud_i2s2_idle>;
- };
- abox_uaif_3: abox_uaif@0x17C50530 {
- compatible = "samsung,abox-uaif";
- reg = <0x0 0x17C50530 0x10>;
- id = <3>;
- clocks = <&clock DOUT_CLK_ABOX_UAIF3>, <&clock GATE_ABOX_BCLK3>;
- clock-names = "bclk", "bclk_gate";
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&aud_i2s3_bus>;
- pinctrl-1 = <&aud_i2s3_idle>;
- };
- abox_dsif: abox_dsif@0x17C50550 {
- compatible = "samsung,abox-dsif";
- reg = <0x0 0x17C50550 0x10>;
- id = <5>;
- clocks = <&clock DOUT_CLK_ABOX_DSIF>, <&clock GATE_ABOX_BCLK_DSIF>;
- clock-names = "bclk", "bclk_gate";
- /* DSIF and UAIF2 shares GPIO
- * pinctrl-names = "default", "sleep";
- * pinctrl-0 = <&aud_dsd_bus>;
- * pinctrl-1 = <&aud_dsd_idle>;
- */
- };
- abox_effect: abox_effect@0x17D2E000 {
- compatible = "samsung,abox-effect";
- reg = <0x0 0x17D2E000 0x1000>;
- reg-names = "reg";
- abox = <&abox>;
- };
- abox_debug: abox_debug@0 {
- compatible = "samsung,abox-debug";
- memory-region = <&abox_rmem>;
- reg = <0x0 0x0 0x0>;
- };
- abox_vss: abox_vss@0 {
- compatible = "samsung,abox-vss";
- magic_offset = <0x600000>;
- reg = <0x0 0x0 0x0>;
- };
- ext_bin_0: ext_bin@0 {
- status = "disabled";
- samsung,name = "dsm.bin";
- samsung,area = <1>; /* 0:SRAM, 1:DRAM, 2:VSS */
- samsung,offset = <0x502000>;
- };
- ext_bin_1: ext_bin@1 {
- status = "okay";
- samsung,name = "AP_AUDIO_SLSI.bin";
- samsung,area = <1>;
- samsung,offset = <0x7E0000>;
- };
- ext_bin_2: ext_bin@2 {
- status = "okay";
- samsung,name = "APBargeIn_AUDIO_SLSI.bin";
- samsung,area = <1>;
- samsung,offset = <0x7DC000>;
- };
- ext_bin_3: ext_bin@3 {
- status = "disabled";
- samsung,name = "SoundBoosterParam.bin";
- samsung,area = <1>;
- samsung,offset = <0x4FC000>;
- };
- ext_bin_4: ext_bin@4 {
- status = "okay";
- samsung,name = "APDV_AUDIO_SLSI.bin";
- samsung,area = <1>;
- samsung,offset = <0x4D0000>;
- };
- ext_bin_5: ext_bin@5 {
- status = "okay";
- samsung,name = "APBiBF_AUDIO_SLSI.bin";
- samsung,area = <1>;
- samsung,offset = <0x7DF000>;
- };
- ext_bin_6: ext_bin@6 {
- status = "disabled";
- samsung,name = "dummy.bin";
- samsung,area = <1>;
- samsung,offset = <0x800000>;
- };
- ext_bin_7: ext_bin@7 {
- status = "disabled";
- samsung,name = "dummy.bin";
- samsung,area = <1>;
- samsung,offset = <0x800000>;
- };
- };
- /* tbase */
- tee {
- compatible = "samsung,exynos-tee";
- interrupts = <0 233 0>;
- };
- seclog {
- compatible = "samsung,exynos-seclog";
- interrupts = <0 INTREQ__PPMU_DPUD1_UPPER_OR_NORMAL 0>;
- };
- /* Secure RPMB */
- ufs-srpmb {
- compatible = "samsung,ufs-srpmb";
- interrupts = <0 460 0>;
- };
- exynos_dm: exynos-dm@17000000 {
- compatible = "samsung,exynos-dvfs-manager";
- reg = <0x0 0x17000000 0x0>;
- acpm-ipc-channel = <1>;
- cpufreq_cl0 {
- dm-index = <DM_CPU_CL0>;
- available = "true";
- cal_id = <ACPM_DVFS_CPUCL0>;
- };
- cpufreq_cl1 {
- dm-index = <DM_CPU_CL1>;
- available = "true";
- cal_id = <ACPM_DVFS_CPUCL1>;
- };
- devfreq_mif {
- dm-index = <DM_MIF>;
- available = "true";
- policy_use = "true";
- cal_id = <ACPM_DVFS_MIF>;
- };
- devfreq_int {
- dm-index = <DM_INT>;
- available = "true";
- policy_use = "true";
- cal_id = <ACPM_DVFS_INT>;
- };
- devfreq_intcam {
- dm-index = <DM_INTCAM>;
- available = "true";
- cal_id = <ACPM_DVFS_INTCAM>;
- };
- devfreq_fsys0 {
- dm-index = <DM_FSYS0>;
- available = "true";
- cal_id = <ACPM_DVFS_FSYS0>;
- };
- devfreq_cam {
- dm-index = <DM_CAM>;
- available = "true";
- cal_id = <ACPM_DVFS_CAM>;
- };
- devfreq_disp {
- dm-index = <DM_DISP>;
- available = "true";
- cal_id = <ACPM_DVFS_DISP>;
- };
- devfreq_aud {
- dm-index = <DM_AUD>;
- available = "true";
- cal_id = <ACPM_DVFS_AUD>;
- };
- devfreq_iva {
- dm-index = <DM_IVA>;
- available = "true";
- cal_id = <ACPM_DVFS_IVA>;
- };
- devfreq_score {
- dm-index = <DM_SCORE>;
- available = "true";
- cal_id = <ACPM_DVFS_SCORE>;
- };
- dvfs_gpu {
- dm-index = <DM_GPU>;
- available = "false";
- cal_id = <ACPM_DVFS_G3D>;
- };
- };
- schedutil {
- domain@0 {
- device_type = "freqvar-tune";
- shared-cpus = "0-3";
- boost_table = < 100 598000 60 715000 30 832000 20 949000 10 1053000 0 >;
- up_rate_limit_table = < 5 >;
- down_rate_limit_table = < 5 >;
- upscale_ratio_table = < 80 >;
- };
- domain@1 {
- device_type = "freqvar-tune";
- shared-cpus = "4-7";
- boost_table = < 20 858000 15 962000 5 1261000 0 >;
- up_rate_limit_table = < 5 >;
- down_rate_limit_table = < 5 >;
- upscale_ratio_table = < 80 >;
- };
- };
- cpu_hotplug {
- compatible = "exynos, cpu_hotplug";
- boot_lock_time = <40>;
- fast_hp_cpus = "5-7";
- };
- hotplug_governor {
- compatible = "exynos, hotplug_governor";
- single_change_ms = <30>;
- dual_change_ms = <30>;
- quad_change_ms = <15>;
- big_heavy_thr = <600>;
- lit_heavy_thr = <180>;
- big_idle_thr = <106>;
- lit_idle_thr = <46>;
- ldsum_heavy_thr = <800>;
- ldsum_enabled = <0>;
- skip_lit_enabled = <0>;
- cl_busy_ratio = <65>;
- /* single_freq is parsed from ECT */
- dual_freq = <2314000>;
- triple_freq = <1794000>;
- quad_freq = <1794000>;
- cal-id = <ACPM_DVFS_CPUCL1>;
- };
- schedutil_gov {
- schedutil_domain0: domain@0 {
- device_type = "schedutil-domain";
- shared-cpus = "0-3";
- enabled = <0>; /* Disable */
- qos_min_class = <3>;
- };
- schedutil_domain1: domain@1 {
- device_type = "schedutil-domain";
- shared-cpus = "4-7";
- enabled = <1>; /* Enabled */
- expired_time = <80>; /* 80ms */
- qos_min_class = <5>;
- };
- };
- cpufreq {
- cpufreq_domain0: domain@0 {
- device_type = "cpufreq-domain";
- sibling-cpus = "0-3";
- cal-id = <ACPM_DVFS_CPUCL0>;
- dm-type = <DM_CPU_CL0>;
- min-freq = <455000>;
- /* PM QoS Class ID*/
- pm_qos-min-class = <3>;
- pm_qos-max-class = <4>;
- user-default-qos = <715000>;
- #cooling-cells = <2>; /* min followed by max */
- dm-constraints {
- mif-perf {
- const-type = <CONSTRAINT_MIN>;
- dm-type = <DM_MIF>;
- /* cpu mif */
- table = < 2002000 845000
- 1898000 845000
- 1794000 845000
- 1690000 845000
- 1456000 676000
- 1248000 676000
- 1053000 676000
- 949000 676000
- 832000 546000
- 715000 546000
- 598000 421000
- 455000 0
- >;
- };
- mif-skew {
- guidance;
- const-type = <CONSTRAINT_MIN>;
- dm-type = <DM_MIF>;
- ect-name = "dvfs_cpucl0";
- };
- };
- };
- cpufreq_domain1: domain@1 {
- device_type = "cpufreq-domain";
- sibling-cpus = "4-7";
- cal-id = <ACPM_DVFS_CPUCL1>;
- dm-type = <DM_CPU_CL1>;
- min-freq = <650000>;
- max-freq = <1794000>;
- policy-max = <1794000>;
- /* PM QoS Class ID*/
- pm_qos-min-class = <5>;
- pm_qos-max-class = <6>;
- pm_qos-booting = <1794000>;
- #cooling-cells = <2>; /* min followed by max */
- dm-constraints {
- mif-perf {
- const-type = <CONSTRAINT_MIN>;
- dm-type = <DM_MIF>;
- /* cpu mif */
- table = < 2964000 1794000
- 2860000 1794000
- 2704000 1794000
- 2652000 1794000
- 2496000 1794000
- 2314000 1794000
- 2158000 1794000
- 2002000 1794000
- 1924000 1794000
- 1794000 1794000
- 1690000 1539000
- 1586000 1014000
- 1469000 845000
- 1261000 676000
- 1170000 676000
- 1066000 676000
- 962000 546000
- 858000 546000
- 741000 421000
- 650000 421000
- 598000 421000 >;
- };
- mif-skew {
- guidance;
- const-type = <CONSTRAINT_MIN>;
- dm-type = <DM_MIF>;
- ect-name = "dvfs_cpucl1";
- };
- };
- };
- };
- tmuctrl_0: BIG@10070000 {
- compatible = "samsung,exynos9810-tmu";
- reg = <0x0 0x10070000 0x700>;
- interrupts = <0 INTREQ__TMU_TMU_TOP 0>;
- tmu_name = "BIG";
- id = <0>;
- sensors = <94>; /* 0x5E */
- sensing_mode = "balance";
- hotplug_enable = <1>;
- hotplug_in_threshold = <91>;
- hotplug_out_threshold = <96>;
- #include "exynos9810-tmu-sensor-conf.dtsi"
- };
- tmuctrl_1: LITTLE@10070000 {
- compatible = "samsung,exynos9810-tmu";
- reg = <0x0 0x10070000 0x700>;
- interrupts = <0 INTREQ__TMU_TMU_TOP 0>;
- tmu_name = "LITTLE";
- id = <1>;
- sensors = <32>; /* 0x20 */
- sensing_mode = "max";
- #include "exynos9810-tmu-sensor-conf.dtsi"
- };
- tmuctrl_2: G3D@10074000 {
- compatible = "samsung,exynos9810-tmu";
- reg = <0x0 0x10074000 0x700>;
- interrupts = <0 INTREQ__TMU_TMU_SUB 0>;
- tmu_name = "G3D";
- id = <2>;
- sensors = <2>; /* 0x02 */
- sensing_mode = "max";
- #include "exynos9810-tmu-sensor-conf.dtsi"
- };
- tmuctrl_3: ISP@10074000 {
- compatible = "samsung,exynos9810-tmu";
- reg = <0x0 0x10074000 0x700>;
- interrupts = <0 INTREQ__TMU_TMU_SUB 0>;
- tmu_name = "ISP";
- id = <3>;
- sensors = <4>; /* 0x04 */
- sensing_mode = "max";
- #include "exynos9810-tmu-sensor-conf.dtsi"
- };
- acpm_tmu {
- acpm-ipc-channel = <12>;
- };
- thermal-zones {
- big_thermal: BIG {
- zone_name = "BIG_THERMAL";
- polling-delay-passive = <50>;
- polling-delay = <1000>;
- thermal-sensors = <&tmuctrl_0>;
- governor = "power_allocator";
- sustainable-power = <0>;
- k_po = <0>;
- k_pu = <0>;
- k_i = <0>;
- i_max = <0>;
- integral_cutoff = <0>;
- trips {
- big_cold: big-cold {
- temperature = <20000>;
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- big_switch_on: big-switch-on {
- temperature = <55000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
- big_control_temp: big-control-temp {
- temperature = <83000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "passive";
- };
- big_alert0: big-alert0 {
- temperature = <95000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- big_alert1: big-alert1 {
- temperature = <100000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- big_alert2: big-alert2 {
- temperature = <105000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- big_alert3: big-alert3 {
- temperature = <110000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- big_hot: big-hot {
- temperature = <115000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "hot";
- };
- };
- cooling-maps {
- map0 {
- trip = <&big_control_temp>;
- cooling-device = <&cpufreq_domain1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- little_thermal: LITTLE {
- zone_name = "LITTLE_THERMAL";
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&tmuctrl_1>;
- trips {
- little_alert0: little-alert0 {
- temperature = <20000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_alert1: little-alert1 {
- temperature = <76000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_alert2: little-alert2 {
- temperature = <81000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_alert3: little-alert3 {
- temperature = <86000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_alert4: little-alert4 {
- temperature = <91000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_alert5: little-alert5 {
- temperature = <96000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_alert6: little-alert6 {
- temperature = <101000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- little_hot: little-hot {
- temperature = <115000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "hot";
- };
- };
- cooling-maps {
- map0 {
- trip = <&little_alert0>;
- /* Corresponds to 1794MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map1 {
- trip = <&little_alert1>;
- /* Corresponds to 1690MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map2 {
- trip = <&little_alert2>;
- /* Corresponds to 1456MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map3 {
- trip = <&little_alert3>;
- /* Corresponds to 1248MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map4 {
- trip = <&little_alert4>;
- /* Corresponds to 1053MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map5 {
- trip = <&little_alert5>;
- /* Corresponds to 455MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map6 {
- trip = <&little_alert6>;
- /* Corresponds to 455MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- map7 {
- trip = <&little_hot>;
- /* Corresponds to 455MHz at freq_table */
- cooling-device = <&cpufreq_domain0 0 0>;
- };
- };
- };
- gpu_thermal: G3D {
- zone_name = "G3D_THERMAL";
- polling-delay-passive = <100>;
- polling-delay = <0>;
- thermal-sensors = <&tmuctrl_2>;
- governor = "power_allocator";
- sustainable-power = <0>;
- k_po = <0>;
- k_pu = <0>;
- k_i = <0>;
- i_max = <0>;
- integral_cutoff = <0>;
- trips {
- gpu_cold: gpu-cold {
- temperature = <20000>;
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- gpu_switch_on: gpu-switch-on {
- temperature = <78000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "active";
- };
- gpu_control_temp: gpu-control-temp {
- temperature = <88000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "passive";
- };
- gpu_alert0: gpu-alert0 {
- temperature = <105000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- gpu_alert1: gpu-alert1 {
- temperature = <110000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- gpu_alert2: gpu-alert2 {
- temperature = <115000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- gpu_alert3: gpu-alert3 {
- temperature = <115000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- gpu_hot: gpu-hot {
- temperature = <115000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "hot";
- };
- };
- cooling-maps {
- map0 {
- trip = <&gpu_control_temp>;
- cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- isp_thermal: ISP {
- zone_name = "ISP_THERMAL";
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&tmuctrl_3>;
- trips {
- isp_alert0: isp-alert0 {
- temperature = <20000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_alert1: isp-alert1 {
- temperature = <91000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_alert2: isp-alert2 {
- temperature = <96000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_alert3: isp-alert3 {
- temperature = <101000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_alert4: isp-alert4 {
- temperature = <101000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_alert5: isp-alert5 {
- temperature = <101000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_alert6: isp-alert6 {
- temperature = <101000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "active";
- };
- isp_hot: isp-hot {
- temperature = <115000>; /* millicelsius */
- hysteresis = <5000>; /* millicelsius */
- type = "hot";
- };
- };
- cooling-maps {
- map0 {
- trip = <&isp_alert0>;
- /* Corresponds to No limit */
- cooling-device = <&fimc_is 0 0>;
- };
- map1 {
- trip = <&isp_alert1>;
- /* Corresponds to No limit */
- cooling-device = <&fimc_is 0 0>;
- };
- map2 {
- trip = <&isp_alert2>;
- /* Corresponds to 15fps at freq_table */
- cooling-device = <&fimc_is 0 0>;
- };
- map3 {
- trip = <&isp_alert3>;
- /* Corresponds to 5fps at freq_table */
- cooling-device = <&fimc_is 0 0>;
- };
- map4 {
- trip = <&isp_alert4>;
- /* Corresponds to 5fps at freq_table */
- cooling-device = <&fimc_is 0 0>;
- };
- map5 {
- trip = <&isp_alert5>;
- /* Corresponds to 5fps at freq_table */
- cooling-device = <&fimc_is 0 0>;
- };
- map6 {
- trip = <&isp_alert6>;
- /* Corresponds to 5fps at freq_table */
- cooling-device = <&fimc_is 0 0>;
- };
- map7 {
- trip = <&isp_hot>;
- /* Corresponds to HW trip */
- cooling-device = <&fimc_is 0 0>;
- };
- };
- };
- };
- smc_info: mcinfo@1B8300000 {
- compatible = "samsung,exynos-mcinfo";
- reg = <0x0 0x1B83004C 0x4>,
- <0x0 0x1B93004C 0x4>,
- <0x0 0x1BA3004C 0x4>,
- <0x0 0x1BB3004C 0x4>;
- bit_field = <20 4>;
- /* start bit, width */
- basecnt = <4>;
- irqcnt = <4>;
- interrupts = <0 INTREQ__DMC_TEMPERR_MIF0 0>,
- <0 INTREQ__DMC_TEMPERR_MIF1 0>,
- <0 INTREQ__DMC_TEMPERR_MIF2 0>,
- <0 INTREQ__DMC_TEMPERR_MIF3 0>;
- };
- fimc_is: fimc_is@16290000 {
- compatible = "samsung,exynos5-fimc-is";
- #pb-id-cells = <6>;
- reg = <0x0 0x162F0000 0x100>, /* CSIS-DMA */
- <0x0 0x16290000 0x10000>, /* FIMC-3AA0 */
- <0x0 0x162A0000 0x10000>, /* FIMC-3AA1 */
- <0x0 0x16430000 0x10000>, /* FIMC_ISPLP */
- <0x0 0x16630000 0x10000>, /* FIMC_ISPHQ */
- <0x0 0x16440000 0x4000>, /* MC_SCALER */
- <0x0 0x16510000 0x10000>, /* FIMC-VRA (Set A) */
- <0x0 0x16520000 0x10000>, /* FIMC-VRA (Set B) */
- <0x0 0x16880000 0x10000>, /* DCP */
- <0x0 0x163A0000 0x100>; /* PDP_STAT_DMA */
- interrupts = <0 INTREQ__TAAM_0 0>, /* 3AA0_0 */
- <0 INTREQ__TAAM_1 0>, /* 3AA0_1 */
- <0 INTREQ__TAA_0 0>, /* 3AA1_0 */
- <0 INTREQ__TAA_1 0>, /* 3AA1_1 */
- <0 INTREQ__ISPLP_0 0>, /* ISPLP_0 */
- <0 INTREQ__ISPLP_1 0>, /* ISPLP_1 */
- <0 INTREQ__BLK_ISPHQ_ISPHQ_INTREQ0 0>, /* ISPHQ_0 */
- <0 INTREQ__BLK_ISPHQ_ISPHQ_INTREQ1 0>, /* ISPHQ_1 */
- <0 INTREQ__MC_SCALER_0 0>, /* MC_SC_0 */
- <0 INTREQ__MC_SCALER_1 0>, /* MC_SC_1 */
- <0 INTREQ__VRA 0>, /* VRA_1 */
- <0 INTREQ_BLK_DCRD_DCP_IntReq_0 0>, /* DCP_0 */
- <0 INTREQ_BLK_DCRD_DCP_IntReq_1 0>; /* DCP_1 */
- pinctrl-names = "default","release";
- pinctrl-0 = <>;
- pinctrl-1 = <>;
- samsung,power-domain = <&pd_isplp>;
- clocks = <&clock GATE_IS_ISPHQ>,
- <&clock GATE_IS_ISPHQ_C2COM>,
- <&clock UMUX_CLKCMU_ISPHQ_BUS>,
- <&clock GATE_IS_ISPLP_MC_SCALER>,
- <&clock GATE_IS_ISPLP>,
- <&clock GATE_IS_ISPLP_VRA>,
- <&clock GATE_IS_ISPLP_GDC>,
- <&clock GATE_IS_ISPLP_C2>,
- <&clock UMUX_CLKCMU_ISPLP_BUS>,
- <&clock UMUX_CLKCMU_ISPLP_VRA>,
- <&clock UMUX_CLKCMU_ISPLP_GDC>,
- <&clock GATE_IS_ISPPRE_CSIS0>,
- <&clock GATE_IS_ISPPRE_CSIS1>,
- <&clock GATE_IS_ISPPRE_CSIS2>,
- <&clock GATE_IS_ISPPRE_CSIS3>,
- <&clock GATE_IS_ISPPRE_PDP_DMA>,
- <&clock GATE_IS_ISPPRE_3AA>,
- <&clock GATE_IS_ISPPRE_3AAM>,
- <&clock GATE_IS_ISPPRE_PDP_CORE0>,
- <&clock GATE_IS_ISPPRE_PDP_CORE1>,
- <&clock UMUX_CLKCMU_ISPPRE_BUS>,
- <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK3>;
- clock-names = "GATE_IS_ISPHQ",
- "GATE_IS_ISPHQ_C2COM",
- "UMUX_CLKCMU_ISPHQ_BUS",
- "GATE_IS_ISPLP_MC_SCALER",
- "GATE_IS_ISPLP",
- "GATE_IS_ISPLP_VRA",
- "GATE_IS_ISPLP_GDC",
- "GATE_IS_ISPLP_C2",
- "UMUX_CLKCMU_ISPLP_BUS",
- "UMUX_CLKCMU_ISPLP_VRA",
- "UMUX_CLKCMU_ISPLP_GDC",
- "GATE_IS_ISPPRE_CSIS0",
- "GATE_IS_ISPPRE_CSIS1",
- "GATE_IS_ISPPRE_CSIS2",
- "GATE_IS_ISPPRE_CSIS3",
- "GATE_IS_ISPPRE_PDP_DMA",
- "GATE_IS_ISPPRE_3AA",
- "GATE_IS_ISPPRE_3AAM",
- "GATE_IS_ISPPRE_PDP_CORE0",
- "GATE_IS_ISPPRE_PDP_CORE1",
- "UMUX_CLKCMU_ISPPRE_BUS",
- "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
- "MUX_CIS_CLK0",
- "MUX_CIS_CLK1",
- "MUX_CIS_CLK2",
- "MUX_CIS_CLK3";
- status = "ok";
- iommus = <&sysmmu_isppre>, <&sysmmu_isplp0>, <&sysmmu_isplp1>, <&sysmmu_isphq>;
- #cooling-cells = <2>; /* min followed by max */
- ewf-index = <EWF_CMU_BUSC>;
- };
- camerapp_gdc: gdc@16530000 {
- compatible = "samsung,exynos5-camerapp-gdc";
- #pb-id-cells = <6>;
- reg = <0x0 0x16530000 0x10000>; /* GDC */
- interrupts = <0 INTREQ__GDC 0>; /* GDC */
- pinctrl-names = "default","release";
- pinctrl-0 = <>;
- pinctrl-1 = <>;
- samsung,power-domain = <&pd_isplp>;
- clocks = <&clock GATE_IS_ISPLP_GDC>,
- <&clock UMUX_CLKCMU_ISPLP_GDC>;
- clock-names = "gate",
- "gate2";
- status = "ok";
- iommus = <&sysmmu_isplp0>;
- #cooling-cells = <2>; /* min followed by max */
- };
- mipi_phy_csis0_m4s4_top: dphy_m4s4_csis0@0x16210500 {
- /* DCPHY 4.5 Gbps 4lane */
- compatible = "samsung,mipi-phy-m4s4-top";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x70C>; /* PMU address offset */
- reg = <0x0 0x16210500 0x4>; /* SYSREG address for reset */
- reset = <0>; /* reset bit */
- owner = <1>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
- mipi_phy_csis2_m4s4_mod: dphy_m4s4_csis2@0x16210500 {
- /* DCPHY 4.5 Gbps 4lane */
- compatible = "samsung,mipi-phy-m4s4-mod";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x710>; /* PMU address offset */
- reset = <1>; /* reset bit */
- owner = <1>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
- mipi_phy_csis1_m0s4s2: dphy_m0s4s2_csis1@0x16210500 {
- /* DPHY 2.5 Gbps 4lane */
- compatible = "samsung,mipi-phy-m1s2s2";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x730>; /* PMU address offset */
- reset = <2>; /* reset bit */
- owner = <1>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
- mipi_phy_csis3_m0s4s2: dphy_m0s4s2_csis3@0x16210500 {
- /* DPHY 2.5 Gbps 2lane */
- compatible = "samsung,mipi-phy-m1s2s2";
- samsung,pmu-syscon = <&pmu_system_controller>;
- isolation = <0x730>; /* PMU address offset */
- reset = <3>; /* reset bit */
- owner = <1>; /* 0: DSI, 1: CSI */
- #phy-cells = <1>;
- };
- fimc_is_sensor0: fimc_is_sensor@16230000 {
- /* REAR/CSIS0 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x16230000 0x1000>, /* MIPI-CSI0 */
- <0x0 0x16160000 0x10000>, /* PHY: TOP_M4S4 */
- <0x0 0x162B0000 0x100>, /* VC0 DMA0 */
- <0x0 0x162B0400 0x100>, /* VC0 DMA0 COMMON */
- <0x0 0x162B0100 0x100>, /* VC1 DMA0 */
- <0x0 0x162B0400 0x100>, /* VC1 DMA0 COMMON */
- <0x0 0x162B0200 0x100>, /* VC2 DMA0 */
- <0x0 0x162B0400 0x100>, /* VC2 DMA0 COMMON */
- <0x0 0x162B0300 0x100>, /* VC3 DMA0 */
- <0x0 0x162B0400 0x100>, /* VC3 DMA0 COMMON */
- <0x0 0x162B0000 0x100>, /* VC0 DMA0 */
- <0x0 0x162B0400 0x100>, /* VC0 DMA0 COMMON */
- <0x0 0x16380000 0x100>, /* VC0 DMA4 */
- <0x0 0x16380400 0x100>, /* VC0 DMA4 COMMON */
- <0x0 0x16380100 0x100>, /* VC1 DMA4 */
- <0x0 0x16380400 0x100>, /* VC1 DMA4 COMMON */
- <0x0 0x16380200 0x100>, /* NOTHING */
- <0x0 0x16380400 0x100>; /* NOTHING */
- interrupts = <0 INTREQ__CSIS0 0>, /* MIPI-CSI0 */
- <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC0 DMA0 */
- <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC1 DMA0 */
- <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC2 DMA0 */
- <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC3 DMA0 */
- <0 INTREQ__CSIS0_PDP_DMA 0>, /* VC0 DMA0 */
- <0 INTREQ__PDP0_STAT_DMA 0>, /* VC0 DMA4 */
- <0 INTREQ__PDP0_STAT_DMA 0>, /* VC1 DMA4 */
- <0 INTREQ__PDP0_STAT_DMA 0>; /* NOTHING */
- samsung,power-domain = <&pd_isppre>;
- phys = <&mipi_phy_csis0_m4s4_top 0>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
- <&clock GATE_IS_ISPPRE_CSIS0>,
- <&clock GATE_IS_ISPPRE_CSIS1>,
- <&clock GATE_IS_ISPPRE_CSIS2>,
- <&clock GATE_IS_ISPPRE_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
- "MUX_CIS_CLK0",
- "MUX_CIS_CLK1",
- "MUX_CIS_CLK2",
- "MUX_CIS_CLK3",
- "GATE_IS_ISPPRE_CSIS0",
- "GATE_IS_ISPPRE_CSIS1",
- "GATE_IS_ISPPRE_CSIS2",
- "GATE_IS_ISPPRE_CSIS3";
- iommus = <&sysmmu_isppre>;
- };
- fimc_is_sensor1: fimc_is_sensor@16240000 {
- /* FRONT/CSIS0 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x16240000 0x1000>, /* MIPI-CSI0 */
- <0x0 0x16180000 0x10000>, /* PHY: MODULE_M0S4S2(S4) */
- <0x0 0x162C0000 0x100>, /* VC0 DMA1 */
- <0x0 0x162C0400 0x100>, /* VC0 DMA1 COMMON */
- <0x0 0x162C0100 0x100>, /* VC1 DMA1 */
- <0x0 0x162C0400 0x100>, /* VC1 DMA1 COMMON */
- <0x0 0x162C0200 0x100>, /* VC2 DMA1 */
- <0x0 0x162C0400 0x100>, /* VC2 DMA1 COMMON */
- <0x0 0x162C0300 0x100>, /* VC3 DMA1 */
- <0x0 0x162C0400 0x100>; /* VC3 DMA1 COMMON */
- interrupts = <0 INTREQ__CSIS1 0>, /* MIPI-CSI1 */
- <0 INTREQ__CSIS1_PDP_DMA 0>, /* VC0 DMA1 */
- <0 INTREQ__CSIS1_PDP_DMA 0>, /* VC1 DMA1 */
- <0 INTREQ__CSIS1_PDP_DMA 0>, /* VC2 DMA1 */
- <0 INTREQ__CSIS1_PDP_DMA 0>; /* VC3 DMA1 */
- samsung,power-domain = <&pd_isppre>;
- phys = <&mipi_phy_csis1_m0s4s2 0>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
- <&clock GATE_IS_ISPPRE_CSIS0>,
- <&clock GATE_IS_ISPPRE_CSIS1>,
- <&clock GATE_IS_ISPPRE_CSIS2>,
- <&clock GATE_IS_ISPPRE_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
- "MUX_CIS_CLK0",
- "MUX_CIS_CLK1",
- "MUX_CIS_CLK2",
- "MUX_CIS_CLK3",
- "GATE_IS_ISPPRE_CSIS0",
- "GATE_IS_ISPPRE_CSIS1",
- "GATE_IS_ISPPRE_CSIS2",
- "GATE_IS_ISPPRE_CSIS3";
- iommus = <&sysmmu_isppre>;
- };
- fimc_is_sensor2: fimc_is_sensor@16250000 {
- /* REAR_SUB/CSIS2 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x16250000 0x1000>, /* MIPI-CSI0 */
- <0x0 0x16170000 0x10000>, /* PHY: MODULE_M4S4*/
- <0x0 0x162D0000 0x100>, /* VC0 DMA2 */
- <0x0 0x162D0400 0x100>, /* VC0 DMA2 COMMON */
- <0x0 0x162D0100 0x100>, /* VC1 DMA2 */
- <0x0 0x162D0400 0x100>, /* VC1 DMA2 COMMON */
- <0x0 0x162D0200 0x100>, /* VC2 DMA2 */
- <0x0 0x162D0400 0x100>, /* VC2 DMA2 COMMON */
- <0x0 0x162D0300 0x100>, /* VC3 DMA2 */
- <0x0 0x162D0400 0x100>; /* VC3 DMA2 COMMON */
- interrupts = <0 INTREQ__CSIS2 0>, /* MIPI-CSI2 */
- <0 INTREQ__CSIS2_PDP_DMA 0>, /* VC0 DMA2 */
- <0 INTREQ__CSIS2_PDP_DMA 0>, /* VC1 DMA2 */
- <0 INTREQ__CSIS2_PDP_DMA 0>, /* VC2 DMA2 */
- <0 INTREQ__CSIS2_PDP_DMA 0>; /* VC3 DMA2 */
- samsung,power-domain = <&pd_isppre>;
- phys = <&mipi_phy_csis2_m4s4_mod 0>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
- <&clock GATE_IS_ISPPRE_CSIS0>,
- <&clock GATE_IS_ISPPRE_CSIS1>,
- <&clock GATE_IS_ISPPRE_CSIS2>,
- <&clock GATE_IS_ISPPRE_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
- "MUX_CIS_CLK0",
- "MUX_CIS_CLK1",
- "MUX_CIS_CLK2",
- "MUX_CIS_CLK3",
- "GATE_IS_ISPPRE_CSIS0",
- "GATE_IS_ISPPRE_CSIS1",
- "GATE_IS_ISPPRE_CSIS2",
- "GATE_IS_ISPPRE_CSIS3";
- iommus = <&sysmmu_isppre>;
- };
- fimc_is_sensor3: fimc_is_sensor@16260000 {
- /* IRIS/CSIS3 */
- compatible = "samsung,exynos5-fimc-is-sensor";
- #pb-id-cells = <4>;
- reg = <0x0 0x16260000 0x1000>, /* MIPI-CSI0 */
- <0x0 0x16190000 0x10000>, /* PHY: MODULE_M0S4S2(S2) */
- <0x0 0x162E0000 0x100>, /* VC0 DMA3 */
- <0x0 0x162E0400 0x100>, /* VC0 DMA3 COMMON */
- <0x0 0x162E0100 0x100>, /* VC1 DMA3 */
- <0x0 0x162E0400 0x100>, /* VC1 DMA3 COMMON */
- <0x0 0x162E0200 0x100>, /* VC2 DMA3 */
- <0x0 0x162E0400 0x100>, /* VC2 DMA3 COMMON */
- <0x0 0x162E0300 0x100>, /* VC3 DMA3 */
- <0x0 0x162E0400 0x100>; /* VC3 DMA3 COMMON */
- interrupts = <0 INTREQ__CSIS3 0>, /* MIPI-CSI3 */
- <0 INTREQ__CSIS3_PDP_DMA 0>, /* VC0 DMA3 */
- <0 INTREQ__CSIS3_PDP_DMA 0>, /* VC1 DMA3 */
- <0 INTREQ__CSIS3_PDP_DMA 0>, /* VC2 DMA3 */
- <0 INTREQ__CSIS3_PDP_DMA 0>; /* VC3 DMA3 */
- samsung,power-domain = <&pd_isppre>;
- phys = <&mipi_phy_csis3_m0s4s2 0>;
- phy-names = "csis_dphy";
- clocks = <&clock CIS_CLK0>,
- <&clock CIS_CLK1>,
- <&clock CIS_CLK2>,
- <&clock CIS_CLK3>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK0>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK1>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK2>,
- <&clock GATE_DFTMUX_TOP_CIS_CLK3>,
- <&clock GATE_IS_ISPPRE_CSIS0>,
- <&clock GATE_IS_ISPPRE_CSIS1>,
- <&clock GATE_IS_ISPPRE_CSIS2>,
- <&clock GATE_IS_ISPPRE_CSIS3>;
- clock-names = "CIS_CLK0",
- "CIS_CLK1",
- "CIS_CLK2",
- "CIS_CLK3",
- "MUX_CIS_CLK0",
- "MUX_CIS_CLK1",
- "MUX_CIS_CLK2",
- "MUX_CIS_CLK3",
- "GATE_IS_ISPPRE_CSIS0",
- "GATE_IS_ISPPRE_CSIS1",
- "GATE_IS_ISPPRE_CSIS2",
- "GATE_IS_ISPPRE_CSIS3";
- iommus = <&sysmmu_isppre>;
- };
- fimc_is_pdp0: fimc_is_pdp@16270000 {
- /* PDP CORE0 */
- compatible = "samsung,exynos5-fimc-is-pdp";
- reg = <0x0 0x16270000 0x2000>; /* PDP CORE0 */
- interrupts = <0 INTREQ__PDP_CORE0 0>;
- id = <0>;
- };
- fimc_is_pdp1: fimc_is_pdp@16280000 {
- /* PDP CORE1 */
- compatible = "samsung,exynos5-fimc-is-pdp";
- interrupts = <0 INTREQ__PDP_CORE1 0>;
- reg = <0x0 0x16280000 0x2000>; /* PDP CORE1 */
- id = <1>;
- };
- sysreg_fsys1_controller: sysreg-controller@11410000 {
- compatible = "samsung,exynos8895-sysreg", "syscon";
- reg = <0x0 0x11410000 0x1200>;
- };
- sysmmu_pcie: sysmmu@11420000 {
- compatible = "samsung,pcie-sysmmu";
- reg = <0x0 0x11420000 0x9000>;
- interrupts = <0 INTREQ__SYSMMU_FSYS1 0>;
- clock-names = "aclk";
- clocks = <&clock GATE_SYSMMU_FSYS1>;
- port-name = "PCIe";
- #iommu-cells = <0>;
- use-tlb-pinning = "true";
- };
- pcie0@116A0000 {
- compatible = "samsung,exynos-pcie";
- gpios = <&gpf2 2 0x1 /* PERST */>;
- reg = <0x0 0x116A0000 0x1000 /* elbi base */
- 0x0 0x116D0000 0x1000 /* phy base */
- 0x0 0x11411044 0x10 /* sysreg base */
- 0x0 0x11700000 0x1000 /* DBI base */
- 0x0 0x116C0000 0x1FC /* phy pcs base */
- 0x0 0x127FE000 0x2000 /* configuration space */
- 0x0 0x11680000 0x1000>; /* I/A space */
- reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config", "ia";
- interrupts = <0 INTREQ__PCIE_WIFI0 0>; /* IRQ_PULSE */
- samsung,syscon-phandle = <&pmu_system_controller>;
- samsung,sysreg-phandle = <&sysreg_fsys1_controller>;
- clocks = <&clock GATE_PCIE_GEN2_MSTR>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_clkreq &pcie0_perst &pcie_wake>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- /* non-prefetchable memory */
- ranges = <0x82000000 0 0x11800000 0 0x11800000 0 0xFF0000>;
- /* ranges = <0x82000000 0 0x20000000 0 0x20000000 0 0x20000000>; */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 253 0x4>;
- ip-ver = <0x981000>;
- num-lanes = <1>;
- ch-num = <0>;
- pcie-clk-num = <0>;
- phy-clk-num = <0>;
- pcie-pm-qos-int = <0>;
- use-cache-coherency = "false";
- use-msi = "false";
- use-sicd = "true";
- use-sysmmu = "false";
- use-ia = "true";
- max-link-speed = <LINK_SPEED_GEN2>;
- status = "disabled";
- };
- pcie1@116B0000 {
- compatible = "samsung,exynos-pcie";
- gpios = <&gpf2 5 0x1 /* PERST */>;
- reg = <0x0 0x116B0000 0x1000 /* elbi base */
- 0x0 0x116F0000 0x1000 /* phy base */
- 0x0 0x11411054 0x10 /* sysreg base */
- 0x0 0x11710000 0x1000 /* DBI base */
- 0x0 0x116E0000 0x1FC /* phy pcs base */
- 0x0 0x137FE000 0x2000>; /* configuration space */
- reg-names = "elbi", "phy", "sysreg", "dbi", "pcs", "config";
- interrupts = <0 INTREQ__PCIE_WIFI1 0>; /* IRQ_PULSE */
- samsung,syscon-phandle = <&pmu_system_controller>;
- clocks = <&clock GATE_PCIE_GEN3_MSTR>;
- pinctrl-names = "default";
- pinctrl-0 = <&pcie1_clkreq &pcie1_perst>;
- #address-cells = <3>;
- #size-cells = <2>;
- device_type = "pci";
- /* non-prefetchable memory */
- ranges = <0x82000000 0 0x12800000 0 0x12800000 0 0xFF0000>;
- /* ranges = <0x82000000 0 0x40000000 0 0x40000000 0 0x20000000>; */
- #interrupt-cells = <1>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 254 0x4>;
- ip-ver = <0x981000>;
- num-lanes = <1>;
- ch-num = <1>;
- pcie-clk-num = <0>;
- phy-clk-num = <0>;
- pcie-pm-qos-int = <0>;
- use-cache-coherency = "false";
- use-msi = "false";
- use-sicd = "true";
- use-sysmmu = "false";
- max-link-speed = <LINK_SPEED_GEN3>;
- status = "disabled";
- };
- mailbox_vts: mailbox@0x141B0000 {
- compatible = "samsung,mailbox-asoc";
- reg = <0x0 0x141B0000 0x10000>;
- reg-names = "sfr";
- interrupts = <0 INTREQ__MAILBOX_VTS2AP 0>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
- vts: vts@0x13870000 {
- compatible = "samsung,vts";
- reg = <0x0 0x13810000 0x1000>, <0x0 0x13B00000 0x10010>, <0x0 0x13870000 0x8>, <0x0 0x13900000 0x67070>,
- <0x0 0x138F0000 0x50>;
- reg-names = "sfr", "baaw", "dmic", "sram", "gpr";
- pinctrl-names = "dmic_default", "amic_default", "idle";
- pinctrl-0 = <&dmic_bus_clk &dmic_pdm>;
- pinctrl-1 = <&amic_bus_clk &amic_pdm>;
- pinctrl-2 = <&mic_bus_clk_idle &dmic_pdm_idle &amic_pdm_idle>;
- samsung,power-domain = <&pd_vts>;
- clocks = <&clock DOUT_CLK_VTS_DMIC>,
- <&clock DOUT_CLK_VTS_DMICIF>, <&clock DOUT_CLK_VTS_DMIC_DIV2>;
- clock-names = "dmic", "dmic_if", "dmic_sync";
- mailbox = <&mailbox_vts>;
- #sound-dai-cells = <1>;
- interrupt-parent = <&mailbox_vts>;
- interrupts = <16>, <17>, <18>, <19>, <20>, <21>, <22>, <23>, <24>, <25>;
- interrupt-names = "error", "boot_completed", "ipc_received", "voice_triggered",
- "trigger_period_elapsed", "record_period_elapsed",
- "debuglog_bufzero", "debuglog_bufone",
- "audio_dump", "log_dump";
- };
- vts_dma0: vts_dma0 {
- compatible = "samsung,vts-dma";
- vts = <&vts>;
- id = <0>;
- type = "vts-trigger";
- };
- vts_dma1: vts_dma1 {
- compatible = "samsung,vts-dma";
- vts = <&vts>;
- id = <1>;
- type = "vts-record";
- };
- cmu_ewf {
- compatible = "samsung,exynos-cmuewf";
- #address-cells = <2>;
- #size-cells = <1>;
- reg = <0x0 0x1A240000 0x1000>;
- };
- };
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