DMA

module processor(mode,databus,address,toaddress,write,read,clk); //hldreq,hldack,count,int

inout [31:0] databus;

output reg [31:0] address;
output reg [31:0] toaddress;
input wire [1:0] mode;      //able to send and receive data to/from RAM or IO devices directly if it wants to
output reg write;
output reg read;
//input wire int;           //interrupt signal signaling that dma has finished
//input wire hldreq;        //hold request
//output reg hldack;        //hold acknowledge for dma
//output reg [9:0] count;       //number of bytes to be transferred by dma (up to 1024 Byte)
input clk;
reg [31:0] register [0:7];
reg [31:0] Dout;

// inout ports are wires, so we can't change its value in a block
// we change the value of Dout, and the databus is assigned to be equal to Dout
assign databus=(write)? Dout:32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;

initial
begin
register[0]=32'b0;
register[1]=32'b0;
register[7]=32'b00000000000000000000000000001111; //'h0f
end

always @(posedge clk)
 case(mode)
    2'b00: // read 5 words (5*32=160)  from io1 to memory location 5    //assume mode=2'b00 equals hldreq=1
          begin
      //hldack<=1'b1;
          address<=32'b00000000000000000000000000000001;    //assume dma req from i01
          read<=1'b1;
          write<=1'b0;
      //count <= 9'b010100000;              //160 bytes
      toaddress <=32'b00000000000000000000000000000110;
      //processor doing some stuff
      end

    2'b01: //read io1
        begin
          address<=32'b00000000000000000000000000000001; // memory location of io1
          read<=1'b1;
          write<=1'b0;
      //hldack<=1'b0;
          register[6]<=databus; //read buffer of io1 and store in reg6 -> reg6 = 07 (line 103 & 120)
         end
     2'b10: //write in io2
        begin
          address<=32'b00000000000000000000000000000010; // memory location of io2
          write<=1'b1;
          read<=1'b0;
      //hldack<=1'b0;
          Dout<=register[7]; // make io2 buffer = reg7 = 'h0f
         end
     2'b11: //read memory address 5
        begin
          address<=32'b00000000000000000000000000000101;
          read<=1'b1;
          write<=1'b0;
      //hldack<=1'b0;
          register[7]=databus; // -> reg7= 5
         end
    default:register[0]<=1;
 endcase


endmodule


module ram(Address,toaddress,Memread,Memwrite,databus,clk);

input[31:0] Address;
input[31:0] toaddress;
input Memread;
input Memwrite;
input clk;

inout [31:0] databus;
reg [31:0] Dout;
assign databus=(Memread && Address>3) ? Dout:32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;

reg[31:0]mem[0:50];

initial begin
mem[4]=32'b00000000000000000000000000000100;
mem[5]=32'b00000000000000000000000000000101;
end

always@(posedge clk)
begin
    if(Address>3)
    begin
    if(Memread)
    begin
    Dout <= mem[Address];
    end
    if (Memwrite)
    begin
    mem[Address] <= databus;
    end
    end
    else if(toaddress>3)
    begin
    if(Memwrite)
    begin
    Dout <= mem[toaddress];
    end
    if (Memread)
    begin
    mem[toaddress] <= databus;
    end
    end

end
endmodule



module io1(address,toaddress,write,read,databus);//, dmareq1, dmaack1); //address=1 (memory location of io1)

input [31:0] address;
input[31:0] toaddress;
input write;
input read;
//output reg dmareq1;
//input wire dmaack1;
inout [31:0] databus;
reg [31:0] Dout;

assign databus=(read && address==1)? Dout:32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;

reg [31:0] buffer;
initial begin
buffer=32'b00000000000000000000000000000111; //'h07
end

always@(address,toaddress)
begin
if (address==1) //&& mode!=2'b00)
begin
if (write)
begin
buffer<=databus;
end
if (read)
begin
Dout<=buffer;
end
end
else if(toaddress==1)
begin
if (read)
begin
buffer<=databus;
end
if (write)
begin
Dout<=buffer;
end
end
end

endmodule


module io2(address,toaddress,write,read,databus);//, dmareq2, dmaack2); //address=2 (memory location of io2)
input [31:0] address;
input[31:0] toaddress;
input write;
input read;
//output reg dmareq2;
//input wire dmaack2;
inout [31:0] databus;
reg [31:0] Dout;

assign databus=(read && address==2)? Dout:32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;

reg [31:0] buffer;
initial begin
buffer=32'b00000000000000000000000000011111; //'h1F
end

always@(address)
begin
if (address==2)// && mode!=2'b00)
begin
if (write)
begin
buffer<=databus;
end
if (read)
begin
Dout<=buffer;
end
end

else if(toaddress==2)
begin
if (read)
begin
buffer<=databus;
end
if (write)
begin
Dout<=buffer;
end
end
end
endmodule

/*module dma (address, write, read, databus, dmareq, dmaack, hldack, int, count);

inout [31:0] databus;

input [31:0] address;
input write;
input read;
input [1:0] dmareq;
output reg [1:0] dmaack;
//output reg hldreq;        //hold request for processor
input wire hldack;      //hold acknowledge
output reg int;         //interrupt signal signaling that dma has finished for processor
input [9:0] count;      //number of bytes to be transferred by dma
reg [31:0] Dout;

assign databus=()? Dout:32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz;
initial begin
buffer=32'b00000000000000000000000000011111; //'h1F
end

always@(address,dmareq)
begin
    //if(dmareq == 2'b01)//io1 requested the dma
    //begin
        //mode=2'b00; //equals hldreq1=1
        dmaack == 2'b01;
        if (write)
        begin
        buffer<=databus;
        end
        if (read)
        begin
        Dout<=buffer;
        end
    //end
    //if(dmareq == 2'b10)//io2 requested the dma
    //begin
        //mode=2'b00; //equals hldreq1=1
        dmaack == 2'b10;
        if (write)
        begin
        buffer<=databus;
        end
        if (read)
        begin
        Dout<=buffer;
        end
    end
end

endmodule

*/

module tbb();
reg clock1;
initial
begin
assign clock1=0;
end
always
begin
#5;
assign clock1=~clock1;
#5;
end
wire write,read;
wire [31:0] databus;
wire [31:0]address;
wire [31:0]toaddress;

io1 io(address,toaddress,write,read,databus);
io2 ioo(address,toaddress,write,read,databus);

ram ramm(address,toaddress,read,write,databus,clock1);

processor pro(2'b00,databus,address,toaddress,write,read,clock1);


endmodule
/*
     2'b100: // read 5 words from io1 to memory location 10 //assume mode=2'b100 equals hldreq1=
        begin
      hldack<=1'b1;
          address<=32'b00000000000000000000000000000101;
          read<=1'b1;
          write<=1'b0;
          register[7]=databus; // -> reg7= 5
         end */