Exams/2014 qfsm

module top_module (
    input clk,
    input reset,   // Synchronous reset
    input s,
    input w,
    output z
);
    parameter A=1'd0, B=1'd1;

    reg [1:0] w_count, cycle_count;
    reg [3:0] current_state, next_state;

    // next state logic
    always @(*) begin
        case (current_state)
            A  : next_state = s ? B : A;
            B  : next_state = B;
        endcase
    end

    // current state logic
    always @(posedge clk) begin
        if (reset) begin
            current_state <= A;
        end else begin
        	current_state <= next_state;
        end
    end

    // tracks w frequency and clock cycle
    always @(posedge clk) begin
        if (reset) begin
        	cycle_count <= 1'd0;
            w_count <= 1'd0;
        end else begin
            if (current_state == B) begin
                if (cycle_count == 2'd3) begin
                    cycle_count <= 1'd0;
                    w_count <= 1'd0;
                end else begin
                    cycle_count <= cycle_count + 1'd1;
                    w_count <= w_count + w;
                end
            end
        end
    end

    assign z = (cycle_count == 2'd3) * (w_count == 2'd2);
endmodule