/* verilator lint_off UNUSED */
module MIPS32SOC (
    input clk, // Clock signal
    input resetIn,  // Reset signal
    input [7:0] keypadIn,
    output invalidOpcode,
    output invalidPC,
    output invalidAddr
);

    `ifdef SYNTHESIS
        assign reset = ~resetIn;
        assign keypad = ~keypadIn;
    `else
        assign reset = resetIn;
        assign keypad = keypadIn;
    `endif

    wire [31:0] inst /*verilator public*/;
    reg  [31:0] nextPC; // Should be 'reg' because it used in a always block
    reg  [31:0] PC /*verilator public*/; // The PC (Program Counter) register
    wire [31:0] pcPlus4;
    wire [5:0] func;
    wire [4:0] rd /*verilator public*/;
    wire [4:0] rt /*verilator public*/;
    wire [4:0] rs /*verilator public*/;
    wire [4:0] sa;
    wire [5:0] opcode;
    wire [1:0] aluSrc;
    wire aluSrc1;
    wire rfWriteEnable; // Register File Write Enable
    wire [1:0] rfWriteAddrSel; // Register File Write Address Select
    wire [1:0] rfWriteDataSel; // Register File Write Data Select
    reg [4:0] rfWriteAddr; // Register File Write Address
    reg  [31:0] rfWriteData /*verilator public*/; // Register File Write Data
    wire [31:0] rfData1 /*verilator public*/;
    wire [31:0] rfData2 /*verilator public*/;
    wire [31:0] imm32;
    wire [15:0] imm16;
    wire [7:0] memAddr;
    wire memWrite;
    wire memRead;
    wire [31:0] memData;
    wire [3:0] aluFunc /*verilator public*/;
    wire [31:0] aluOperand1;
    reg [31:0] aluOperand2;
    wire [31:0] aluResult /*verilator public*/;
    wire [31:0] branchTargetAddr;
    wire [31:0] jmpTarget32;
    wire isJmp /*verilator public*/;
    wire isZero /*verilator public*/;
    wire bitXtend;
    // wire invalidOpcode /*verilator public*/;
    // wire invalidPC /*verilator public*/;
    // wire invalidAddr /*verilator public*/;
    wire [10:0] physPC;
    wire [31:0] physMemAdd;
    wire isUsingMemory;
    wire [2:0] memEnable;
    wire [1:0] memoryBank;
    wire [3:0] encMemoryWrite;
    wire [1:0] memoryDataSize;
    wire memoryBitExtend;
    wire [31:0] memWriteData;
    reg [31:0] readData /*verilator public*/;
    wire [31:0] lui;
    wire [31:0] vgaReadData;
    wire [31:0] dataMemReadData;
    wire [31:0] IOReadData;
    wire [2:0] red;
    wire [2:0] green;
    wire [1:0] blue;
    wire hsync;
    wire vsync;
    wire [31:0] decodedReadData;
    wire [31:0] encodedWriteData;
    wire [2:0] branchCU;
    wire branchTaken;
    wire jal;
    wire jr;
    wire fClk;
    wire vClk;
    wire sClk;
    wire [31:0] mCounter /*verilator public*/;
    reg [31:0] nextPC2;
    wire [7:0] keypad;
    wire reset;

    assign func = inst[5:0];
    assign rd = inst[15:11];
    assign rt = inst[20:16];
    assign rs = inst[25:21];
    assign sa = inst[10:6];
    assign opcode = inst[31:26];
    assign imm16 = inst[15:0];
    assign memAddr = aluResult[9:2];
    assign lui = {imm16, 16'd0};

    assign pcPlus4 = PC + 32'd4;
    assign jmpTarget32 = {pcPlus4[31:28], inst[25:0], 2'b00};
    assign branchTargetAddr = pcPlus4 + {imm32[29:0], 2'b00};

    //assign rfWriteAddr = rfWriteAddrSel? rd : rt; // MUX
    //assign aluOperand2 = aluSrc? imm32 : rfData2; // MUX
    //assign rfWriteData = rfWriteDataSel[0]? memData : aluResult; // MUX
    assign aluOperand1 = aluSrc1 ? rfData2 : rfData1; //MUX

    //rfWirteAddr MUX
    always @ (*) begin
        case (rfWriteAddrSel)
            2'b00:
                rfWriteAddr = rt;
            2'b01:
                rfWriteAddr = rd;
            2'b10:
                rfWriteAddr = 5'd31;
            default:
                rfWriteAddr = 5'dx;
        endcase
    end

    //ALUOperand2 MUX
    always @ (*) begin
        case (aluSrc)
            2'd0:
                aluOperand2 = rfData2;
            2'd1:
                aluOperand2 = imm32;
            2'd2:
                aluOperand2 = {27'd0, sa};
            default:
                aluOperand2 = 32'd0;
        endcase
    end

    //rfWriteData MUX
    always @ (*) begin
        case (rfWriteDataSel)
            2'b00:
                rfWriteData = aluResult;
            2'b01:
                rfWriteData = decodedReadData;
            2'b10:
                rfWriteData = lui;
            2'b11:
                rfWriteData = pcPlus4;
            default:
                rfWriteData = 32'd0;
        endcase
    end

    //memBank MUX
    always @ (*) begin
        case (memoryBank)
            2'd0:
                readData = dataMemReadData;
            2'd1:
                readData = vgaReadData;
            2'd2:
                readData = IOReadData;
            default:
                readData = 32'd0;
        endcase
    end

    //

    // Next PC value
    always @ (*) begin
        if(jr)
            nextPC = rfData1;
        else begin
            if(isJmp || jal)
                nextPC = jmpTarget32;
            else begin
                if(branchTaken)
                    nextPC = branchTargetAddr;
                else begin
                    if(invalidAddr)
                        nextPC = nextPC;
                    else
                        nextPC = pcPlus4;
                end
            end
        end
    end

    always @ (*) begin
        if(reset)
            nextPC2 = 32'h400000;
        else
            nextPC2 = nextPC;
    end
    // always @ (*) begin
    //     if (isJmp)
    //         nextPC = jmpTarget32;
    //     else begin
    //         if (branchTaken)
    //             nextPC = branchTargetAddr;
    //         else
    //             if(invalidAddr)
    //                 nextPC = nextPC;
    //             else
    //                 nextPC = pcPlus4;
    //     end
    // end

    // PC
    always @ (posedge sClk) begin
        if (reset)
            PC <= 32'h400000;
        else
            PC <= nextPC;
    end

    // Instruction Memory
    // AsyncROM instMem (
    //     .addr( physPC[9:0] ),
    //     .en( 1'b1 ),
    //     .dout( inst )
    // );

    InstMem instMem(
        .clk ( sClk ),
        .en ( 1'b1 ),
        .addr ( physPC ),
        .rdata ( inst )
    );

    // Data Memory
    // RAMDualPort dataMem (
    //     .A( physMemAdd ),
    //     .D_in( rfData2 ),
    //     .str( memWrite ),
    //     .C( clk ),
    //     .ld ( memRead ),
    //     .D ( memData )
    // );

    //Register File
    RegisterFile regFile (
        .ra1( rs ),
        .ra2( rt ),
        .wa( rfWriteAddr ),
        .wd( rfWriteData ),
        .we( rfWriteEnable ),
        .clk( sClk ),
        .rd1( rfData1 ),
        .rd2( rfData2 )
    );

  // ALU
  ALU ALU_i11 (
    .a( aluOperand1 ),
    .b( aluOperand2 ),
    .func( aluFunc ),
    .res( aluResult ),
    .isZero( isZero )
  );

  // BitExtender
  BitExtender BitExtender_i12 (
    .x( bitXtend ),
    .in( imm16 ),
    .out( imm32 )
  );

  // Control Unit
  ControlUnit ControlUnit_i13 (
    .opc( opcode ),
    .func( func ),
    .rt ( rt ),
    .rst ( reset ),
    .jmp( isJmp ),
    .rfWriteDataSel( rfWriteDataSel ),
    .rfWriteAddrSel( rfWriteAddrSel ),
    .rfWriteEnable( rfWriteEnable ),
    .memWrite( memWrite ),
    .memRead( memRead ),
    .aluSrc( aluSrc ),
    .aluSrc1( aluSrc1 ),
    .aluFunc( aluFunc ),
    .bitXtend( bitXtend ),
    .invOpcode( invalidOpcode ),
    .isUsingMem ( isUsingMemory ),
    .memDataSize( memoryDataSize ),
    .memBitExt( memoryBitExtend ),
    .branch ( branchCU ),
    .jal ( jal ),
    .jr ( jr )
  );

  PCDecoder Pdecoder(
      .virtualPC( nextPC2 ),
      .physicalPC( physPC ),
      .invalidPC( invalidPC )
  );

  MemDecoder mDecoder(
      .virtualAddress( aluResult ),
      .memWrite( memWrite ),
      .memRead( memRead ),
      .memEn( memEnable ),
      .memBank( memoryBank ),
      .physicalAddress( physMemAdd ),
      .invalidAddress ( invalidAddr )
  );

    DataMem dataMem(
        .clk( clk ),
        .en( memEnable[0] ),
        .memWrite( encMemoryWrite ),
        .addr( physMemAdd[12:2] ),
        .wdata( encodedWriteData ),
        .rdata( dataMemReadData )
    );

    MemReadDataDecoder memreaddatadecoder(
        .inData( readData ),
        .offset( physMemAdd[1:0] ),
        .bitExt( memoryBitExtend ),
        .dataSize( memoryDataSize ),
        .outData( decodedReadData )
    );

    MemWriteDataEncoder memwritedataencoder(
        .inData( rfData2 ),
        .offset( physMemAdd[1:0] ),
        .memWrite( memWrite ),
        .dataSize( memoryDataSize ),
        .outData( encodedWriteData ),
        .encMW( encMemoryWrite )
    );

    VGATextCard vgaTextCard(
        .vclk( vClk ),
        .clk( fClk ),
        .rst( reset ),
        .en( memEnable[1] ),
        .memWrite( encMemoryWrite ),
        .addr( physMemAdd[12:2] ),
        .wdata( encodedWriteData ),
        .rdata( vgaReadData ),
        .red( red ),
        .green( green ),
        .blue( blue ),
        .hsync( hsync ),
        .vsync( vsync )
    );

    BranchResolver resolver(
        .branch( branchCU ),
        .zero ( isZero ),
        .sign ( rfData1[31] ),
        .branchTaken( branchTaken )
    );

    ClockGenerator clkGen(
        .clkIn( clk ),
        .fastClk( fClk ),
        .vgaClk( vClk ),
        .slowClk( sClk )
    );

    MillisCounter msCounter(
        .clk ( clk ),
        .reset ( reset ),
        .counter ( mCounter )
    );

    IOMem io(
        .msCounter ( mCounter ),
        .addr ( physMemAdd[12:2] ),
        .keypad ( keypad ),
        .en ( memEnable[2] ),
        .o ( IOReadData )
    );

endmodule