commit a8060ae2a75aa5eacf4f295679ebbb8089aae813
Author: Marian Mihailescu <[email protected]>
Date:   Mon Oct 28 12:09:49 2019 +1030

    clk: samsung: exynos5420: Preserve CPU clocks configuration during suspend/resume

    Save and restore top PLL related configuration registers for big (APLL)
    and LITTLE (KPLL) cores during suspend/resume cycle. So far, CPU clocks
    were reset to default values after suspend/resume cycle and performance
    after system resume was affected when performance governor has been selected.

    Fixes: 773424326b51 ("clk: samsung: exynos5420: add more registers to restore list")

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 83fc6997effb..430536c7b380 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -165,6 +165,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = {
 	GATE_BUS_CPU,
 	GATE_SCLK_CPU,
 	CLKOUT_CMU_CPU,
+	APLL_CON0,
+	KPLL_CON0,
 	CPLL_CON0,
 	DPLL_CON0,
 	EPLL_CON0,