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Dec 25th, 2020
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  1. 0x0001 - pwm id 0x00
  2. bl2_stage_init 0xc0
  3. bl2_stage_init 0x02
  4.  
  5. sdio debug board detected
  6. L0:00000000
  7. L1:00000703
  8. L2:00008067
  9. L3:15000020
  10. S1:00000000
  11. B2:20282000
  12. B1:a0f83180
  13.  
  14. TE: 183583
  15.  
  16. BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  17.  
  18. Board ID = 1
  19. Set cpu clk to 24M
  20. Set clk81 to 24M
  21. Use GP1_pll as DSU clk.
  22. DSU clk: 1200 Mhz
  23. CPU clk: 1200 MHz
  24. Set clk81 to 166.6M
  25. eMMC boot @ 0
  26. sw8 s
  27. board id: 1
  28. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  29. fw parse done
  30. PIEI prepare done
  31. 00000000
  32. emmc switch 1 ok
  33. ddr saved addr:00016000
  34. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  35. 00000000
  36. emmc switch 0 ok
  37. fastboot data verify
  38. result: 255
  39. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  40. DDR4 probe
  41.  
  42. LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  43. ddr clk to 1320MHz
  44.  
  45. dmc_version 0001
  46. Check phy result
  47. INFO : End of initialization
  48. INFO : End of read enable training
  49. INFO : End of fine write leveling
  50. INFO : ERROR : Training has failed!
  51. 1D training failed
  52. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  53. DDR4 probe
  54. ddr clk to 1320MHz
  55.  
  56. dmc_version 0001
  57. Check phy result
  58. INFO : End of initialization
  59. INFO : End of read enable training
  60. INFO : End of fine write leveling
  61. INFO : ERROR : Training has failed!
  62. 1D training failed
  63. Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
  64. DDR3 probe
  65. ddr clk to 648MHz
  66.  
  67. dmc_version 0001
  68. Check phy result
  69. INFO : End of initialization
  70. INFO : ERROR : Training has failed!
  71. 1D training failed
  72. Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
  73. DDR3 probe
  74. ddr clk to 648MHz
  75.  
  76. dmc_version 0001
  77. Check phy result
  78. INFO : End of initialization
  79. INFO : End of read enable training
  80. INFO : End of fine write leveling
  81. INFO : End of read dq deskew training
  82. INFO : End of MPR read delay center optimization
  83. INFO : End of Write leveling coarse delay
  84. INFO : End of write delay center optimization
  85. INFO : End of read delay center optimization
  86. INFO : End of max read latency training
  87. INFO : Training has run successfully!
  88. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
  89. 1D training succeed
  90. auto size-- 65535DDR cs0 size: 2048MB
  91. DDR cs1 size: 0MB
  92. DMC_DDR_CTRL: 0000002cDDR size: 2048MB
  93. cs0 DataBus test pass
  94. cs0 AddrBus test pass
  95.  
  96. non-sec scramble use zero key
  97. ddr scramble enabled
  98.  
  99. 100bdlr_step_size ps== 451
  100. result report
  101. boot times 0Enable ddr reg access
  102. 00000000
  103. emmc switch 3 ok
  104. Authentication key not yet programmed
  105. get rpmb counter error 0x00000007
  106. 00000000
  107. emmc switch 0 ok
  108. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  109. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
  110. 0.0;M3 CHK:0;cm4_sp_mode 0
  111. [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
  112. OPS=0x01
  113. ring efuse init
  114. 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
  115. [0.014467 Inits done]
  116.  
  117. === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
  118. r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
  119. r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
  120. r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
  121. r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
  122. Precise data bus error, bfar = 4443144
  123. mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
  124.  
  125. =========== Process Stack Contents ===========
  126. 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
  127. 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
  128. 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
  129. 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
  130.  
  131. Rebooting...
  132. ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
  133. V▒▒▒$▒+▒$VW▒,W▒H▒
  134. ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
  135. ▒2ᚊ�j▒▒H▒U▒'▒LNM▒▒4
  136.  
  137. BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  138.  
  139. Board ID = 1
  140. Set cpu clk to 24M
  141. Set clk81 to 24M
  142. Use GP1_pll as DSU clk.
  143. DSU clk: 1200 Mhz
  144. CPU clk: 1200 MHz
  145. Set clk81 to 166.6M
  146. eMMC boot @ 0
  147. sw8 s
  148. board id: 1
  149. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  150. fw parse done
  151. PIEI prepare done
  152. 00000000
  153. emmc switch 1 ok
  154. ddr saved addr:00016000
  155. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  156. 00000000
  157. emmc switch 0 ok
  158. fastboot data verify
  159. result: 255
  160. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  161. DDR4 probe
  162.  
  163. LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  164. ddr clk to 1320MHz
  165.  
  166. dmc_version 0001
  167. Check phy result
  168. INFO : End of initialization
  169. INFO : End of read enable training
  170. INFO : End of fine write leveling
  171. INFO : ERROR : Training has failed!
  172. 1D training failed
  173. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  174. DDR4 probe
  175. ddr clk to 1320MHz
  176.  
  177. dmc_version 0001
  178. Check phy result
  179. INFO : End of initialization
  180. INFO : End of read enable training
  181. INFO : End of fine write leveling
  182. INFO : ERROR : Training has failed!
  183. 1D training failed
  184. Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
  185. DDR3 probe
  186. ddr clk to 648MHz
  187.  
  188. dmc_version 0001
  189. Check phy result
  190. INFO : End of initialization
  191. INFO : ERROR : Training has failed!
  192. 1D training failed
  193. Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
  194. DDR3 probe
  195. ddr clk to 648MHz
  196.  
  197. dmc_version 0001
  198. Check phy result
  199. INFO : End of initialization
  200. INFO : End of read enable training
  201. INFO : End of fine write leveling
  202. INFO : End of read dq deskew training
  203. INFO : End of MPR read delay center optimization
  204. INFO : End of Write leveling coarse delay
  205. INFO : End of write delay center optimization
  206. INFO : End of read delay center optimization
  207. INFO : End of max read latency training
  208. INFO : Training has run successfully!
  209. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
  210. 1D training succeed
  211. auto size-- 65535DDR cs0 size: 2048MB
  212. DDR cs1 size: 0MB
  213. DMC_DDR_CTRL: 0000002cDDR size: 2048MB
  214. cs0 DataBus test pass
  215. cs0 AddrBus test pass
  216.  
  217. non-sec scramble use zero key
  218. ddr scramble enabled
  219.  
  220. 100bdlr_step_size ps== 462
  221. result report
  222. boot times 1Enable ddr reg access
  223. 00000000
  224. emmc switch 3 ok
  225. Authentication key not yet programmed
  226. get rpmb counter error 0x00000007
  227. 00000000
  228. emmc switch 0 ok
  229. Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
  230. Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
  231. bl2z_ptr: 0512d334
  232. img_info->image_base: 05100000
  233. bl2z: ptr: 0512d330, size: 00001e40
  234. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  235. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
  236. 0.0;M3 CHK:0;cm4_sp_mode 0
  237. [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
  238. OPS=0x01
  239. ring efuse init
  240. 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
  241. [1.040401 Inits done]
  242.  
  243. === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
  244. r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
  245. r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
  246. r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
  247. r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
  248. Precise data bus error, bfar = 4443144
  249. mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
  250.  
  251. =========== Process Stack Contents ===========
  252. 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
  253. 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
  254. 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
  255. 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
  256.  
  257. Rebooting...
  258. ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
  259. V▒▒▒$▒+▒$VW▒,W▒H▒
  260. ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
  261. ▒2ᚊ�j▒▒H▒U▒'▒LN▒998
  262.  
  263. BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  264.  
  265. Board ID = 1
  266. Set cpu clk to 24M
  267. Set clk81 to 24M
  268. Use GP1_pll as DSU clk.
  269. DSU clk: 1200 Mhz
  270. CPU clk: 1200 MHz
  271. Set clk81 to 166.6M
  272. eMMC boot @ 0
  273. sw8 s
  274. board id: 1
  275. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  276. fw parse done
  277. PIEI prepare done
  278. 00000000
  279. emmc switch 1 ok
  280. ddr saved addr:00016000
  281. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  282. 00000000
  283. emmc switch 0 ok
  284. fastboot data verify
  285. result: 255
  286. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  287. DDR4 probe
  288.  
  289. LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  290. ddr clk to 1320MHz
  291.  
  292. dmc_version 0001
  293. Check phy result
  294. INFO : End of initialization
  295. INFO : End of read enable training
  296. INFO : End of fine write leveling
  297. INFO : ERROR : Training has failed!
  298. 1D training failed
  299. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  300. DDR4 probe
  301. ddr clk to 1320MHz
  302.  
  303. dmc_version 0001
  304. Check phy result
  305. INFO : End of initialization
  306. INFO : End of read enable training
  307. INFO : End of fine write leveling
  308. INFO : ERROR : Training has failed!
  309. 1D training failed
  310. Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
  311. DDR3 probe
  312. ddr clk to 648MHz
  313.  
  314. dmc_version 0001
  315. Check phy result
  316. INFO : End of initialization
  317. INFO : ERROR : Training has failed!
  318. 1D training failed
  319. Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
  320. DDR3 probe
  321. ddr clk to 648MHz
  322.  
  323. dmc_version 0001
  324. Check phy result
  325. INFO : End of initialization
  326. INFO : End of read enable training
  327. INFO : End of fine write leveling
  328. INFO : End of read dq deskew training
  329. INFO : End of MPR read delay center optimization
  330. INFO : End of Write leveling coarse delay
  331. INFO : End of write delay center optimization
  332. INFO : End of read delay center optimization
  333. INFO : End of max read latency training
  334. INFO : Training has run successfully!
  335. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
  336. 1D training succeed
  337. auto size-- 65535DDR cs0 size: 2048MB
  338. DDR cs1 size: 0MB
  339. DMC_DDR_CTRL: 0000002cDDR size: 2048MB
  340. cs0 DataBus test pass
  341. cs0 AddrBus test pass
  342.  
  343. non-sec scramble use zero key
  344. ddr scramble enabled
  345.  
  346. 100bdlr_step_size ps== 453
  347. result report
  348. boot times 2Enable ddr reg access
  349. 00000000
  350. emmc switch 3 ok
  351. Authentication key not yet programmed
  352. get rpmb counter error 0x00000007
  353. 00000000
  354. emmc switch 0 ok
  355. Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
  356. Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
  357. bl2z_ptr: 0512d334
  358. img_info->image_base: 05100000
  359. bl2z: ptr: 0512d330, size: 00001e40
  360. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  361. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
  362. 0.0;M3 CHK:0;cm4_sp_mode 0
  363. [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
  364. OPS=0x01
  365. ring efuse init
  366. 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
  367. [1.033442 Inits done]
  368.  
  369. === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
  370. r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
  371. r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
  372. r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
  373. r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
  374. Precise data bus error, bfar = 4443144
  375. mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
  376.  
  377. =========== Process Stack Contents ===========
  378. 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
  379. 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
  380. 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
  381. 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
  382.  
  383. Rebooting...
  384. ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
  385. V▒▒▒$▒+▒$VW▒,W▒H▒
  386. ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
  387. ▒2ᚊ�j▒▒H▒U▒'▒LN▒NN▒C▒C▒▒L2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  388.  
  389. Board ID = 1
  390. Set cpu clk to 24M
  391. Set clk81 to 24M
  392. Use GP1_pll as DSU clk.
  393. DSU clk: 1200 Mhz
  394. CPU clk: 1200 MHz
  395. Set clk81 to 166.6M
  396. eMMC boot @ 0
  397. sw8 s
  398. board id: 1
  399. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  400. fw parse done
  401. PIEI prepare done
  402. 00000000
  403. emmc switch 1 ok
  404. ddr saved addr:00016000
  405. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  406. 00000000
  407. emmc switch 0 ok
  408. fastboot data verify
  409. result: 255
  410. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  411. DDR4 probe
  412.  
  413. LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  414. ddr clk to 1320MHz
  415.  
  416. dmc_version 0001
  417. Check phy result
  418. INFO : End of initialization
  419. INFO : End of read enable training
  420. INFO : End of fine write leveling
  421. INFO : ERROR : Training has failed!
  422. 1D training failed
  423. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  424. DDR4 probe
  425. ddr clk to 1320MHz
  426.  
  427. dmc_version 0001
  428. Check phy result
  429. INFO : End of initialization
  430. INFO : End of read enable training
  431. INFO : End of fine write leveling
  432. INFO : ERROR : Training has failed!
  433. 1D training failed
  434. Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
  435. DDR3 probe
  436. ddr clk to 648MHz
  437.  
  438. dmc_version 0001
  439. Check phy result
  440. INFO : End of initialization
  441. INFO : ERROR : Training has failed!
  442. 1D training failed
  443. Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
  444. DDR3 probe
  445. ddr clk to 648MHz
  446.  
  447. dmc_version 0001
  448. Check phy result
  449. INFO : End of initialization
  450. INFO : End of read enable training
  451. INFO : End of fine write leveling
  452. INFO : End of read dq deskew training
  453. INFO : End of MPR read delay center optimization
  454. INFO : End of Write leveling coarse delay
  455. INFO : End of write delay center optimization
  456. INFO : End of read delay center optimization
  457. INFO : End of max read latency training
  458. INFO : Training has run successfully!
  459. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
  460. 1D training succeed
  461. auto size-- 65535DDR cs0 size: 2048MB
  462. DDR cs1 size: 0MB
  463. DMC_DDR_CTRL: 0000002cDDR size: 2048MB
  464. cs0 DataBus test pass
  465. cs0 AddrBus test pass
  466.  
  467. non-sec scramble use zero key
  468. ddr scramble enabled
  469.  
  470. 100bdlr_step_size ps== 448
  471. result report
  472. boot times 3Enable ddr reg access
  473. 00000000
  474. emmc switch 3 ok
  475. Authentication key not yet programmed
  476. get rpmb counter error 0x00000007
  477. 00000000
  478. emmc switch 0 ok
  479. Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
  480. Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
  481. bl2z_ptr: 0512d334
  482. img_info->image_base: 05100000
  483. bl2z: ptr: 0512d330, size: 00001e40
  484. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  485. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
  486. 0.0;M3 CHK:0;cm4_sp_mode 0
  487. [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
  488. OPS=0x01
  489. ring efuse init
  490. 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
  491. [1.036702 Inits done]
  492.  
  493. === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
  494. r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
  495. r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
  496. r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
  497. r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
  498. Precise data bus error, bfar = 4443144
  499. mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
  500.  
  501. =========== Process Stack Contents ===========
  502. 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
  503. 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
  504. 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
  505. 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
  506.  
  507. Rebooting...
  508. 0x0001 - pwm id 0x00
  509. bl2_stage_init 0xc0
  510. bl2_stage_init 0x02
  511.  
  512. sdio debug board detected
  513. L0:00000000
  514. L1:00000703
  515. L2:00008067
  516. L3:15000020
  517. S1:00000000
  518. B2:20282000
  519. B1:a0f83180
  520.  
  521. TE: 187019
  522.  
  523. BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  524.  
  525. Board ID = 1
  526. Set cpu clk to 24M
  527. Set clk81 to 24M
  528. Use GP1_pll as DSU clk.
  529. DSU clk: 1200 Mhz
  530. CPU clk: 1200 MHz
  531. Set clk81 to 166.6M
  532. eMMC boot @ 0
  533. sw8 s
  534. board id: 1
  535. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  536. fw parse done
  537. PIEI prepare done
  538. 00000000
  539. emmc switch 1 ok
  540. ddr saved addr:00016000
  541. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  542. 00000000
  543. emmc switch 0 ok
  544. fastboot data verify
  545. result: 255
  546. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  547. DDR4 probe
  548.  
  549. LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  550. ddr clk to 1320MHz
  551.  
  552. dmc_version 0001
  553. Check phy result
  554. INFO : End of initialization
  555. INFO : End of read enable training
  556. INFO : End of fine write leveling
  557. INFO : ERROR : Training has failed!
  558. 1D training failed
  559. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  560. DDR4 probe
  561. ddr clk to 1320MHz
  562.  
  563. dmc_version 0001
  564. Check phy result
  565. INFO : End of initialization
  566. INFO : End of read enable training
  567. INFO : End of fine write leveling
  568. INFO : ERROR : Training has failed!
  569. 1D training failed
  570. Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
  571. DDR3 probe
  572. ddr clk to 648MHz
  573.  
  574. dmc_version 0001
  575. Check phy result
  576. INFO : End of initialization
  577. INFO : ERROR : Training has failed!
  578. 1D training failed
  579. Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
  580. DDR3 probe
  581. ddr clk to 648MHz
  582.  
  583. dmc_version 0001
  584. Check phy result
  585. INFO : End of initialization
  586. INFO : End of read enable training
  587. INFO : End of fine write leveling
  588. INFO : End of read dq deskew training
  589. INFO : End of MPR read delay center optimization
  590. INFO : End of Write leveling coarse delay
  591. INFO : End of write delay center optimization
  592. INFO : End of read delay center optimization
  593. INFO : End of max read latency training
  594. INFO : Training has run successfully!
  595. dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
  596. 1D training succeed
  597. auto size-- 65535DDR cs0 size: 2048MB
  598. DDR cs1 size: 0MB
  599. DMC_DDR_CTRL: 0000002cDDR size: 2048MB
  600. cs0 DataBus test pass
  601. cs0 AddrBus test pass
  602.  
  603. non-sec scramble use zero key
  604. ddr scramble enabled
  605.  
  606. 100bdlr_step_size ps== 453
  607. result report
  608. boot times 4Enable ddr reg access
  609. 00000000
  610. emmc switch 3 ok
  611. Authentication key not yet programmed
  612. get rpmb counter error 0x00000007
  613. 00000000
  614. emmc switch 0 ok
  615. Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
  616. Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
  617. bl2z_ptr: 0512d334
  618. img_info->image_base: 05100000
  619. bl2z: ptr: 0512d330, size: 00001e40
  620. Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
  621. Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
  622. 0.0;M3 CHK:0;cm4_sp_mode 0
  623. [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
  624. OPS=0x01
  625. ring efuse init
  626. 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
  627. [1.051139 Inits done]
  628.  
  629. === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
  630. r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
  631. r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
  632. r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
  633. r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
  634. Precise data bus error, bfar = 4443144
  635. mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
  636.  
  637. =========== Process Stack Contents ===========
  638. 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
  639. 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
  640. 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
  641. 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
  642.  
  643. Rebooting...
  644. ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
  645. V▒▒▒$▒+▒$VW▒,W▒H▒
  646. ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
  647. ▒2ᚊ�j▒▒H▒U▒'▒LN▒389
  648.  
  649. BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  650.  
  651. Board ID = 1
  652. Set cpu clk to 24M
  653. Set clk81 to 24M
  654. Use GP1_pll as DSU clk.
  655. DSU clk: 1200 Mhz
  656. CPU clk: 1200 MHz
  657. Set clk81 to 166.6M
  658. eMMC boot @ 0
  659. sw8 s
  660. board id: 1
  661. Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
  662. fw parse done
  663. PIEI prepare done
  664. 00000000
  665. emmc switch 1 ok
  666. ddr saved addr:00016000
  667. Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
  668. 00000000
  669. emmc switch 0 ok
  670. fastboot data verify
  671. result: 255
  672. Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
  673. DDR4 probe
  674.  
  675. LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
  676. ddr clk to 1320MHz
  677.  
  678. dmc_version 0001
  679. Check phy result
  680. INFO : End of initialization
  681. INFO : End of read enable training
  682. INFO : End of fine write leveling
  683. INFO : ERROR : Training has failed!
  684. 1D training failed
  685. Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
  686. DDR4 probe
  687. ddr clk to 1320MHz
  688.  
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