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- 0x0001 - pwm id 0x00
- bl2_stage_init 0xc0
- bl2_stage_init 0x02
- sdio debug board detected
- L0:00000000
- L1:00000703
- L2:00008067
- L3:15000020
- S1:00000000
- B2:20282000
- B1:a0f83180
- TE: 183583
- BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- eMMC boot @ 0
- sw8 s
- board id: 1
- Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- DDR4 probe
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of Write leveling coarse delay
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
- 1D training succeed
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 0MB
- DMC_DDR_CTRL: 0000002cDDR size: 2048MB
- cs0 DataBus test pass
- cs0 AddrBus test pass
- non-sec scramble use zero key
- ddr scramble enabled
- 100bdlr_step_size ps== 451
- result report
- boot times 0Enable ddr reg access
- 00000000
- emmc switch 3 ok
- Authentication key not yet programmed
- get rpmb counter error 0x00000007
- 00000000
- emmc switch 0 ok
- Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
- OPS=0x01
- ring efuse init
- 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
- [0.014467 Inits done]
- === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
- r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
- r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
- r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
- r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
- Precise data bus error, bfar = 4443144
- mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
- =========== Process Stack Contents ===========
- 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
- 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
- 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
- 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
- Rebooting...
- ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
- V▒▒▒$▒+▒$VW▒,W▒H▒
- ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
- ▒2ᚊ�j▒▒H▒U▒'▒LNM▒▒4
- BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- eMMC boot @ 0
- sw8 s
- board id: 1
- Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- DDR4 probe
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of Write leveling coarse delay
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
- 1D training succeed
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 0MB
- DMC_DDR_CTRL: 0000002cDDR size: 2048MB
- cs0 DataBus test pass
- cs0 AddrBus test pass
- non-sec scramble use zero key
- ddr scramble enabled
- 100bdlr_step_size ps== 462
- result report
- boot times 1Enable ddr reg access
- 00000000
- emmc switch 3 ok
- Authentication key not yet programmed
- get rpmb counter error 0x00000007
- 00000000
- emmc switch 0 ok
- Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
- Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
- bl2z_ptr: 0512d334
- img_info->image_base: 05100000
- bl2z: ptr: 0512d330, size: 00001e40
- Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
- OPS=0x01
- ring efuse init
- 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
- [1.040401 Inits done]
- === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
- r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
- r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
- r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
- r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
- Precise data bus error, bfar = 4443144
- mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
- =========== Process Stack Contents ===========
- 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
- 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
- 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
- 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
- Rebooting...
- ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
- V▒▒▒$▒+▒$VW▒,W▒H▒
- ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
- ▒2ᚊ�j▒▒H▒U▒'▒LN▒998
- BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- eMMC boot @ 0
- sw8 s
- board id: 1
- Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- DDR4 probe
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of Write leveling coarse delay
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
- 1D training succeed
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 0MB
- DMC_DDR_CTRL: 0000002cDDR size: 2048MB
- cs0 DataBus test pass
- cs0 AddrBus test pass
- non-sec scramble use zero key
- ddr scramble enabled
- 100bdlr_step_size ps== 453
- result report
- boot times 2Enable ddr reg access
- 00000000
- emmc switch 3 ok
- Authentication key not yet programmed
- get rpmb counter error 0x00000007
- 00000000
- emmc switch 0 ok
- Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
- Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
- bl2z_ptr: 0512d334
- img_info->image_base: 05100000
- bl2z: ptr: 0512d330, size: 00001e40
- Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
- OPS=0x01
- ring efuse init
- 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
- [1.033442 Inits done]
- === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
- r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
- r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
- r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
- r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
- Precise data bus error, bfar = 4443144
- mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
- =========== Process Stack Contents ===========
- 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
- 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
- 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
- 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
- Rebooting...
- ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
- V▒▒▒$▒+▒$VW▒,W▒H▒
- ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
- ▒2ᚊ�j▒▒H▒U▒'▒LN▒NN▒C▒C▒▒L2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- eMMC boot @ 0
- sw8 s
- board id: 1
- Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- DDR4 probe
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of Write leveling coarse delay
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
- 1D training succeed
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 0MB
- DMC_DDR_CTRL: 0000002cDDR size: 2048MB
- cs0 DataBus test pass
- cs0 AddrBus test pass
- non-sec scramble use zero key
- ddr scramble enabled
- 100bdlr_step_size ps== 448
- result report
- boot times 3Enable ddr reg access
- 00000000
- emmc switch 3 ok
- Authentication key not yet programmed
- get rpmb counter error 0x00000007
- 00000000
- emmc switch 0 ok
- Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
- Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
- bl2z_ptr: 0512d334
- img_info->image_base: 05100000
- bl2z: ptr: 0512d330, size: 00001e40
- Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
- OPS=0x01
- ring efuse init
- 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
- [1.036702 Inits done]
- === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
- r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
- r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
- r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
- r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
- Precise data bus error, bfar = 4443144
- mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
- =========== Process Stack Contents ===========
- 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
- 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
- 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
- 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
- Rebooting...
- 0x0001 - pwm id 0x00
- bl2_stage_init 0xc0
- bl2_stage_init 0x02
- sdio debug board detected
- L0:00000000
- L1:00000703
- L2:00008067
- L3:15000020
- S1:00000000
- B2:20282000
- B1:a0f83180
- TE: 187019
- BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- eMMC boot @ 0
- sw8 s
- board id: 1
- Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- DDR4 probe
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 3. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 4. Board id: 255. Force loop cfg
- DDR3 probe
- ddr clk to 648MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : End of read dq deskew training
- INFO : End of MPR read delay center optimization
- INFO : End of Write leveling coarse delay
- INFO : End of write delay center optimization
- INFO : End of read delay center optimization
- INFO : End of max read latency training
- INFO : Training has run successfully!
- dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):00e4
- 1D training succeed
- auto size-- 65535DDR cs0 size: 2048MB
- DDR cs1 size: 0MB
- DMC_DDR_CTRL: 0000002cDDR size: 2048MB
- cs0 DataBus test pass
- cs0 AddrBus test pass
- non-sec scramble use zero key
- ddr scramble enabled
- 100bdlr_step_size ps== 453
- result report
- boot times 4Enable ddr reg access
- 00000000
- emmc switch 3 ok
- Authentication key not yet programmed
- get rpmb counter error 0x00000007
- 00000000
- emmc switch 0 ok
- Load FIP TMP HDR from eMMC, src: 0x00010200, des: 0x05100000, size: 0x00004000, part: 0
- Load BL31 from eMMC, src: 0x00086200, des: 0x05104000, size: 0x00031170, part: 0
- bl2z_ptr: 0512d334
- img_info->image_base: 05100000
- bl2z: ptr: 0512d330, size: 00001e40
- Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
- Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000f8200, part: 0
- 0.0;M3 CHK:0;cm4_sp_mode 0
- [Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
- OPS=0x01
- ring efuse init
- 2b 0b 01 00 01 1d 10 00 00 06 33 31 50 52 52 50
- [1.051139 Inits done]
- === PROCESS EXCEPTION: 05 ====== xPSR: 01000000 ===
- r0 :00000000 r1 :00000010 r2 :0d300090 r3 :ff7ded7f
- r4 :044430a8 r5 :facfdf1b r6 :11060102 r7 :fffdefff
- r8 :800c311b r9 :ff397fd7 r10:800760c0 r11:7ff7f7ff
- r12:0428490c sp :1000f360 lr :10000a51 pc :1000b802
- Precise data bus error, bfar = 4443144
- mmfs = 8200, shcsr = 70002, hfsr = 0, dfsr = 0
- =========== Process Stack Contents ===========
- 1000f380: 02598000 d70fbeaf 08000282 ff9bfffb
- 1000f390: 0621008b 7efdf77c 22010028 7d6ef4de
- 1000f3a0: 08001a80 eff7feff 012405c1 ff5ffd7d
- 1000f3b0: 51004820 effbffdf c0500060 ffffefbf
- Rebooting...
- ▒▒▒▒▒j▒ݵ▒J▒▒▒▒▒j▒$▒K▒5х▒▒}▒▒▒с▒�▒jR$▒▒▒▒х▒▒}▒▒▒с▒▒▒j▒▒HhV▒
- V▒▒▒$▒+▒$VW▒,W▒H▒
- ▒▒▒▒▒▒▒▒▒j▒▒*҂▒▒▒▒▒▒▒j▒▒J҂▒▒▒�▒▒j▒▒jҊ▒▒▒▒▒▒▒j▒4҂▒▒▒▒▒▒▒j▒$JҒ▒▒�▒▒▒j▒$*▒
- ▒2ᚊ�j▒▒H▒U▒'▒LN▒389
- BL2 Built : 14:57:11, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- Board ID = 1
- Set cpu clk to 24M
- Set clk81 to 24M
- Use GP1_pll as DSU clk.
- DSU clk: 1200 Mhz
- CPU clk: 1200 MHz
- Set clk81 to 166.6M
- eMMC boot @ 0
- sw8 s
- board id: 1
- Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
- fw parse done
- PIEI prepare done
- 00000000
- emmc switch 1 ok
- ddr saved addr:00016000
- Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
- 00000000
- emmc switch 0 ok
- fastboot data verify
- result: 255
- Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
- DDR4 probe
- LPDDR4_PHY_V_0_1_22-Built : 14:57:16, Sep 1 2020. g12a g3c95fed - gongwei.chen@droid11-sz
- ddr clk to 1320MHz
- dmc_version 0001
- Check phy result
- INFO : End of initialization
- INFO : End of read enable training
- INFO : End of fine write leveling
- INFO : ERROR : Training has failed!
- 1D training failed
- Cfg max: 12, cur: 2. Board id: 255. Force loop cfg
- DDR4 probe
- ddr clk to 1320MHz
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