//fibonacci module, version 3.0
module fibonacci(output [15:0]fibval, input rst, input clk);//establish fibval, reset and clock
	wire [15:0] fibval;
	reg [15:0] Reg1; //for first fib value an-1
	reg [16:0] Reg2; //for second an-2, 1 bit higher to allow carryover and to catch potential error without error wire

	initial
		begin
		$monitor("\tFibonacci Value = %d ", fibval);
	end

	always@(posedge clk or negedge rst)
		begin
		if(rst == 0) begin
		Reg1<=0;//establish registers to 0 and 1 by default
		Reg2<=1;
	end
	else if(clk==1)
		begin
		Reg1 <= Reg2;//fibonacci arithmetic
		Reg2 <= Reg2 + Reg1;
		if(Reg2[16] == 1)
			$display("\tValues now Out of Range and Incorrect");//backup error message
		end
	end

	assign fibval = Reg1;

endmodule//end Fibonacci


//Test Bench
module fibonacci_tb; // stimulus for Fibonacci generator
	reg clk, rst;
	wire[15:0] fibval;
	parameter maxFibval=46368;//setting max fib value for 16bits

	// Instantiating the Fibonacci Module of fibo.v
	fibonacci fib(fibval,rst,clk);

	initial forever begin	//starting clock
		clk=0;
		#1;
		clk=1;
		#1;
		if(fibval>=maxFibval) $display("\tNow Out of range of 16 bit fibonacci values");//primary error message
		if(fibval>=maxFibval) $finish; //finish at last possible 16 bit fib number

	end

	initial begin//starting reset
		#1;
		rst=0;
		#1;
		rst=1;

	end

endmodule//end Testbench