library ieee;
use ieee.std_logic_1164.all;

entity counter_test is
end entity;

architecture STRUCT of counter_test is
component COUNTE
	port(x, clk: in std_logic;
	     z: out std_logic_vector(3 downto 0) := (others => '0'));
end component;
signal x, clk: std_logic := '0';
signal z: std_logic_vector(3 downto 0);
begin
	x <= not x after 200 ns;
	clk <= not clk after 10 ns;
	COUNTER: COUNTE port map(x, clk, z);
end architecture;