multiplekser poprawiony

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity multiplekser is
Port(U:in STD_LOGIC;
		clk10: in STD_LOGIC;
		clk1:in STD_LOGIC;
		Sl:in STD_LOGIC;
		U10:in STD_LOGIC;
		x:out STD_LOGIC);
	end multiplekser;
architecture multi of multiplekser is
begin
x<=(not U10 and not Sl and not U)
	or (not U10 and Sl and clk1)
	or (U10 and not Sl and clk10)
	or (U10 and Sl and clk1);
	end multi;